/******************************************************************************
**                                                                           **
** Copyright (C) Infineon Technologies (2013)                                **
**                                                                           **
** All rights reserved.                                                      **
**                                                                           **
** This document contains proprietary information belonging to Infineon      **
** Technologies. Passing on and copying of this document, and communication  **
** of its contents is not permitted without prior written authorization.     **
**                                                                           **
*******************************************************************************
**                                                                           **
**  $FILENAME   : Irq.c $                                                    **
**                                                                           **
**  $CC VERSION : \main\80 $                                                 **
**                                                                           **
**  $DATE       : 2016-06-21 $                                               **
**                                                                           **
**  AUTHOR      : DL-AUTOSAR-Engineering                                     **
**                                                                           **
**  VENDOR      : Infineon Technologies                                      **
**                                                                           **
**  DESCRIPTION : This file contains initisalization of interrupt priority   **
**                and interruptframe based on interrupt category.            **
**                                                                           **
**  MAY BE CHANGED BY USER [yes/no]: Yes                                     **
**                                                                           **
******************************************************************************/

/*******************************************************************************
**                      Includes                                              **
*******************************************************************************/

/* Inclusion of Tasking sfr file */
#include "IfxSrc_reg.h"

/*Include Irq Module header file*/
#include "Irq.h"

/* Inclusion of Global Header File */
#include "Mcal.h"

#include "Mcal_Options.h"

/*******************************************************************************
**                      Private Type Definitions                              **
*******************************************************************************/

/* Set CLRR to clear SRR bit and disable SRE bit */
#define IRQ_DISABLE_CLEAR_SRC     (0x02000000U)

/*******************************************************************************
**                      Private Function Declarations                         **
*******************************************************************************/
#if (IFX_MCAL_USED == STD_ON)
#define IRQ_START_SEC_CODE
#include "MemMap.h"
#else
#define IFX_IRQ_START_SEC_CODE_ASIL_B
#include "Ifx_MemMap.h"
#endif

#if (IFX_MCAL_USED == STD_ON)

#if (IRQ_ASCLIN_EXIST == STD_ON)
static void Irq_ClearAsclinIntFlags(void);
#endif

#if (IRQ_CCU6_EXIST == STD_ON)
static void Irq_ClearCcu6IntFlags (void);
#endif

#if (IRQ_GPT_EXIST == STD_ON)
static void Irq_ClearGptIntFlags (void);
#endif

#if (IRQ_GTM_EXIST == STD_ON)
static void Irq_ClearGtmIntFlags (void);
#endif

#if (IRQ_CAN_EXIST == STD_ON)
static void Irq_ClearCanIntFlags (void);
#endif

#if ((IRQ_HSM0_EXIST == STD_ON) || (IRQ_HSM1_EXIST == STD_ON))
static void Irq_ClearHsmIntFlags (void);
#endif

#if (IRQ_GPSRGROUP_EXIST == STD_ON)
static void Irq_ClearGpsrGroupIntFlags (void);
#endif

#if (IRQ_QSPI_EXIST == STD_ON)
static void Irq_ClearSpiIntFlags (void);
#endif

#if (IRQ_ADC_EXIST == STD_ON)
static void Irq_ClearAdcIntFlags (void);
#endif

#if (IRQ_DSADC_EXIST == STD_ON)
static void Irq_ClearDsadcIntFlags (void);
#endif

#if (IRQ_MSC_EXIST == STD_ON)
static void Irq_ClearMscIntFlags (void);
#endif

#if (IRQ_FLEXRAY_EXIST == STD_ON)
static void Irq_ClearFlexrayIntFlags (void);
#endif

#if (IRQ_ETH_EXIST == STD_ON)
static void Irq_ClearEthernetIntFlags (void);
#endif

#if (IRQ_DMA_EXIST == STD_ON)
static void Irq_ClearDmaIntFlags (void);
#endif

#if (IRQ_STM_EXIST == STD_ON)
static void Irq_ClearStmIntFlags (void);
#endif

#if (IRQ_SCU_EXIST == STD_ON)
static void Irq_ClearScuIntFlags(void);
#endif

#if (IRQ_PMU0_EXIST == STD_ON)
static void Irq_ClearPmuIntFlags (void);
#endif

#if (IRQ_SENT_EXIST == STD_ON)
static void Irq_ClearSentIntFlags (void);
#endif

#if (IRQ_I2C_EXIST == STD_ON)
static void Irq_ClearI2cIntFlags (void);
#endif

#if (IRQ_HSSL_EXIST == STD_ON)
static void Irq_ClearHsslIntFlags(void);
#endif

#endif /* (IFX_MCAL_USED == STD_ON) */

#if (IFX_MCAL_USED == STD_ON)
#define IRQ_STOP_SEC_CODE
#include "MemMap.h"
#else
#define IFX_IRQ_STOP_SEC_CODE_ASIL_B
#include "Ifx_MemMap.h"
#endif
/*******************************************************************************
**                      Global Constant Definitions                           **
*******************************************************************************/

/*******************************************************************************
**                      Global Variable Definitions                           **
*******************************************************************************/

/*******************************************************************************
**                      Private Constant Definitions                          **
*******************************************************************************/

/*******************************************************************************
**                      Private Variable Definitions                          **
*******************************************************************************/
#if (IFX_MCAL_USED == STD_ON)
#define IRQ_START_SEC_CODE
#include "MemMap.h"
#else
#define IFX_IRQ_START_SEC_CODE_ASIL_B
#include "Ifx_MemMap.h"
#endif
/*******************************************************************************
**                      Private Function Definitions                          **
*******************************************************************************/

#if (IFX_MCAL_USED == STD_ON)

#if (IRQ_ASCLIN_EXIST == STD_ON)
static void Irq_ClearAsclinIntFlags(void)
{
  /* Set CLRR to clear SRR bit and disable SRE bit */
  #if (IRQ_ASCLIN0_EXIST == STD_ON)
  SRC_ASCLIN0TX.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_ASCLIN0RX.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_ASCLIN0ERR.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_ASCLIN1_EXIST == STD_ON)
  SRC_ASCLIN1TX.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_ASCLIN1RX.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_ASCLIN1ERR.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_ASCLIN2_EXIST == STD_ON)
  SRC_ASCLIN2TX.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_ASCLIN2RX.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_ASCLIN2ERR.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_ASCLIN3_EXIST == STD_ON)
  SRC_ASCLIN3TX.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_ASCLIN3RX.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_ASCLIN3ERR.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

}
#endif

#if (IRQ_CCU6_EXIST == STD_ON)
static void Irq_ClearCcu6IntFlags (void)
{
  /* Set CLRR to clear SRR bit and disable SRE bit */
  #if (IRQ_CCU60_EXIST == STD_ON)
  SRC_CCU60SR0.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_CCU60SR1.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_CCU60SR2.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_CCU60SR3.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_CCU61_EXIST == STD_ON)
  SRC_CCU61SR0.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_CCU61SR1.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_CCU61SR2.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_CCU61SR3.U = IRQ_DISABLE_CLEAR_SRC;
  #endif  
}
#endif

#if (IRQ_GPT_EXIST == STD_ON)
static void Irq_ClearGptIntFlags (void)
{
  /* Set CLRR to clear SRR bit and disable SRE bit */
  #if (IRQ_GPT120_EXIST == STD_ON)
  SRC_GPT120CIRQ.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GPT120T2.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GPT120T3.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GPT120T4.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GPT120T5.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GPT120T6.U = IRQ_DISABLE_CLEAR_SRC;
  #endif  
}
#endif

#if (IRQ_GTM_EXIST == STD_ON)
static void Irq_ClearGtmIntFlags (void)
{
  /* Set CLRR to clear SRR bit and disable SRE bit */
  #if (IRQ_GTM_AEI_EXIST == STD_ON)
  SRC_GTMAEIIRQ.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_GTM_ARU_EXIST == STD_ON)
  SRC_GTMARUIRQ0.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMARUIRQ1.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMARUIRQ2.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_GTM_BRC_EXIST == STD_ON)
  SRC_GTMBRCIRQ.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_GTM_CMP_EXIST == STD_ON)
  SRC_GTMCMPIRQ.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_GTM_SPE_EXIST == STD_ON)

  #if (IRQ_GTM_SPE0_EXIST == STD_ON)
  SRC_GTMSPE0IRQ.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_GTM_SPE1_EXIST == STD_ON)
  SRC_GTMSPE1IRQ.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_GTM_SPE2_EXIST == STD_ON)
  SRC_GTMSPE2IRQ.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_GTM_SPE3_EXIST == STD_ON)
  SRC_GTMSPE3IRQ.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #endif

  #if (IRQ_GTM_PSM0_EXIST == STD_ON)
  SRC_GTMPSM00.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMPSM01.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMPSM02.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMPSM03.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMPSM04.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMPSM05.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMPSM06.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMPSM07.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_GTM_PSM1_EXIST == STD_ON)
  SRC_GTMPSM10.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMPSM11.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMPSM12.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMPSM13.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMPSM14.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMPSM15.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMPSM16.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMPSM17.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_GTM_DPLL_EXIST == STD_ON)
  SRC_GTMDPLL0.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMDPLL1.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMDPLL2.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMDPLL3.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMDPLL4.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMDPLL5.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMDPLL6.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMDPLL7.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMDPLL8.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMDPLL9.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMDPLL10.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMDPLL11.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMDPLL12.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMDPLL13.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMDPLL14.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMDPLL15.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMDPLL16.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMDPLL17.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMDPLL18.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMDPLL19.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMDPLL20.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMDPLL21.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMDPLL22.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMDPLL23.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMDPLL24.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMDPLL25.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMDPLL26.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_GTM_ERR_EXIST == STD_ON)
  SRC_GTMERR.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_GTM_TIM0_EXIST == STD_ON)
  SRC_GTMTIM00.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMTIM01.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMTIM02.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMTIM03.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMTIM04.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMTIM05.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMTIM06.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMTIM07.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_GTM_TIM1_EXIST == STD_ON)
  SRC_GTMTIM10.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMTIM11.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMTIM12.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMTIM13.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMTIM14.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMTIM15.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMTIM16.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMTIM17.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_GTM_TIM2_EXIST == STD_ON)
  SRC_GTMTIM20.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMTIM21.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMTIM22.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMTIM23.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMTIM24.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMTIM25.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMTIM26.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMTIM27.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_GTM_TIM3_EXIST == STD_ON)
  SRC_GTMTIM30.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMTIM31.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMTIM32.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMTIM33.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMTIM34.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMTIM35.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMTIM36.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMTIM37.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_GTM_TIM4_EXIST == STD_ON)
  SRC_GTMTIM40.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMTIM41.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMTIM42.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMTIM43.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMTIM44.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMTIM45.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMTIM46.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMTIM47.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_GTM_TIM5_EXIST == STD_ON)
  SRC_GTMTIM50.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMTIM51.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMTIM52.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMTIM53.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMTIM54.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMTIM55.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMTIM56.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMTIM57.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_GTM_MCS0_EXIST == STD_ON)
  SRC_GTMMCS00.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMMCS01.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMMCS02.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMMCS03.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMMCS04.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMMCS05.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMMCS06.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMMCS07.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_GTM_MCS1_EXIST == STD_ON)
  SRC_GTMMCS10.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMMCS11.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMMCS12.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMMCS13.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMMCS14.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMMCS15.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMMCS16.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMMCS17.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_GTM_MCS2_EXIST == STD_ON)
  SRC_GTMMCS20.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMMCS21.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMMCS22.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMMCS23.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMMCS24.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMMCS25.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMMCS26.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMMCS27.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_GTM_MCS3_EXIST == STD_ON)
  SRC_GTMMCS30.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMMCS31.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMMCS32.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMMCS33.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMMCS34.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMMCS35.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMMCS36.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMMCS37.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_GTM_MCS4_EXIST == STD_ON)
  SRC_GTMMCS40.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMMCS41.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMMCS42.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMMCS43.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMMCS44.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMMCS45.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMMCS46.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMMCS47.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_GTM_MCS5_EXIST == STD_ON)
  SRC_GTMMCS50.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMMCS51.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMMCS52.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMMCS53.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMMCS54.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMMCS55.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMMCS56.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMMCS57.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_GTM_TOM0_EXIST == STD_ON)
  SRC_GTMTOM00.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMTOM01.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMTOM02.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMTOM03.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMTOM04.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMTOM05.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMTOM06.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMTOM07.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_GTM_TOM1_EXIST == STD_ON)
  SRC_GTMTOM10.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMTOM11.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMTOM12.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMTOM13.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMTOM14.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMTOM15.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMTOM16.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMTOM17.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_GTM_TOM2_EXIST == STD_ON)
  SRC_GTMTOM20.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMTOM21.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMTOM22.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMTOM23.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMTOM24.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMTOM25.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMTOM26.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMTOM27.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_GTM_TOM3_EXIST == STD_ON)
  SRC_GTMTOM30.U  = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMTOM31.U  = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMTOM32.U  = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMTOM33.U  = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMTOM34.U  = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMTOM35.U  = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMTOM36.U  = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMTOM37.U  = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_GTM_TOM4_EXIST == STD_ON)
  SRC_GTMTOM40.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMTOM41.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMTOM42.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMTOM43.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMTOM44.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMTOM45.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMTOM46.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMTOM47.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_GTM_ATOM0_EXIST == STD_ON)
  SRC_GTMATOM00.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMATOM01.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMATOM02.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMATOM03.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_GTM_ATOM1_EXIST == STD_ON)
  SRC_GTMATOM10.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMATOM11.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMATOM12.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMATOM13.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_GTM_ATOM2_EXIST == STD_ON)
  SRC_GTMATOM20.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMATOM21.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMATOM22.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMATOM23.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_GTM_ATOM3_EXIST == STD_ON)
  SRC_GTMATOM30.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMATOM31.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMATOM32.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMATOM33.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_GTM_ATOM4_EXIST == STD_ON)
  SRC_GTMATOM40.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMATOM41.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMATOM42.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMATOM43.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_GTM_ATOM5_EXIST == STD_ON)
  SRC_GTMATOM50.U  = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMATOM51.U  = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMATOM52.U  = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMATOM53.U  = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_GTM_ATOM6_EXIST == STD_ON)
  SRC_GTMATOM60.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMATOM61.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMATOM62.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMATOM63.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_GTM_ATOM7_EXIST == STD_ON)
  SRC_GTMATOM70.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMATOM71.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMATOM72.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMATOM73.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_GTM_ATOM8_EXIST == STD_ON)
  SRC_GTMATOM80.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMATOM81.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMATOM82.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GTMATOM83.U = IRQ_DISABLE_CLEAR_SRC;
  #endif
}
#endif

#if (IRQ_CAN_EXIST == STD_ON)
static void Irq_ClearCanIntFlags (void)
{
  /* Set CLRR to clear SRR bit and disable SRE bit */
  #if (IRQ_CAN0_EXIST == STD_ON)
  SRC_CANINT0.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_CAN1_EXIST == STD_ON)
  SRC_CANINT1.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_CAN2_EXIST == STD_ON)
  SRC_CANINT2.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_CAN3_EXIST == STD_ON)
  SRC_CANINT3.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_CAN4_EXIST == STD_ON)
  SRC_CANINT4.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_CAN5_EXIST == STD_ON)
  SRC_CANINT5.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_CAN6_EXIST == STD_ON)
  SRC_CANINT6.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_CAN7_EXIST == STD_ON)
  SRC_CANINT7.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_CAN8_EXIST == STD_ON)
  SRC_CANINT8.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_CAN9_EXIST == STD_ON)
  SRC_CANINT9.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_CAN10_EXIST == STD_ON)
  SRC_CANINT10.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_CAN11_EXIST == STD_ON)
  SRC_CANINT11.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_CAN12_EXIST == STD_ON)
  SRC_CANINT12.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_CAN13_EXIST == STD_ON)
  SRC_CANINT13.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_CAN14_EXIST == STD_ON)
  SRC_CANINT14.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_CAN15_EXIST == STD_ON)
  SRC_CANINT15.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_CAN16_EXIST == STD_ON)
  SRC_CANRINT0.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_CAN17_EXIST == STD_ON)
  SRC_CANRINT1.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_CAN18_EXIST == STD_ON)
  SRC_CANRINT2.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_CAN19_EXIST == STD_ON)
  SRC_CANRINT3.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_CAN20_EXIST == STD_ON)
  SRC_CANRINT4.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_CAN21_EXIST == STD_ON)
  SRC_CANRINT5.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_CAN22_EXIST == STD_ON)
  SRC_CANRINT6.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_CAN23_EXIST == STD_ON)
  SRC_CANRINT7.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

}
#endif

#if ((IRQ_HSM0_EXIST == STD_ON) || (IRQ_HSM1_EXIST == STD_ON))
static void Irq_ClearHsmIntFlags (void)
{
  #if (IRQ_HSM0_EXIST == STD_ON)
  SRC_HSM0.U = IRQ_DISABLE_CLEAR_SRC;
  #endif
  #if (IRQ_HSM1_EXIST == STD_ON)
  SRC_HSM1.U = IRQ_DISABLE_CLEAR_SRC;
  #endif
}
#endif

#if (IRQ_GPSRGROUP_EXIST == STD_ON)
static void Irq_ClearGpsrGroupIntFlags (void)
{
  /* Set CLRR to clear SRR bit and disable SRE bit */
  #if (IRQ_GPSRGROUP0_EXIST == STD_ON)
  SRC_GPSR00.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GPSR01.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GPSR02.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GPSR03.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_GPSRGROUP1_EXIST == STD_ON)
  SRC_GPSR10.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GPSR11.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GPSR12.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GPSR13.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_GPSRGROUP2_EXIST == STD_ON)
  SRC_GPSR20.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GPSR21.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GPSR22.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_GPSR23.U = IRQ_DISABLE_CLEAR_SRC;
  #endif
}
#endif

#if (IRQ_QSPI_EXIST == STD_ON)
static void Irq_ClearSpiIntFlags (void)
{
  /* Set CLRR to clear SRR bit and disable SRE bit */
  #if (IRQ_QSPI0_EXIST == STD_ON)
  SRC_QSPI0TX.U  = IRQ_DISABLE_CLEAR_SRC;
  SRC_QSPI0RX.U  = IRQ_DISABLE_CLEAR_SRC;
  SRC_QSPI0ERR.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_QSPI0PT.U  = IRQ_DISABLE_CLEAR_SRC;
  SRC_QSPI0U.U   = IRQ_DISABLE_CLEAR_SRC; 
  #endif
  
  #if (IRQ_QSPI1_EXIST == STD_ON)
  SRC_QSPI1TX.U  = IRQ_DISABLE_CLEAR_SRC;
  SRC_QSPI1RX.U  = IRQ_DISABLE_CLEAR_SRC;
  SRC_QSPI1ERR.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_QSPI1PT.U  = IRQ_DISABLE_CLEAR_SRC;
  SRC_QSPI1U.U   = IRQ_DISABLE_CLEAR_SRC;
  #endif
  
  #if (IRQ_QSPI2_EXIST == STD_ON)
  SRC_QSPI2TX.U  = IRQ_DISABLE_CLEAR_SRC;
  SRC_QSPI2RX.U  = IRQ_DISABLE_CLEAR_SRC;
  SRC_QSPI2ERR.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_QSPI2PT.U  = IRQ_DISABLE_CLEAR_SRC;
  #if (IRQ_QSPI_HC_SRN_EXIST == STD_ON)
  SRC_QSPI2HC.U  = IRQ_DISABLE_CLEAR_SRC;
  #endif /* (IRQ_QSPI_HC_SRN_EXIST == STD_ON) */
  SRC_QSPI2U.U   = IRQ_DISABLE_CLEAR_SRC;
  #endif
  
  #if (IRQ_QSPI3_EXIST == STD_ON)
  SRC_QSPI3TX.U  = IRQ_DISABLE_CLEAR_SRC;
  SRC_QSPI3RX.U  = IRQ_DISABLE_CLEAR_SRC;
  SRC_QSPI3ERR.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_QSPI3PT.U  = IRQ_DISABLE_CLEAR_SRC;
  #if (IRQ_QSPI_HC_SRN_EXIST == STD_ON)
  SRC_QSPI3HC.U  = IRQ_DISABLE_CLEAR_SRC;
  #endif /* (IRQ_QSPI_HC_SRN_EXIST == STD_ON) */
  SRC_QSPI3U.U   = IRQ_DISABLE_CLEAR_SRC;
  #endif
  
  #if (IRQ_QSPI4_EXIST == STD_ON)
  SRC_QSPI4TX.U  = IRQ_DISABLE_CLEAR_SRC;
  SRC_QSPI4RX.U  = IRQ_DISABLE_CLEAR_SRC;
  SRC_QSPI4ERR.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_QSPI4PT.U  = IRQ_DISABLE_CLEAR_SRC;



  SRC_QSPI4U.U   = IRQ_DISABLE_CLEAR_SRC;
  #endif
  
  #if (IRQ_QSPI5_EXIST == STD_ON)
  SRC_QSPI5TX.U  = IRQ_DISABLE_CLEAR_SRC;
  SRC_QSPI5RX.U  = IRQ_DISABLE_CLEAR_SRC;
  SRC_QSPI5ERR.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_QSPI5PT.U  = IRQ_DISABLE_CLEAR_SRC;



  SRC_QSPI5U.U   = IRQ_DISABLE_CLEAR_SRC;
  #endif
  
}
#endif

#if (IRQ_ADC_EXIST == STD_ON)
static void Irq_ClearAdcIntFlags (void)
{
  /* Set CLRR to clear SRR bit and disable SRE bit */
  #if (IRQ_ADC0_EXIST == STD_ON)
  SRC_VADCG0SR0.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_VADCG0SR1.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_VADCG0SR2.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_VADCG0SR3.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_ADC1_EXIST == STD_ON)
  SRC_VADCG1SR0.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_VADCG1SR1.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_VADCG1SR2.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_VADCG1SR3.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_ADC2_EXIST == STD_ON)
  SRC_VADCG2SR0.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_VADCG2SR1.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_VADCG2SR2.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_VADCG2SR3.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_ADC3_EXIST == STD_ON)
  SRC_VADCG3SR0.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_VADCG3SR1.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_VADCG3SR2.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_VADCG3SR3.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_ADC4_EXIST == STD_ON)
  SRC_VADCG4SR0.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_VADCG4SR1.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_VADCG4SR2.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_VADCG4SR3.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_ADC5_EXIST == STD_ON)
  SRC_VADCG5SR0.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_VADCG5SR1.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_VADCG5SR2.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_VADCG5SR3.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_ADC6_EXIST == STD_ON)
  SRC_VADCG6SR0.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_VADCG6SR1.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_VADCG6SR2.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_VADCG6SR3.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_ADC7_EXIST == STD_ON)
  SRC_VADCG7SR0.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_VADCG7SR1.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_VADCG7SR2.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_VADCG7SR3.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_ADC8_EXIST == STD_ON)
  SRC_VADCG8SR0.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_VADCG8SR1.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_VADCG8SR2.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_VADCG8SR3.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_ADC9_EXIST == STD_ON)
  SRC_VADCG9SR0.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_VADCG9SR1.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_VADCG9SR2.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_VADCG9SR3.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_ADC10_EXIST == STD_ON)
  SRC_VADCG10SR0.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_VADCG10SR1.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_VADCG10SR2.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_VADCG10SR3.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_ADCCG0_EXIST == STD_ON)
  SRC_VADCCG0SR0.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_VADCCG0SR1.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_VADCCG0SR2.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_VADCCG0SR3.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_ADCCG1_EXIST == STD_ON)
  SRC_VADCCG1SR0.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_VADCCG1SR1.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_VADCCG1SR2.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_VADCCG1SR3.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

}
#endif

#if (IRQ_DSADC_EXIST == STD_ON)
static void Irq_ClearDsadcIntFlags (void)
{
  /* Set CLRR to clear SRR bit and disable SRE bit */
  #if (IRQ_DSADC_A0_EXIST == STD_ON)
  SRC_DSADCSRA0.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_DSADC_A1_EXIST == STD_ON)
  SRC_DSADCSRA1.U = IRQ_DISABLE_CLEAR_SRC;
  #endif
  
  #if (IRQ_DSADC_A2_EXIST == STD_ON)
  SRC_DSADCSRA2.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_DSADC_A3_EXIST == STD_ON)
  SRC_DSADCSRA3.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_DSADC_A4_EXIST == STD_ON)
  SRC_DSADCSRA4.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_DSADC_A5_EXIST == STD_ON)
  SRC_DSADCSRA5.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_DSADC_A6_EXIST == STD_ON)
  SRC_DSADCSRA6.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_DSADC_A7_EXIST == STD_ON)
  SRC_DSADCSRA7.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_DSADC_A8_EXIST == STD_ON)
  SRC_DSADCSRA8.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_DSADC_A9_EXIST == STD_ON)
  SRC_DSADCSRA9.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_DSADC_M0_EXIST == STD_ON)
  SRC_DSADCSRM0.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_DSADC_M1_EXIST == STD_ON)
  SRC_DSADCSRM1.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_DSADC_M2_EXIST == STD_ON)
  SRC_DSADCSRM2.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_DSADC_M3_EXIST == STD_ON)
  SRC_DSADCSRM3.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_DSADC_M4_EXIST == STD_ON)
  SRC_DSADCSRM4.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_DSADC_M5_EXIST == STD_ON)
  SRC_DSADCSRM5.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_DSADC_M6_EXIST == STD_ON)
  SRC_DSADCSRM6.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_DSADC_M7_EXIST == STD_ON)
  SRC_DSADCSRM7.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_DSADC_M8_EXIST == STD_ON)
  SRC_DSADCSRM8.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_DSADC_M9_EXIST == STD_ON)
  SRC_DSADCSRM9.U = IRQ_DISABLE_CLEAR_SRC;
  #endif
  
}
#endif

#if (IRQ_MSC_EXIST == STD_ON)
static void Irq_ClearMscIntFlags (void)
{
  /* Set CLRR to clear SRR bit and disable SRE bit */
  #if (IRQ_MSC0_EXIST == STD_ON)
  SRC_MSC0SR0.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_MSC0SR1.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_MSC0SR2.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_MSC0SR3.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_MSC0SR4.U = IRQ_DISABLE_CLEAR_SRC;
  #endif/* End for IRQ_MSC0_EXIST == STD_ON*/

  #if (IRQ_MSC1_EXIST == STD_ON)
  SRC_MSC1SR0.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_MSC1SR1.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_MSC1SR2.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_MSC1SR3.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_MSC1SR4.U = IRQ_DISABLE_CLEAR_SRC;
  #endif/* End for IRQ_MSC1_EXIST == STD_ON*/

  #if (IRQ_MSC2_EXIST == STD_ON)
  SRC_MSC2SR0.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_MSC2SR1.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_MSC2SR2.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_MSC2SR3.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_MSC2SR4.U = IRQ_DISABLE_CLEAR_SRC;
  #endif/* End for IRQ_MSC2_EXIST == STD_ON*/
  
}
#endif

#if (IRQ_FLEXRAY_EXIST == STD_ON)
static void Irq_ClearFlexrayIntFlags (void)
{
  /* Set CLRR to clear SRR bit and disable SRE bit */
  #if (IRQ_FLEXRAY0_EXIST == STD_ON)
  SRC_ERAY_ERAY0_INT0.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_ERAY_ERAY0_INT1.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_ERAY_ERAY0_TINT0.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_ERAY_ERAY0_TINT1.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_ERAY_ERAY0_NDAT0.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_ERAY_ERAY0_NDAT1.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_ERAY_ERAY0_MBSC0.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_ERAY_ERAY0_MBSC1.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_ERAY_ERAY0_OBUSY.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_ERAY_ERAY0_IBUSY.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_FLEXRAY1_EXIST == STD_ON)
  SRC_ERAY_ERAY1_INT0.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_ERAY_ERAY1_INT1.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_ERAY_ERAY1_TINT0.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_ERAY_ERAY1_TINT1.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_ERAY_ERAY1_NDAT0.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_ERAY_ERAY1_NDAT1.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_ERAY_ERAY1_MBSC0.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_ERAY_ERAY1_MBSC1.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_ERAY_ERAY1_OBUSY.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_ERAY_ERAY1_IBUSY.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  
}
#endif

#if (IRQ_ETH_EXIST == STD_ON)
static void Irq_ClearEthernetIntFlags (void)
{
  /* Set CLRR to clear SRR bit and disable SRE bit */
  SRC_ETH.U = IRQ_DISABLE_CLEAR_SRC;
}
#endif

#if (IRQ_DMA_EXIST == STD_ON)
static void Irq_ClearDmaIntFlags (void)
{
  /* Set CLRR to clear SRR bit and disable SRE bit */
  SRC_DMAERR.U = IRQ_DISABLE_CLEAR_SRC;

  #if (IRQ_DMA_CH0TO47_EXIST == STD_ON)
  SRC_DMACH0.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH1.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH2.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH3.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH4.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH5.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH6.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH7.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH8.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH9.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH10.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH11.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH12.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH13.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH14.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH15.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH16.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH17.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH18.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH19.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH20.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH21.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH22.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH23.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH24.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH25.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH26.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH27.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH28.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH29.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH30.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH31.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH32.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH33.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH34.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH35.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH36.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH37.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH38.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH39.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH40.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH41.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH42.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH43.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH44.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH45.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH46.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH47.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_DMA_CH48TO63_EXIST == STD_ON)
  SRC_DMACH48.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH49.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH50.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH51.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH52.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH53.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH54.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH55.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH56.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH57.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH58.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH59.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH60.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH61.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH62.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH63.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_DMA_CH64TO127_EXIST == STD_ON)
  SRC_DMACH64.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH65.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH66.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH67.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH68.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH69.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH70.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH71.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH72.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH73.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH74.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH75.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH76.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH77.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH78.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH79.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH80.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH81.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH82.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH83.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH84.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH85.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH86.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH87.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH88.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH89.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH90.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH91.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH92.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH93.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH94.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH95.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH96.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH97.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH98.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH99.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH100.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH101.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH102.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH103.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH104.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH105.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH106.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH107.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH108.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH109.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH110.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH111.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH112.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH113.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH114.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH115.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH116.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH117.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH118.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH119.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH120.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH121.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH122.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH123.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH124.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH125.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH126.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_DMACH127.U = IRQ_DISABLE_CLEAR_SRC;
  #endif
  
}
#endif

#if (IRQ_STM_EXIST == STD_ON)
static void Irq_ClearStmIntFlags (void)
{
  /* Set CLRR to clear SRR bit and disable SRE bit */
  #if (IRQ_STM0_EXIST == STD_ON)
  SRC_STM0SR0.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_STM0SR1.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_STM1_EXIST == STD_ON)
  SRC_STM1SR0.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_STM1SR1.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_STM2_EXIST == STD_ON)
  SRC_STM2SR0.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_STM2SR1.U = IRQ_DISABLE_CLEAR_SRC;
  #endif
  
}
#endif

#if (IRQ_SCU_EXIST == STD_ON)
static void Irq_ClearScuIntFlags (void)
{
  /* Set CLRR to clear SRR bit and disable SRE bit */
  SRC_SCUDTS.U  = IRQ_DISABLE_CLEAR_SRC;
  SRC_SCUERU0.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_SCUERU1.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_SCUERU2.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_SCUERU3.U = IRQ_DISABLE_CLEAR_SRC;
}
#endif

#if (IRQ_PMU0_EXIST == STD_ON)
static void Irq_ClearPmuIntFlags (void)
{
  /* Set CLRR to clear SRR bit and disable SRE bit */
  #if (IRQ_PMU0_SR0_EXIST == STD_ON)
  SRC_PMU00.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_PMU0_SR1_EXIST == STD_ON)
  SRC_PMU01.U = IRQ_DISABLE_CLEAR_SRC;
  #endif  
}
#endif

#if (IRQ_SENT_EXIST == STD_ON)
static void Irq_ClearSentIntFlags (void)
{
  /* Set CLRR to clear SRR bit and disable SRE bit */
  #if (IRQ_SENT0_EXIST == STD_ON)
  SRC_SENT0.U = IRQ_DISABLE_CLEAR_SRC;
  #endif
  #if (IRQ_SENT1_EXIST == STD_ON)
  SRC_SENT1.U = IRQ_DISABLE_CLEAR_SRC;
  #endif
  #if (IRQ_SENT2_EXIST == STD_ON)
  SRC_SENT2.U = IRQ_DISABLE_CLEAR_SRC;
  #endif
  #if (IRQ_SENT3_EXIST == STD_ON)
  SRC_SENT3.U = IRQ_DISABLE_CLEAR_SRC;
  #endif
  #if (IRQ_SENT4_EXIST == STD_ON)
  SRC_SENT4.U = IRQ_DISABLE_CLEAR_SRC;
  #endif
  #if (IRQ_SENT5_EXIST == STD_ON)
  SRC_SENT5.U = IRQ_DISABLE_CLEAR_SRC;
  #endif
  #if (IRQ_SENT6_EXIST == STD_ON)
  SRC_SENT6.U = IRQ_DISABLE_CLEAR_SRC;
  #endif
  #if (IRQ_SENT7_EXIST == STD_ON)
  SRC_SENT7.U = IRQ_DISABLE_CLEAR_SRC;
  #endif
  #if (IRQ_SENT8_EXIST == STD_ON)
  SRC_SENT8.U = IRQ_DISABLE_CLEAR_SRC;
  #endif
  #if (IRQ_SENT9_EXIST == STD_ON)
  SRC_SENT9.U = IRQ_DISABLE_CLEAR_SRC;
  #endif
  #if (IRQ_SENT10_EXIST == STD_ON)
  SRC_SENT10.U = IRQ_DISABLE_CLEAR_SRC;
  #endif
  #if (IRQ_SENT11_EXIST == STD_ON)
  SRC_SENT11.U = IRQ_DISABLE_CLEAR_SRC;
  #endif
  #if (IRQ_SENT12_EXIST == STD_ON)
  SRC_SENT12.U = IRQ_DISABLE_CLEAR_SRC;
  #endif
  #if (IRQ_SENT13_EXIST == STD_ON)
  SRC_SENT13.U = IRQ_DISABLE_CLEAR_SRC;
  #endif
  #if (IRQ_SENT14_EXIST == STD_ON)
  SRC_SENT14.U = IRQ_DISABLE_CLEAR_SRC;
  #endif
  
}
#endif

#if (IRQ_I2C_EXIST == STD_ON)
static void Irq_ClearI2cIntFlags (void)
{
  /* Set CLRR to clear SRR bit and disable SRE bit */
  #if (IRQ_I2C0_EXIST == STD_ON)
  SRC_I2C0BREQ.U  = IRQ_DISABLE_CLEAR_SRC;
  SRC_I2C0LBREQ.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_I2C0SREQ.U  = IRQ_DISABLE_CLEAR_SRC;
  SRC_I2C0LSREQ.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_I2C0ERR.U   = IRQ_DISABLE_CLEAR_SRC;
  SRC_I2C0P.U     = IRQ_DISABLE_CLEAR_SRC;
  #endif/* End for IRQ_I2C0_EXIST == STD_ON*/

  #if (IRQ_I2C1_EXIST == STD_ON)
  SRC_I2C1BREQ.U  = IRQ_DISABLE_CLEAR_SRC;
  SRC_I2C1LBREQ.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_I2C1SREQ.U  = IRQ_DISABLE_CLEAR_SRC;
  SRC_I2C1LSREQ.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_I2C1ERR.U   = IRQ_DISABLE_CLEAR_SRC;
  SRC_I2C1P.U     = IRQ_DISABLE_CLEAR_SRC;
  #endif/* End for IRQ_I2C1_EXIST == STD_ON*/
  
}
#endif

#if (IRQ_HSSL_EXIST == STD_ON)
static void Irq_ClearHsslIntFlags(void)
{
  /* Set CLRR to clear SRR bit and disable SRE bit */
  #if (IRQ_HSSL0_EXIST == STD_ON)
  SRC_HSSLCOK0.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_HSSLRDI0.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_HSSLTRG0.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_HSSLERR0.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_HSSL1_EXIST == STD_ON)
  SRC_HSSLCOK1.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_HSSLRDI1.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_HSSLTRG1.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_HSSLERR1.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_HSSL2_EXIST == STD_ON)
  SRC_HSSLCOK2.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_HSSLRDI2.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_HSSLTRG2.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_HSSLERR2.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_HSSL3_EXIST == STD_ON)
  SRC_HSSLCOK3.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_HSSLRDI3.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_HSSLTRG3.U = IRQ_DISABLE_CLEAR_SRC;
  SRC_HSSLERR3.U = IRQ_DISABLE_CLEAR_SRC;
  #endif

  #if (IRQ_HSSL_EXI_SRN_EXIST == STD_ON)
  SRC_HSSLEXI.U  = IRQ_DISABLE_CLEAR_SRC;
  #endif
}
#endif

#endif /*(IFX_MCAL_USED == STD_ON) */

/*******************************************************************************
**                      Global Function Definitions                           **
*******************************************************************************/
#if (IFX_MCAL_USED == STD_ON)
/*******************************************************************************
** Syntax :  void IrqAscLin_Init(void)                                        **
**                                                                            **
** Service ID:  none                                                          **
**                                                                            **
** Sync/Async:  Synchronous                                                   **
**                                                                            **
** Reentrancy:  non reentrant                                                 **
**                                                                            **
** Parameters (in): none                                                      **
**                                                                            **
** Parameters (out): none                                                     **
**                                                                            **
** Return value: none                                                         **
**                                                                            **
** Description : To set the interrupt priority for various                    **
**               service nodes according to priority configurartion.          **
**                                                                            **
*******************************************************************************/

void IrqAscLin_Init(void)
{
  #if (IRQ_ASCLIN_EXIST == STD_ON)

  #if (IRQ_ASCLIN0_EXIST == STD_ON)
  /* Reserve bit access is ensured for SRC register at all places accessed*/
  IRQ_SFR_MODIFY32(SRC_ASCLIN0TX.U, IRQ_CLEAR_MASK , \
                     (IRQ_ASCLIN0_TX_TOS | IRQ_ASCLIN0_TX_PRIO));
  IRQ_SFR_MODIFY32(SRC_ASCLIN0RX.U, IRQ_CLEAR_MASK ,  \
                     (IRQ_ASCLIN0_RX_TOS | IRQ_ASCLIN0_RX_PRIO));
  IRQ_SFR_MODIFY32(SRC_ASCLIN0ERR.U, IRQ_CLEAR_MASK ,  \
                     (IRQ_ASCLIN0_ERR_TOS | IRQ_ASCLIN0_ERR_PRIO));
  #endif

  #if (IRQ_ASCLIN1_EXIST == STD_ON)
  IRQ_SFR_MODIFY32(SRC_ASCLIN1TX.U, IRQ_CLEAR_MASK , \
                     (IRQ_ASCLIN1_TX_TOS | IRQ_ASCLIN1_TX_PRIO));
  IRQ_SFR_MODIFY32(SRC_ASCLIN1RX.U, IRQ_CLEAR_MASK ,  \
                     (IRQ_ASCLIN1_RX_TOS | IRQ_ASCLIN1_RX_PRIO));
  IRQ_SFR_MODIFY32(SRC_ASCLIN1ERR.U, IRQ_CLEAR_MASK , \
                     (IRQ_ASCLIN1_ERR_TOS | IRQ_ASCLIN1_ERR_PRIO));
  #endif

  #if (IRQ_ASCLIN2_EXIST == STD_ON)
  IRQ_SFR_MODIFY32(SRC_ASCLIN2TX.U, IRQ_CLEAR_MASK , \
                     (IRQ_ASCLIN2_TX_TOS | IRQ_ASCLIN2_TX_PRIO));
  IRQ_SFR_MODIFY32(SRC_ASCLIN2RX.U, IRQ_CLEAR_MASK , \
                     (IRQ_ASCLIN2_RX_TOS | IRQ_ASCLIN2_RX_PRIO));
  IRQ_SFR_MODIFY32(SRC_ASCLIN2ERR.U, IRQ_CLEAR_MASK , \
                     (IRQ_ASCLIN2_ERR_TOS | IRQ_ASCLIN2_ERR_PRIO));
  #endif

  #if (IRQ_ASCLIN3_EXIST == STD_ON)
  IRQ_SFR_MODIFY32(SRC_ASCLIN3TX.U, IRQ_CLEAR_MASK , \
                     (IRQ_ASCLIN3_TX_TOS | IRQ_ASCLIN3_TX_PRIO));
  IRQ_SFR_MODIFY32(SRC_ASCLIN3RX.U, IRQ_CLEAR_MASK , \
                     (IRQ_ASCLIN3_RX_TOS | IRQ_ASCLIN3_RX_PRIO));
  IRQ_SFR_MODIFY32(SRC_ASCLIN3ERR.U, IRQ_CLEAR_MASK , \
                     (IRQ_ASCLIN3_ERR_TOS | IRQ_ASCLIN3_ERR_PRIO));
  #endif

  #endif

}

/*******************************************************************************
** Syntax :  void IrqCcu6_Init(void)                                         **
**                                                                            **
** Service ID:  none                                                          **
**                                                                            **
** Sync/Async:  Synchronous                                                   **
**                                                                            **
** Reentrancy:  non reentrant                                                 **
**                                                                            **
** Parameters (in): none                                                      **
**                                                                            **
** Parameters (out): none                                                     **
**                                                                            **
** Return value: none                                                         **
**                                                                            **
** Description : To set the interrupt priority for various                    **
**               service nodes according to priority configurartion.          **
**                                                                            **
*******************************************************************************/

void IrqCcu6_Init(void)
{
  #if (IRQ_CCU6_EXIST == STD_ON)

  #if (IRQ_CCU60_EXIST == STD_ON)
  IRQ_SFR_MODIFY32(SRC_CCU60SR0.U,IRQ_CLEAR_MASK, \
                     (IRQ_CCU60_SR0_TOS | IRQ_CCU60_SR0_PRIO));
  IRQ_SFR_MODIFY32(SRC_CCU60SR1.U,IRQ_CLEAR_MASK, \
                     (IRQ_CCU60_SR1_TOS | IRQ_CCU60_SR1_PRIO));
  IRQ_SFR_MODIFY32(SRC_CCU60SR2.U,IRQ_CLEAR_MASK, \
                     (IRQ_CCU60_SR2_TOS | IRQ_CCU60_SR2_PRIO));
  IRQ_SFR_MODIFY32(SRC_CCU60SR3.U,IRQ_CLEAR_MASK,  \
                     (IRQ_CCU60_SR3_TOS | IRQ_CCU60_SR3_PRIO));
  #endif

  #if (IRQ_CCU61_EXIST == STD_ON)
  IRQ_SFR_MODIFY32(SRC_CCU61SR0.U, IRQ_CLEAR_MASK , \
                     (IRQ_CCU61_SR0_TOS | IRQ_CCU61_SR0_PRIO));
  IRQ_SFR_MODIFY32(SRC_CCU61SR1.U, IRQ_CLEAR_MASK , \
                     (IRQ_CCU61_SR1_TOS | IRQ_CCU61_SR1_PRIO));
  IRQ_SFR_MODIFY32(SRC_CCU61SR2.U, IRQ_CLEAR_MASK , \
                     (IRQ_CCU61_SR2_TOS | IRQ_CCU61_SR2_PRIO));
  IRQ_SFR_MODIFY32(SRC_CCU61SR3.U, IRQ_CLEAR_MASK , \
                     (IRQ_CCU61_SR3_TOS | IRQ_CCU61_SR3_PRIO));
  #endif

  #endif
}
/*******************************************************************************
** Syntax :  void IrqGpt_Init(void)                                         **
**                                                                            **
** Service ID:  none                                                          **
**                                                                            **
** Sync/Async:  Synchronous                                                   **
**                                                                            **
** Reentrancy:  non reentrant                                                 **
**                                                                            **
** Parameters (in): none                                                      **
**                                                                            **
** Parameters (out): none                                                     **
**                                                                            **
** Return value: none                                                         **
**                                                                            **
** Description : To set the interrupt priority for various                    **
**               service nodes according to priority configurartion.          **
**                                                                            **
*******************************************************************************/

void IrqGpt_Init(void)
{
  #if (IRQ_GPT_EXIST == STD_ON)

  #if (IRQ_GPT120_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_GPT120CIRQ.U, IRQ_CLEAR_MASK , \
                     (IRQ_GPT120_CARPEL_TOS | IRQ_GPT120_CARPEL_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GPT120T2.U, IRQ_CLEAR_MASK , \
                     (IRQ_GPT120_T2_TOS | IRQ_GPT120_T2_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GPT120T3.U, IRQ_CLEAR_MASK , \
                     (IRQ_GPT120_T3_TOS | IRQ_GPT120_T3_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GPT120T4.U, IRQ_CLEAR_MASK , \
                     (IRQ_GPT120_T4_TOS | IRQ_GPT120_T4_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GPT120T5.U, IRQ_CLEAR_MASK , \
                     (IRQ_GPT120_T5_TOS | IRQ_GPT120_T5_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GPT120T6.U, IRQ_CLEAR_MASK , \
                     (IRQ_GPT120_T6_TOS | IRQ_GPT120_T6_PRIO));
  #endif

  #endif
}
/*******************************************************************************
** Syntax :  void IrqGtm_Init(void)                                           **
**                                                                            **
** Service ID:  none                                                          **
**                                                                            **
** Sync/Async:  Synchronous                                                   **
**                                                                            **
** Reentrancy:  non reentrant                                                 **
**                                                                            **
** Parameters (in): none                                                      **
**                                                                            **
** Parameters (out): none                                                     **
**                                                                            **
** Return value: none                                                         **
**                                                                            **
** Description : To set the interrupt priority for various                    **
**               service nodes according to priority configurartion.          **
**                                                                            **
*******************************************************************************/
void IrqGtm_Init(void)
{
  #if (IRQ_GTM_EXIST == STD_ON)

  #if (IRQ_GTM_AEI_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_GTMAEIIRQ.U, IRQ_CLEAR_MASK , \
                     (IRQ_GTM_AEI_TOS | IRQ_GTM_AEI_PRIO));
  #endif

  #if (IRQ_GTM_ARU_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_GTMARUIRQ0.U, IRQ_CLEAR_MASK , \
                     (IRQ_GTM_ARU_SR0_TOS | IRQ_GTM_ARU_SR0_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMARUIRQ1.U, IRQ_CLEAR_MASK , \
                     (IRQ_GTM_ARU_SR1_TOS | IRQ_GTM_ARU_SR1_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMARUIRQ2.U, IRQ_CLEAR_MASK , \
                     (IRQ_GTM_ARU_SR2_TOS | IRQ_GTM_ARU_SR2_PRIO));
  #endif

  #if (IRQ_GTM_BRC_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_GTMBRCIRQ.U, IRQ_CLEAR_MASK , \
                     (IRQ_GTM_BRC_TOS | IRQ_GTM_BRC_PRIO));
  #endif

  #if (IRQ_GTM_CMP_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_GTMCMPIRQ.U, IRQ_CLEAR_MASK , \
                     (IRQ_GTM_CMP_TOS | IRQ_GTM_CMP_PRIO));
  #endif

  #if (IRQ_GTM_SPE_EXIST == STD_ON)

  #if (IRQ_GTM_SPE0_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_GTMSPE0IRQ.U ,IRQ_CLEAR_MASK , \
                     (IRQ_GTM_SPE0_TOS | IRQ_GTM_SPE0_PRIO));
  #endif

  #if (IRQ_GTM_SPE1_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_GTMSPE1IRQ.U ,IRQ_CLEAR_MASK , \
                     (IRQ_GTM_SPE1_TOS | IRQ_GTM_SPE1_PRIO));
  #endif

  #if (IRQ_GTM_SPE2_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_GTMSPE2IRQ.U ,IRQ_CLEAR_MASK , \
                     (IRQ_GTM_SPE2_TOS | IRQ_GTM_SPE2_PRIO));
  #endif

  #if (IRQ_GTM_SPE3_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_GTMSPE3IRQ.U ,IRQ_CLEAR_MASK , \
                     (IRQ_GTM_SPE3_TOS | IRQ_GTM_SPE3_PRIO));
  #endif

  #endif

  #if (IRQ_GTM_PSM0_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_GTMPSM00.U , IRQ_CLEAR_MASK , \
                     (IRQ_GTM_PSM0_SR0_TOS | IRQ_GTM_PSM0_SR0_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMPSM01.U , IRQ_CLEAR_MASK , \
                     (IRQ_GTM_PSM0_SR1_TOS | IRQ_GTM_PSM0_SR1_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMPSM02.U , IRQ_CLEAR_MASK , \
                     (IRQ_GTM_PSM0_SR2_TOS | IRQ_GTM_PSM0_SR2_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMPSM03.U , IRQ_CLEAR_MASK , \
                     (IRQ_GTM_PSM0_SR3_TOS | IRQ_GTM_PSM0_SR3_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMPSM04.U , IRQ_CLEAR_MASK , \
                     (IRQ_GTM_PSM0_SR4_TOS | IRQ_GTM_PSM0_SR4_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMPSM05.U , IRQ_CLEAR_MASK , \
                     (IRQ_GTM_PSM0_SR5_TOS | IRQ_GTM_PSM0_SR5_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMPSM06.U , IRQ_CLEAR_MASK , \
                     (IRQ_GTM_PSM0_SR6_TOS | IRQ_GTM_PSM0_SR6_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMPSM07.U, IRQ_CLEAR_MASK , \
                     (IRQ_GTM_PSM0_SR7_TOS | IRQ_GTM_PSM0_SR7_PRIO));
  #endif

  #if (IRQ_GTM_PSM1_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_GTMPSM10.U, IRQ_CLEAR_MASK , \
                     (IRQ_GTM_PSM1_SR0_TOS | IRQ_GTM_PSM1_SR0_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMPSM11.U, IRQ_CLEAR_MASK , \
                     (IRQ_GTM_PSM1_SR1_TOS | IRQ_GTM_PSM1_SR1_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMPSM12.U, IRQ_CLEAR_MASK , \
                     (IRQ_GTM_PSM1_SR2_TOS | IRQ_GTM_PSM1_SR2_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMPSM13.U, IRQ_CLEAR_MASK , \
                     (IRQ_GTM_PSM1_SR3_TOS | IRQ_GTM_PSM1_SR3_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMPSM14.U, IRQ_CLEAR_MASK , \
                     (IRQ_GTM_PSM1_SR4_TOS | IRQ_GTM_PSM1_SR4_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMPSM15.U, IRQ_CLEAR_MASK , \
                     (IRQ_GTM_PSM1_SR5_TOS | IRQ_GTM_PSM1_SR5_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMPSM16.U, IRQ_CLEAR_MASK , \
                     (IRQ_GTM_PSM1_SR6_TOS | IRQ_GTM_PSM1_SR6_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMPSM17.U, IRQ_CLEAR_MASK , \
                     (IRQ_GTM_PSM1_SR7_TOS | IRQ_GTM_PSM1_SR7_PRIO));
  #endif

  #if (IRQ_GTM_DPLL_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_GTMDPLL0.U, IRQ_CLEAR_MASK , \
                     (IRQ_GTM_DPLL_SR0_TOS | IRQ_GTM_DPLL_SR0_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMDPLL1.U, IRQ_CLEAR_MASK , \
                     (IRQ_GTM_DPLL_SR1_TOS | IRQ_GTM_DPLL_SR1_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMDPLL2.U, IRQ_CLEAR_MASK , \
                     (IRQ_GTM_DPLL_SR2_TOS | IRQ_GTM_DPLL_SR2_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMDPLL3.U, IRQ_CLEAR_MASK , \
                     (IRQ_GTM_DPLL_SR3_TOS | IRQ_GTM_DPLL_SR3_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMDPLL4.U, IRQ_CLEAR_MASK , \
                     (IRQ_GTM_DPLL_SR4_TOS | IRQ_GTM_DPLL_SR4_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMDPLL5.U, IRQ_CLEAR_MASK , \
                     (IRQ_GTM_DPLL_SR5_TOS | IRQ_GTM_DPLL_SR5_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMDPLL6.U, IRQ_CLEAR_MASK , \
                     (IRQ_GTM_DPLL_SR6_TOS | IRQ_GTM_DPLL_SR6_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMDPLL7.U, IRQ_CLEAR_MASK , \
                     (IRQ_GTM_DPLL_SR7_TOS | IRQ_GTM_DPLL_SR7_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMDPLL8.U, IRQ_CLEAR_MASK , \
                     (IRQ_GTM_DPLL_SR8_TOS | IRQ_GTM_DPLL_SR8_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMDPLL9.U, IRQ_CLEAR_MASK , \
                     (IRQ_GTM_DPLL_SR9_TOS | IRQ_GTM_DPLL_SR9_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMDPLL10.U, IRQ_CLEAR_MASK , \
                     (IRQ_GTM_DPLL_SR10_TOS | IRQ_GTM_DPLL_SR10_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMDPLL11.U, IRQ_CLEAR_MASK , \
                     (IRQ_GTM_DPLL_SR11_TOS | IRQ_GTM_DPLL_SR11_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMDPLL12.U, IRQ_CLEAR_MASK , \
                     (IRQ_GTM_DPLL_SR12_TOS | IRQ_GTM_DPLL_SR12_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMDPLL13.U, IRQ_CLEAR_MASK , \
                     (IRQ_GTM_DPLL_SR13_TOS | IRQ_GTM_DPLL_SR13_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMDPLL14.U, IRQ_CLEAR_MASK , \
                     (IRQ_GTM_DPLL_SR14_TOS | IRQ_GTM_DPLL_SR14_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMDPLL15.U, IRQ_CLEAR_MASK , \
                     (IRQ_GTM_DPLL_SR15_TOS | IRQ_GTM_DPLL_SR15_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMDPLL16.U, IRQ_CLEAR_MASK , \
                     (IRQ_GTM_DPLL_SR16_TOS | IRQ_GTM_DPLL_SR16_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMDPLL17.U, IRQ_CLEAR_MASK , \
                     (IRQ_GTM_DPLL_SR17_TOS | IRQ_GTM_DPLL_SR17_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMDPLL18.U, IRQ_CLEAR_MASK , \
                     (IRQ_GTM_DPLL_SR18_TOS | IRQ_GTM_DPLL_SR18_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMDPLL19.U, IRQ_CLEAR_MASK , \
                     (IRQ_GTM_DPLL_SR19_TOS | IRQ_GTM_DPLL_SR19_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMDPLL20.U, IRQ_CLEAR_MASK , \
                     (IRQ_GTM_DPLL_SR20_TOS | IRQ_GTM_DPLL_SR20_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMDPLL21.U, IRQ_CLEAR_MASK , \
                     (IRQ_GTM_DPLL_SR21_TOS | IRQ_GTM_DPLL_SR21_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMDPLL22.U, IRQ_CLEAR_MASK , \
                     (IRQ_GTM_DPLL_SR22_TOS | IRQ_GTM_DPLL_SR22_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMDPLL23.U, IRQ_CLEAR_MASK , \
                     (IRQ_GTM_DPLL_SR23_TOS | IRQ_GTM_DPLL_SR23_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMDPLL24.U, IRQ_CLEAR_MASK , \
                     (IRQ_GTM_DPLL_SR24_TOS | IRQ_GTM_DPLL_SR24_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMDPLL25.U, IRQ_CLEAR_MASK , \
                     (IRQ_GTM_DPLL_SR25_TOS | IRQ_GTM_DPLL_SR25_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMDPLL26.U, IRQ_CLEAR_MASK , \
                     (IRQ_GTM_DPLL_SR26_TOS | IRQ_GTM_DPLL_SR26_PRIO));
  #endif

  #if (IRQ_GTM_ERR_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_GTMERR.U, IRQ_CLEAR_MASK ,  \
                     (IRQ_GTM_ERR_SR_TOS | IRQ_GTM_ERR_SR_PRIO));
  #endif

  #if (IRQ_GTM_TIM0_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_GTMTIM00.U, IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TIM0_SR0_TOS | IRQ_GTM_TIM0_SR0_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMTIM01.U, IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TIM0_SR1_TOS | IRQ_GTM_TIM0_SR1_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMTIM02.U, IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TIM0_SR2_TOS | IRQ_GTM_TIM0_SR2_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMTIM03.U, IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TIM0_SR3_TOS | IRQ_GTM_TIM0_SR3_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMTIM04.U, IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TIM0_SR4_TOS | IRQ_GTM_TIM0_SR4_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMTIM05.U, IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TIM0_SR5_TOS | IRQ_GTM_TIM0_SR5_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMTIM06.U, IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TIM0_SR6_TOS | IRQ_GTM_TIM0_SR6_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMTIM07.U, IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TIM0_SR7_TOS | IRQ_GTM_TIM0_SR7_PRIO));
  #endif


  #if (IRQ_GTM_TIM1_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_GTMTIM10.U, IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TIM1_SR0_TOS | IRQ_GTM_TIM1_SR0_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMTIM11.U, IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TIM1_SR1_TOS | IRQ_GTM_TIM1_SR1_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMTIM12.U, IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TIM1_SR2_TOS | IRQ_GTM_TIM1_SR2_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMTIM13.U, IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TIM1_SR3_TOS | IRQ_GTM_TIM1_SR3_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMTIM14.U, IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TIM1_SR4_TOS | IRQ_GTM_TIM1_SR4_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMTIM15.U, IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TIM1_SR5_TOS | IRQ_GTM_TIM1_SR5_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMTIM16.U, IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TIM1_SR6_TOS | IRQ_GTM_TIM1_SR6_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMTIM17.U, IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TIM1_SR7_TOS | IRQ_GTM_TIM1_SR7_PRIO));
  #endif

  #if (IRQ_GTM_TIM2_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_GTMTIM20.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TIM2_SR0_TOS | IRQ_GTM_TIM2_SR0_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMTIM21.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TIM2_SR1_TOS | IRQ_GTM_TIM2_SR1_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMTIM22.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TIM2_SR2_TOS | IRQ_GTM_TIM2_SR2_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMTIM23.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TIM2_SR3_TOS | IRQ_GTM_TIM2_SR3_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMTIM24.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TIM2_SR4_TOS | IRQ_GTM_TIM2_SR4_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMTIM25.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TIM2_SR5_TOS | IRQ_GTM_TIM2_SR5_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMTIM26.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TIM2_SR6_TOS | IRQ_GTM_TIM2_SR6_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMTIM27.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TIM2_SR7_TOS | IRQ_GTM_TIM2_SR7_PRIO));
  #endif

  #if (IRQ_GTM_TIM3_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_GTMTIM30.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TIM3_SR0_TOS | IRQ_GTM_TIM3_SR0_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMTIM31.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TIM3_SR1_TOS | IRQ_GTM_TIM3_SR1_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMTIM32.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TIM3_SR2_TOS | IRQ_GTM_TIM3_SR2_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMTIM33.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TIM3_SR3_TOS | IRQ_GTM_TIM3_SR3_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMTIM34.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TIM3_SR4_TOS | IRQ_GTM_TIM3_SR4_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMTIM35.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TIM3_SR5_TOS | IRQ_GTM_TIM3_SR5_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMTIM36.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TIM3_SR6_TOS | IRQ_GTM_TIM3_SR6_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMTIM37.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TIM3_SR7_TOS | IRQ_GTM_TIM3_SR7_PRIO));
  #endif

  #if (IRQ_GTM_TIM4_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_GTMTIM40.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TIM4_SR0_TOS | IRQ_GTM_TIM4_SR0_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMTIM41.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TIM4_SR1_TOS | IRQ_GTM_TIM4_SR1_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMTIM42.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TIM4_SR2_TOS | IRQ_GTM_TIM4_SR2_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMTIM43.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TIM4_SR3_TOS | IRQ_GTM_TIM4_SR3_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMTIM44.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TIM4_SR4_TOS | IRQ_GTM_TIM4_SR4_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMTIM45.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TIM4_SR5_TOS | IRQ_GTM_TIM4_SR5_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMTIM46.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TIM4_SR6_TOS | IRQ_GTM_TIM4_SR6_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMTIM47.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TIM4_SR7_TOS | IRQ_GTM_TIM4_SR7_PRIO));
  #endif

  #if (IRQ_GTM_TIM5_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_GTMTIM50.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TIM5_SR0_TOS | IRQ_GTM_TIM5_SR0_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMTIM51.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TIM5_SR1_TOS | IRQ_GTM_TIM5_SR1_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMTIM52.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TIM5_SR2_TOS | IRQ_GTM_TIM5_SR2_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMTIM53.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TIM5_SR3_TOS | IRQ_GTM_TIM5_SR3_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMTIM54.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TIM5_SR4_TOS | IRQ_GTM_TIM5_SR4_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMTIM55.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TIM5_SR5_TOS | IRQ_GTM_TIM5_SR5_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMTIM56.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TIM5_SR6_TOS | IRQ_GTM_TIM5_SR6_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMTIM57.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TIM5_SR7_TOS | IRQ_GTM_TIM5_SR7_PRIO));
  #endif

  #if (IRQ_GTM_MCS0_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_GTMMCS00.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_MCS0_SR0_TOS | IRQ_GTM_MCS0_SR0_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMMCS01.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_MCS0_SR1_TOS | IRQ_GTM_MCS0_SR1_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMMCS02.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_MCS0_SR2_TOS | IRQ_GTM_MCS0_SR2_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMMCS03.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_MCS0_SR3_TOS | IRQ_GTM_MCS0_SR3_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMMCS04.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_MCS0_SR4_TOS | IRQ_GTM_MCS0_SR4_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMMCS05.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_MCS0_SR5_TOS | IRQ_GTM_MCS0_SR5_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMMCS06.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_MCS0_SR6_TOS | IRQ_GTM_MCS0_SR6_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMMCS07.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_MCS0_SR7_TOS | IRQ_GTM_MCS0_SR7_PRIO));
  #endif

  #if (IRQ_GTM_MCS1_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_GTMMCS10.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_MCS1_SR0_TOS | IRQ_GTM_MCS1_SR0_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMMCS11.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_MCS1_SR1_TOS | IRQ_GTM_MCS1_SR1_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMMCS12.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_MCS1_SR2_TOS | IRQ_GTM_MCS1_SR2_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMMCS13.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_MCS1_SR3_TOS | IRQ_GTM_MCS1_SR3_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMMCS14.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_MCS1_SR4_TOS | IRQ_GTM_MCS1_SR4_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMMCS15.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_MCS1_SR5_TOS | IRQ_GTM_MCS1_SR5_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMMCS16.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_MCS1_SR6_TOS | IRQ_GTM_MCS1_SR6_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMMCS17.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_MCS1_SR7_TOS | IRQ_GTM_MCS1_SR7_PRIO));
  #endif

  #if (IRQ_GTM_MCS2_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_GTMMCS20.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_MCS2_SR0_TOS | IRQ_GTM_MCS2_SR0_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMMCS21.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_MCS2_SR1_TOS | IRQ_GTM_MCS2_SR1_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMMCS22.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_MCS2_SR2_TOS | IRQ_GTM_MCS2_SR2_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMMCS23.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_MCS2_SR3_TOS | IRQ_GTM_MCS2_SR3_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMMCS24.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_MCS2_SR4_TOS | IRQ_GTM_MCS2_SR4_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMMCS25.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_MCS2_SR5_TOS | IRQ_GTM_MCS2_SR5_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMMCS26.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_MCS2_SR6_TOS | IRQ_GTM_MCS2_SR6_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMMCS27.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_MCS2_SR7_TOS | IRQ_GTM_MCS2_SR7_PRIO));
  #endif

  #if (IRQ_GTM_MCS3_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_GTMMCS30.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_MCS3_SR0_TOS | IRQ_GTM_MCS3_SR0_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMMCS31.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_MCS3_SR1_TOS | IRQ_GTM_MCS3_SR1_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMMCS32.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_MCS3_SR2_TOS | IRQ_GTM_MCS3_SR2_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMMCS33.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_MCS3_SR3_TOS | IRQ_GTM_MCS3_SR3_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMMCS34.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_MCS3_SR4_TOS | IRQ_GTM_MCS3_SR4_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMMCS35.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_MCS3_SR5_TOS | IRQ_GTM_MCS3_SR5_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMMCS36.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_MCS3_SR6_TOS | IRQ_GTM_MCS3_SR6_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMMCS37.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_MCS3_SR7_TOS | IRQ_GTM_MCS3_SR7_PRIO));
  #endif

  #if (IRQ_GTM_MCS4_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_GTMMCS40.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_MCS4_SR0_TOS | IRQ_GTM_MCS4_SR0_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMMCS41.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_MCS4_SR1_TOS | IRQ_GTM_MCS4_SR1_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMMCS42.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_MCS4_SR2_TOS | IRQ_GTM_MCS4_SR2_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMMCS43.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_MCS4_SR3_TOS | IRQ_GTM_MCS4_SR3_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMMCS44.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_MCS4_SR4_TOS | IRQ_GTM_MCS4_SR4_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMMCS45.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_MCS4_SR5_TOS | IRQ_GTM_MCS4_SR5_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMMCS46.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_MCS4_SR6_TOS | IRQ_GTM_MCS4_SR6_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMMCS47.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_MCS4_SR7_TOS | IRQ_GTM_MCS4_SR7_PRIO));
  #endif

  #if (IRQ_GTM_MCS5_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_GTMMCS50.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_MCS5_SR0_TOS | IRQ_GTM_MCS5_SR0_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMMCS51.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_MCS5_SR1_TOS | IRQ_GTM_MCS5_SR1_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMMCS52.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_MCS5_SR2_TOS | IRQ_GTM_MCS5_SR2_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMMCS53.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_MCS5_SR3_TOS | IRQ_GTM_MCS5_SR3_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMMCS54.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_MCS5_SR4_TOS | IRQ_GTM_MCS5_SR4_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMMCS55.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_MCS5_SR5_TOS | IRQ_GTM_MCS5_SR5_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMMCS56.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_MCS5_SR6_TOS | IRQ_GTM_MCS5_SR6_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMMCS57.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_MCS5_SR7_TOS | IRQ_GTM_MCS5_SR7_PRIO));
  #endif

  #if (IRQ_GTM_TOM0_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_GTMTOM00.U, IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TOM0_SR0_TOS | IRQ_GTM_TOM0_SR0_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMTOM01.U, IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TOM0_SR1_TOS | IRQ_GTM_TOM0_SR1_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMTOM02.U, IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TOM0_SR2_TOS | IRQ_GTM_TOM0_SR2_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMTOM03.U, IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TOM0_SR3_TOS | IRQ_GTM_TOM0_SR3_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMTOM04.U, IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TOM0_SR4_TOS | IRQ_GTM_TOM0_SR4_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMTOM05.U, IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TOM0_SR5_TOS | IRQ_GTM_TOM0_SR5_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMTOM06.U, IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TOM0_SR6_TOS | IRQ_GTM_TOM0_SR6_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMTOM07.U, IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TOM0_SR7_TOS | IRQ_GTM_TOM0_SR7_PRIO));
  #endif

  #if (IRQ_GTM_TOM1_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_GTMTOM10.U, IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TOM1_SR0_TOS | IRQ_GTM_TOM1_SR0_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMTOM11.U, IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TOM1_SR1_TOS | IRQ_GTM_TOM1_SR1_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMTOM12.U, IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TOM1_SR2_TOS | IRQ_GTM_TOM1_SR2_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMTOM13.U, IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TOM1_SR3_TOS | IRQ_GTM_TOM1_SR3_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMTOM14.U, IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TOM1_SR4_TOS | IRQ_GTM_TOM1_SR4_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMTOM15.U, IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TOM1_SR5_TOS | IRQ_GTM_TOM1_SR5_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMTOM16.U, IRQ_CLEAR_MASK ,  \
                     (IRQ_GTM_TOM1_SR6_TOS | IRQ_GTM_TOM1_SR6_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMTOM17.U, IRQ_CLEAR_MASK ,  \
                     (IRQ_GTM_TOM1_SR7_TOS | IRQ_GTM_TOM1_SR7_PRIO));

  #endif


  #if (IRQ_GTM_TOM2_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_GTMTOM20.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TOM2_SR0_TOS | IRQ_GTM_TOM2_SR0_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMTOM21.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TOM2_SR1_TOS | IRQ_GTM_TOM2_SR1_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMTOM22.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TOM2_SR2_TOS | IRQ_GTM_TOM2_SR2_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMTOM23.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TOM2_SR3_TOS | IRQ_GTM_TOM2_SR3_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMTOM24.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TOM2_SR4_TOS | IRQ_GTM_TOM2_SR4_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMTOM25.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TOM2_SR5_TOS | IRQ_GTM_TOM2_SR5_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMTOM26.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TOM2_SR6_TOS | IRQ_GTM_TOM2_SR6_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMTOM27.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TOM2_SR7_TOS | IRQ_GTM_TOM2_SR7_PRIO));
  #endif

  #if (IRQ_GTM_TOM3_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_GTMTOM30.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TOM3_SR0_TOS | IRQ_GTM_TOM3_SR0_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMTOM31.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TOM3_SR1_TOS | IRQ_GTM_TOM3_SR1_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMTOM32.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TOM3_SR2_TOS | IRQ_GTM_TOM3_SR2_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMTOM33.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TOM3_SR3_TOS | IRQ_GTM_TOM3_SR3_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMTOM34.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TOM3_SR4_TOS | IRQ_GTM_TOM3_SR4_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMTOM35.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TOM3_SR5_TOS | IRQ_GTM_TOM3_SR5_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMTOM36.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TOM3_SR6_TOS | IRQ_GTM_TOM3_SR6_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMTOM37.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TOM3_SR7_TOS | IRQ_GTM_TOM3_SR7_PRIO));
  #endif

  #if (IRQ_GTM_TOM4_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_GTMTOM40.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TOM4_SR0_TOS | IRQ_GTM_TOM4_SR0_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMTOM41.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TOM4_SR1_TOS | IRQ_GTM_TOM4_SR1_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMTOM42.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TOM4_SR2_TOS | IRQ_GTM_TOM4_SR2_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMTOM43.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TOM4_SR3_TOS | IRQ_GTM_TOM4_SR3_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMTOM44.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TOM4_SR4_TOS | IRQ_GTM_TOM4_SR4_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMTOM45.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TOM4_SR5_TOS | IRQ_GTM_TOM4_SR5_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMTOM46.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TOM4_SR6_TOS | IRQ_GTM_TOM4_SR6_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMTOM47.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_TOM4_SR7_TOS | IRQ_GTM_TOM4_SR7_PRIO));
  #endif

  #if (IRQ_GTM_ATOM0_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_GTMATOM00.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_ATOM0_SR0_TOS | IRQ_GTM_ATOM0_SR0_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMATOM01.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_ATOM0_SR1_TOS | IRQ_GTM_ATOM0_SR1_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMATOM02.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_ATOM0_SR2_TOS | IRQ_GTM_ATOM0_SR2_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMATOM03.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_ATOM0_SR3_TOS | IRQ_GTM_ATOM0_SR3_PRIO));
  #endif

  #if (IRQ_GTM_ATOM1_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_GTMATOM10.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_ATOM1_SR0_TOS | IRQ_GTM_ATOM1_SR0_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMATOM11.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_ATOM1_SR1_TOS | IRQ_GTM_ATOM1_SR1_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMATOM12.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_ATOM1_SR2_TOS | IRQ_GTM_ATOM1_SR2_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMATOM13.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_ATOM1_SR3_TOS | IRQ_GTM_ATOM1_SR3_PRIO));
  #endif

  #if (IRQ_GTM_ATOM2_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_GTMATOM20.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_ATOM2_SR0_TOS | IRQ_GTM_ATOM2_SR0_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMATOM21.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_ATOM2_SR1_TOS | IRQ_GTM_ATOM2_SR1_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMATOM22.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_ATOM2_SR2_TOS | IRQ_GTM_ATOM2_SR2_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMATOM23.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_ATOM2_SR3_TOS | IRQ_GTM_ATOM2_SR3_PRIO));
  #endif

  #if (IRQ_GTM_ATOM3_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_GTMATOM30.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_ATOM3_SR0_TOS | IRQ_GTM_ATOM3_SR0_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMATOM31.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_ATOM3_SR1_TOS | IRQ_GTM_ATOM3_SR1_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMATOM32.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_ATOM3_SR2_TOS | IRQ_GTM_ATOM3_SR2_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMATOM33.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_ATOM3_SR3_TOS | IRQ_GTM_ATOM3_SR3_PRIO));
  #endif

  #if (IRQ_GTM_ATOM4_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_GTMATOM40.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_ATOM4_SR0_TOS | IRQ_GTM_ATOM4_SR0_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMATOM41.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_ATOM4_SR1_TOS | IRQ_GTM_ATOM4_SR1_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMATOM42.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_ATOM4_SR2_TOS | IRQ_GTM_ATOM4_SR2_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMATOM43.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_ATOM4_SR3_TOS | IRQ_GTM_ATOM4_SR3_PRIO));
  #endif

  #if (IRQ_GTM_ATOM5_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_GTMATOM50.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_ATOM5_SR0_TOS | IRQ_GTM_ATOM5_SR0_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMATOM51.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_ATOM5_SR1_TOS | IRQ_GTM_ATOM5_SR1_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMATOM52.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_ATOM5_SR2_TOS | IRQ_GTM_ATOM5_SR2_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMATOM53.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_ATOM5_SR3_TOS | IRQ_GTM_ATOM5_SR3_PRIO));
  #endif

  #if (IRQ_GTM_ATOM6_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_GTMATOM60.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_ATOM6_SR0_TOS | IRQ_GTM_ATOM6_SR0_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMATOM61.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_ATOM6_SR1_TOS | IRQ_GTM_ATOM6_SR1_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMATOM62.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_ATOM6_SR2_TOS | IRQ_GTM_ATOM6_SR2_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMATOM63.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_ATOM6_SR3_TOS | IRQ_GTM_ATOM6_SR3_PRIO));
  #endif

  #if (IRQ_GTM_ATOM7_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_GTMATOM70.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_ATOM7_SR0_TOS | IRQ_GTM_ATOM7_SR0_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMATOM71.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_ATOM7_SR1_TOS | IRQ_GTM_ATOM7_SR1_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMATOM72.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_ATOM7_SR2_TOS | IRQ_GTM_ATOM7_SR2_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMATOM73.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_ATOM7_SR3_TOS | IRQ_GTM_ATOM7_SR3_PRIO));
  #endif

  #if (IRQ_GTM_ATOM8_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_GTMATOM80.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_ATOM8_SR0_TOS | IRQ_GTM_ATOM8_SR0_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMATOM81.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_ATOM8_SR1_TOS | IRQ_GTM_ATOM8_SR1_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMATOM82.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_ATOM8_SR2_TOS | IRQ_GTM_ATOM8_SR2_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GTMATOM83.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GTM_ATOM8_SR3_TOS | IRQ_GTM_ATOM8_SR3_PRIO));
  #endif

  #endif
}

/*******************************************************************************
** Syntax :  void IrqCan_Init(void)                                           **
**                                                                            **
** Service ID:  none                                                          **
**                                                                            **
** Sync/Async:  Synchronous                                                   **
**                                                                            **
** Reentrancy:  non reentrant                                                 **
**                                                                            **
** Parameters (in): none                                                      **
**                                                                            **
** Parameters (out): none                                                     **
**                                                                            **
** Return value: none                                                         **
**                                                                            **
** Description : To set the interrupt priority for various                    **
**               service nodes according to priority configurartion.          **
**                                                                            **
*******************************************************************************/
void IrqCan_Init(void)
{

  #if (IRQ_CAN_EXIST == STD_ON)
  /* Interrupt Priority is written to the SRC registers*/
  #if (IRQ_CAN0_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_CANINT0.U,  IRQ_CLEAR_MASK , \
                     (IRQ_CAN_SR0_TOS | IRQ_CAN_SR0_PRIO));
  #endif

  #if (IRQ_CAN1_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_CANINT1.U,  IRQ_CLEAR_MASK , \
                     (IRQ_CAN_SR1_TOS | IRQ_CAN_SR1_PRIO));
  #endif

  #if (IRQ_CAN2_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_CANINT2.U,  IRQ_CLEAR_MASK , \
                     (IRQ_CAN_SR2_TOS | IRQ_CAN_SR2_PRIO));
  #endif

  #if (IRQ_CAN3_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_CANINT3.U,  IRQ_CLEAR_MASK , \
                     (IRQ_CAN_SR3_TOS | IRQ_CAN_SR3_PRIO));
  #endif

  #if (IRQ_CAN4_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_CANINT4.U,  IRQ_CLEAR_MASK , \
                     (IRQ_CAN_SR4_TOS | IRQ_CAN_SR4_PRIO));
  #endif

  #if (IRQ_CAN5_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_CANINT5.U,  IRQ_CLEAR_MASK , \
                     (IRQ_CAN_SR5_TOS | IRQ_CAN_SR5_PRIO));
  #endif

  #if (IRQ_CAN6_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_CANINT6.U,  IRQ_CLEAR_MASK , \
                     (IRQ_CAN_SR6_TOS | IRQ_CAN_SR6_PRIO));
  #endif

  #if (IRQ_CAN7_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_CANINT7.U,  IRQ_CLEAR_MASK , \
                     (IRQ_CAN_SR7_TOS | IRQ_CAN_SR7_PRIO));
  #endif

  #if (IRQ_CAN8_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_CANINT8.U,  IRQ_CLEAR_MASK , \
                     (IRQ_CAN_SR8_TOS | IRQ_CAN_SR8_PRIO));
  #endif

  #if (IRQ_CAN9_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_CANINT9.U,  IRQ_CLEAR_MASK , \
                     (IRQ_CAN_SR9_TOS | IRQ_CAN_SR9_PRIO));
  #endif

  #if (IRQ_CAN10_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_CANINT10.U,  IRQ_CLEAR_MASK , \
                     (IRQ_CAN_SR10_TOS | IRQ_CAN_SR10_PRIO));
  #endif

  #if (IRQ_CAN11_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_CANINT11.U,  IRQ_CLEAR_MASK , \
                     (IRQ_CAN_SR11_TOS | IRQ_CAN_SR11_PRIO));
  #endif

  #if (IRQ_CAN12_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_CANINT12.U,  IRQ_CLEAR_MASK , \
                     (IRQ_CAN_SR12_TOS | IRQ_CAN_SR12_PRIO));
  #endif

  #if (IRQ_CAN13_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_CANINT13.U,  IRQ_CLEAR_MASK , \
                     (IRQ_CAN_SR13_TOS | IRQ_CAN_SR13_PRIO));
  #endif

  #if (IRQ_CAN14_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_CANINT14.U,  IRQ_CLEAR_MASK , \
                     (IRQ_CAN_SR14_TOS | IRQ_CAN_SR14_PRIO));
  #endif

  #if (IRQ_CAN15_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_CANINT15.U,  IRQ_CLEAR_MASK , \
                     (IRQ_CAN_SR15_TOS | IRQ_CAN_SR15_PRIO));
  #endif

  #if (IRQ_CAN16_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_CANRINT0.U,  IRQ_CLEAR_MASK , \
                     (IRQ_CAN_SR16_TOS | IRQ_CAN_SR16_PRIO));
  #endif

  #if (IRQ_CAN17_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_CANRINT1.U,  IRQ_CLEAR_MASK , \
                     (IRQ_CAN_SR17_TOS | IRQ_CAN_SR17_PRIO));
  #endif

  #if (IRQ_CAN18_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_CANRINT2.U,  IRQ_CLEAR_MASK , \
                     (IRQ_CAN_SR18_TOS | IRQ_CAN_SR18_PRIO));
  #endif

  #if (IRQ_CAN19_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_CANRINT3.U,  IRQ_CLEAR_MASK , \
                     (IRQ_CAN_SR19_TOS | IRQ_CAN_SR19_PRIO));
  #endif

  #if (IRQ_CAN20_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_CANRINT4.U,  IRQ_CLEAR_MASK , \
                     (IRQ_CAN_SR20_TOS | IRQ_CAN_SR20_PRIO));
  #endif

  #if (IRQ_CAN21_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_CANRINT5.U,  IRQ_CLEAR_MASK , \
                     (IRQ_CAN_SR21_TOS | IRQ_CAN_SR21_PRIO));
  #endif

  #if (IRQ_CAN22_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_CANRINT6.U,  IRQ_CLEAR_MASK , \
                     (IRQ_CAN_SR22_TOS | IRQ_CAN_SR22_PRIO));
  #endif

  #if (IRQ_CAN23_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_CANRINT7.U,  IRQ_CLEAR_MASK , \
                     (IRQ_CAN_SR23_TOS | IRQ_CAN_SR23_PRIO));
  #endif

  #endif
 }

/*******************************************************************************
** Syntax :  void IrqHsm_Init(void)                                           **
**                                                                            **
** Service ID:  none                                                          **
**                                                                            **
** Sync/Async:  Synchronous                                                   **
**                                                                            **
** Reentrancy:  non reentrant                                                 **
**                                                                            **
** Parameters (in): none                                                      **
**                                                                            **
** Parameters (out): none                                                     **
**                                                                            **
** Return value: none                                                         **
**                                                                            **
** Description : To set the interrupt priority for various                    **
**               service nodes according to priority configurartion.          **
**                                                                            **
*******************************************************************************/
void IrqHsm_Init(void)
{
  /* Interrupt Priority is written to the SRC registers*/

  #if (IRQ_HSM0_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_HSM0.U,  IRQ_CLEAR_MASK , \
                     (IRQ_HSM_SR0_TOS | IRQ_HSM_SR0_PRIO));
  #endif
  
  #if (IRQ_HSM1_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_HSM1.U,  IRQ_CLEAR_MASK , \
                     (IRQ_HSM_SR1_TOS | IRQ_HSM_SR1_PRIO));
  #endif
}

/*******************************************************************************
** Syntax :  void IrqGpsrGroup_Init(void)                                     **
**                                                                            **
** Service ID:  none                                                          **
**                                                                            **
** Sync/Async:  Synchronous                                                   **
**                                                                            **
** Reentrancy:  non reentrant                                                 **
**                                                                            **
** Parameters (in): none                                                      **
**                                                                            **
** Parameters (out): none                                                     **
**                                                                            **
** Return value: none                                                         **
**                                                                            **
** Description : To set the interrupt priority for Fls                        **
**               service nodes according to priority configurartion.          **
**                                                                            **
*******************************************************************************/
void IrqGpsrGroup_Init(void)
{
  #if (IRQ_GPSRGROUP_EXIST == STD_ON)

  #if (IRQ_GPSRGROUP0_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_GPSR00.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GPSRGROUP0_SR0_TOS | IRQ_GPSRGROUP0_SR0_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GPSR01.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GPSRGROUP0_SR1_TOS | IRQ_GPSRGROUP0_SR1_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GPSR02.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GPSRGROUP0_SR2_TOS | IRQ_GPSRGROUP0_SR2_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GPSR03.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GPSRGROUP0_SR3_TOS | IRQ_GPSRGROUP0_SR3_PRIO));
  #endif

  #if (IRQ_GPSRGROUP1_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_GPSR10.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GPSRGROUP1_SR0_TOS | IRQ_GPSRGROUP1_SR0_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GPSR11.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GPSRGROUP1_SR1_TOS | IRQ_GPSRGROUP1_SR1_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GPSR12.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GPSRGROUP1_SR2_TOS | IRQ_GPSRGROUP1_SR2_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GPSR13.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GPSRGROUP1_SR3_TOS | IRQ_GPSRGROUP1_SR3_PRIO));
  #endif

  #if (IRQ_GPSRGROUP2_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_GPSR20.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GPSRGROUP2_SR0_TOS | IRQ_GPSRGROUP2_SR0_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GPSR21.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GPSRGROUP2_SR1_TOS | IRQ_GPSRGROUP2_SR1_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GPSR22.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GPSRGROUP2_SR2_TOS | IRQ_GPSRGROUP2_SR2_PRIO));
  IRQ_SFR_MODIFY32 (SRC_GPSR23.U,  IRQ_CLEAR_MASK , \
                     (IRQ_GPSRGROUP2_SR3_TOS | IRQ_GPSRGROUP2_SR3_PRIO));
  #endif

  #endif
}

/*******************************************************************************
** Syntax :  void IrqSpi_Init(void)                                           **
**                                                                            **
** Service ID:  none                                                          **
**                                                                            **
** Sync/Async:  Synchronous                                                   **
**                                                                            **
** Reentrancy:  non reentrant                                                 **
**                                                                            **
** Parameters (in): none                                                      **
**                                                                            **
** Parameters (out): none                                                     **
**                                                                            **
** Return value: none                                                         **
**                                                                            **
** Description : To set the interrupt priority for various                    **
**               service nodes according to priority configurartion.          **
**                                                                            **
*******************************************************************************/

void IrqSpi_Init(void)
{

  #if (IRQ_QSPI_EXIST == STD_ON)

  #if (IRQ_QSPI0_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_QSPI0TX.U,  IRQ_CLEAR_MASK , \
                     (IRQ_QSPI0_TX_TOS | IRQ_QSPI0_TX_PRIO));
  IRQ_SFR_MODIFY32 (SRC_QSPI0RX.U,  IRQ_CLEAR_MASK , \
                     (IRQ_QSPI0_RX_TOS | IRQ_QSPI0_RX_PRIO));
  IRQ_SFR_MODIFY32 (SRC_QSPI0ERR.U,  IRQ_CLEAR_MASK , \
                     (IRQ_QSPI0_ERR_TOS | IRQ_QSPI0_ERR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_QSPI0PT.U,  IRQ_CLEAR_MASK , \
                     (IRQ_QSPI0_PT_TOS | IRQ_QSPI0_PT_PRIO));
  IRQ_SFR_MODIFY32 (SRC_QSPI0U.U ,  IRQ_CLEAR_MASK , \
                     (IRQ_QSPI0_UD_TOS | IRQ_QSPI0_UD_PRIO));
  #endif /*IRQ_QSPI0_EXIST == STD_ON*/

  #if (IRQ_QSPI1_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_QSPI1TX.U,  IRQ_CLEAR_MASK , \
                     (IRQ_QSPI1_TX_TOS | IRQ_QSPI1_TX_PRIO));
  IRQ_SFR_MODIFY32 (SRC_QSPI1RX.U,  IRQ_CLEAR_MASK , \
                     (IRQ_QSPI1_RX_TOS | IRQ_QSPI1_RX_PRIO));
  IRQ_SFR_MODIFY32 (SRC_QSPI1ERR.U ,  IRQ_CLEAR_MASK , \
                     (IRQ_QSPI1_ERR_TOS | IRQ_QSPI1_ERR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_QSPI1PT.U,  IRQ_CLEAR_MASK , \
                     (IRQ_QSPI1_PT_TOS | IRQ_QSPI1_PT_PRIO));
  IRQ_SFR_MODIFY32 (SRC_QSPI1U.U ,  IRQ_CLEAR_MASK , \
                     (IRQ_QSPI1_UD_TOS | IRQ_QSPI1_UD_PRIO));
  #endif

  #if (IRQ_QSPI2_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_QSPI2TX.U,  IRQ_CLEAR_MASK , \
                     (IRQ_QSPI2_TX_TOS | IRQ_QSPI2_TX_PRIO));
  IRQ_SFR_MODIFY32 (SRC_QSPI2RX.U,  IRQ_CLEAR_MASK , \
                     (IRQ_QSPI2_RX_TOS | IRQ_QSPI2_RX_PRIO));
  IRQ_SFR_MODIFY32 (SRC_QSPI2ERR.U  ,  IRQ_CLEAR_MASK , \
                     (IRQ_QSPI2_ERR_TOS | IRQ_QSPI2_ERR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_QSPI2PT.U,  IRQ_CLEAR_MASK , \
                     (IRQ_QSPI2_PT_TOS | IRQ_QSPI2_PT_PRIO));
  #if (IRQ_QSPI_HC_SRN_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_QSPI2HC.U,  IRQ_CLEAR_MASK , \
                     (IRQ_QSPI2_HC_TOS | IRQ_QSPI2_HC_PRIO));
  #endif /* (IRQ_QSPI_HC_SRN_EXIST == STD_ON) */
  IRQ_SFR_MODIFY32 (SRC_QSPI2U.U ,  IRQ_CLEAR_MASK , \
                     (IRQ_QSPI2_UD_TOS | IRQ_QSPI2_UD_PRIO));
  #endif

  #if (IRQ_QSPI3_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_QSPI3TX.U,  IRQ_CLEAR_MASK , \
                     (IRQ_QSPI3_TX_TOS | IRQ_QSPI3_TX_PRIO));
  IRQ_SFR_MODIFY32 (SRC_QSPI3RX.U,  IRQ_CLEAR_MASK , \
                     (IRQ_QSPI3_RX_TOS | IRQ_QSPI3_RX_PRIO));
  IRQ_SFR_MODIFY32 (SRC_QSPI3ERR.U,  IRQ_CLEAR_MASK , \
                     (IRQ_QSPI3_ERR_TOS | IRQ_QSPI3_ERR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_QSPI3PT.U,  IRQ_CLEAR_MASK , \
                     (IRQ_QSPI3_PT_TOS | IRQ_QSPI3_PT_PRIO));
  #if (IRQ_QSPI_HC_SRN_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_QSPI3HC.U,  IRQ_CLEAR_MASK , \
                     (IRQ_QSPI3_HC_TOS | IRQ_QSPI3_HC_PRIO));
  #endif /* (IRQ_QSPI_HC_SRN_EXIST == STD_ON) */
  IRQ_SFR_MODIFY32 (SRC_QSPI3U.U ,  IRQ_CLEAR_MASK , \
                     (IRQ_QSPI3_UD_TOS | IRQ_QSPI3_UD_PRIO));
  #endif

  #if (IRQ_QSPI4_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_QSPI4TX.U,  IRQ_CLEAR_MASK , \
                     (IRQ_QSPI4_TX_TOS | IRQ_QSPI4_TX_PRIO));
  IRQ_SFR_MODIFY32 (SRC_QSPI4RX.U,  IRQ_CLEAR_MASK , \
                     (IRQ_QSPI4_RX_TOS | IRQ_QSPI4_RX_PRIO));
  IRQ_SFR_MODIFY32 (SRC_QSPI4ERR.U,  IRQ_CLEAR_MASK , \
                     (IRQ_QSPI4_ERR_TOS | IRQ_QSPI4_ERR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_QSPI4PT.U,  IRQ_CLEAR_MASK , \
                     (IRQ_QSPI4_PT_TOS | IRQ_QSPI4_PT_PRIO));
  IRQ_SFR_MODIFY32 (SRC_QSPI4U.U ,  IRQ_CLEAR_MASK , \
                     (IRQ_QSPI4_UD_TOS | IRQ_QSPI4_UD_PRIO));
  #endif

  #if (IRQ_QSPI5_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_QSPI5TX.U,  IRQ_CLEAR_MASK , \
                     (IRQ_QSPI5_TX_TOS | IRQ_QSPI5_TX_PRIO));
  IRQ_SFR_MODIFY32 (SRC_QSPI5RX.U,  IRQ_CLEAR_MASK , \
                     (IRQ_QSPI5_RX_TOS | IRQ_QSPI5_RX_PRIO));
  IRQ_SFR_MODIFY32 (SRC_QSPI5ERR.U,  IRQ_CLEAR_MASK , \
                     (IRQ_QSPI5_ERR_TOS | IRQ_QSPI5_ERR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_QSPI5PT.U,  IRQ_CLEAR_MASK , \
                     (IRQ_QSPI5_PT_TOS | IRQ_QSPI5_PT_PRIO));
  IRQ_SFR_MODIFY32 (SRC_QSPI5U.U ,  IRQ_CLEAR_MASK , \
                     (IRQ_QSPI5_UD_TOS | IRQ_QSPI5_UD_PRIO));
  #endif

  #endif
}

/*******************************************************************************
** Syntax :  void IrqAdc_Init(void)                                           **
**                                                                            **
** Service ID:  none                                                          **
**                                                                            **
** Sync/Async:  Synchronous                                                   **
**                                                                            **
** Reentrancy:  non reentrant                                                 **
**                                                                            **
** Parameters (in): none                                                      **
**                                                                            **
** Parameters (out): none                                                     **
**                                                                            **
** Return value: none                                                         **
**                                                                            **
** Description : To set the interrupt priority for various                    **
**               service nodes according to priority configurartion.          **
**                                                                            **
*******************************************************************************/
void IrqAdc_Init(void)
{

  #if (IRQ_ADC_EXIST == STD_ON)

  #if (IRQ_ADC0_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_VADCG0SR0.U,  IRQ_CLEAR_MASK , \
                     (IRQ_ADC0_SR0_TOS | IRQ_ADC0_SR0_PRIO));
  IRQ_SFR_MODIFY32 (SRC_VADCG0SR1.U,  IRQ_CLEAR_MASK , \
                     (IRQ_ADC0_SR1_TOS | IRQ_ADC0_SR1_PRIO));
  IRQ_SFR_MODIFY32 (SRC_VADCG0SR2.U,  IRQ_CLEAR_MASK , \
                     (IRQ_ADC0_SR2_TOS | IRQ_ADC0_SR2_PRIO));
  IRQ_SFR_MODIFY32 (SRC_VADCG0SR3.U,  IRQ_CLEAR_MASK , \
                     (IRQ_ADC0_SR3_TOS | IRQ_ADC0_SR3_PRIO));
  #endif

  #if (IRQ_ADC1_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_VADCG1SR0.U,  IRQ_CLEAR_MASK , \
                     (IRQ_ADC1_SR0_TOS | IRQ_ADC1_SR0_PRIO));
  IRQ_SFR_MODIFY32 (SRC_VADCG1SR1.U,  IRQ_CLEAR_MASK , \
                     (IRQ_ADC1_SR1_TOS | IRQ_ADC1_SR1_PRIO));
  IRQ_SFR_MODIFY32 (SRC_VADCG1SR2.U,  IRQ_CLEAR_MASK , \
                     (IRQ_ADC1_SR2_TOS | IRQ_ADC1_SR2_PRIO));
  IRQ_SFR_MODIFY32 (SRC_VADCG1SR3.U,  IRQ_CLEAR_MASK , \
                     (IRQ_ADC1_SR3_TOS | IRQ_ADC1_SR3_PRIO));
  #endif

  #if (IRQ_ADC2_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_VADCG2SR0.U,  IRQ_CLEAR_MASK , \
                     (IRQ_ADC2_SR0_TOS | IRQ_ADC2_SR0_PRIO));
  IRQ_SFR_MODIFY32 (SRC_VADCG2SR1.U,  IRQ_CLEAR_MASK , \
                     (IRQ_ADC2_SR1_TOS | IRQ_ADC2_SR1_PRIO));
  IRQ_SFR_MODIFY32 (SRC_VADCG2SR2.U,  IRQ_CLEAR_MASK , \
                     (IRQ_ADC2_SR2_TOS | IRQ_ADC2_SR2_PRIO));
  IRQ_SFR_MODIFY32 (SRC_VADCG2SR3.U,  IRQ_CLEAR_MASK , \
                     (IRQ_ADC2_SR3_TOS | IRQ_ADC2_SR3_PRIO));
  #endif

  #if (IRQ_ADC3_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_VADCG3SR0.U,  IRQ_CLEAR_MASK , \
                     (IRQ_ADC3_SR0_TOS | IRQ_ADC3_SR0_PRIO));
  IRQ_SFR_MODIFY32 (SRC_VADCG3SR1.U,  IRQ_CLEAR_MASK , \
                     (IRQ_ADC3_SR1_TOS | IRQ_ADC3_SR1_PRIO));
  IRQ_SFR_MODIFY32 (SRC_VADCG3SR2.U,  IRQ_CLEAR_MASK , \
                     (IRQ_ADC3_SR2_TOS | IRQ_ADC3_SR2_PRIO));
  IRQ_SFR_MODIFY32 (SRC_VADCG3SR3.U,  IRQ_CLEAR_MASK , \
                     (IRQ_ADC3_SR3_TOS | IRQ_ADC3_SR3_PRIO));
  #endif

  #if (IRQ_ADC4_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_VADCG4SR0.U,  IRQ_CLEAR_MASK , \
                     (IRQ_ADC4_SR0_TOS | IRQ_ADC4_SR0_PRIO));
  IRQ_SFR_MODIFY32 (SRC_VADCG4SR1.U,  IRQ_CLEAR_MASK , \
                     (IRQ_ADC4_SR1_TOS | IRQ_ADC4_SR1_PRIO));
  IRQ_SFR_MODIFY32 (SRC_VADCG4SR2.U,  IRQ_CLEAR_MASK , \
                     (IRQ_ADC4_SR2_TOS | IRQ_ADC4_SR2_PRIO));
  IRQ_SFR_MODIFY32 (SRC_VADCG4SR3.U,  IRQ_CLEAR_MASK , \
                     (IRQ_ADC4_SR3_TOS | IRQ_ADC4_SR3_PRIO));
  #endif

  #if (IRQ_ADC5_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_VADCG5SR0.U,  IRQ_CLEAR_MASK , \
                     (IRQ_ADC5_SR0_TOS | IRQ_ADC5_SR0_PRIO));
  IRQ_SFR_MODIFY32 (SRC_VADCG5SR1.U,  IRQ_CLEAR_MASK , \
                     (IRQ_ADC5_SR1_TOS | IRQ_ADC5_SR1_PRIO));
  IRQ_SFR_MODIFY32 (SRC_VADCG5SR2.U,  IRQ_CLEAR_MASK , \
                     (IRQ_ADC5_SR2_TOS | IRQ_ADC5_SR2_PRIO));
  IRQ_SFR_MODIFY32 (SRC_VADCG5SR3.U,  IRQ_CLEAR_MASK , \
                     (IRQ_ADC5_SR3_TOS | IRQ_ADC5_SR3_PRIO));
  #endif

  #if (IRQ_ADC6_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_VADCG6SR0.U,  IRQ_CLEAR_MASK , \
                     (IRQ_ADC6_SR0_TOS | IRQ_ADC6_SR0_PRIO));
  IRQ_SFR_MODIFY32 (SRC_VADCG6SR1.U,  IRQ_CLEAR_MASK , \
                     (IRQ_ADC6_SR1_TOS | IRQ_ADC6_SR1_PRIO));
  IRQ_SFR_MODIFY32 (SRC_VADCG6SR2.U,  IRQ_CLEAR_MASK , \
                     (IRQ_ADC6_SR2_TOS | IRQ_ADC6_SR2_PRIO));
  IRQ_SFR_MODIFY32 (SRC_VADCG6SR3.U,  IRQ_CLEAR_MASK , \
                     (IRQ_ADC6_SR3_TOS | IRQ_ADC6_SR3_PRIO));
  #endif

  #if (IRQ_ADC7_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_VADCG7SR0.U,  IRQ_CLEAR_MASK , \
                     (IRQ_ADC7_SR0_TOS | IRQ_ADC7_SR0_PRIO));
  IRQ_SFR_MODIFY32 (SRC_VADCG7SR1.U,  IRQ_CLEAR_MASK , \
                     (IRQ_ADC7_SR1_TOS | IRQ_ADC7_SR1_PRIO));
  IRQ_SFR_MODIFY32 (SRC_VADCG7SR2.U,  IRQ_CLEAR_MASK , \
                     (IRQ_ADC7_SR2_TOS | IRQ_ADC7_SR2_PRIO));
  IRQ_SFR_MODIFY32 (SRC_VADCG7SR3.U,  IRQ_CLEAR_MASK , \
                     (IRQ_ADC7_SR3_TOS | IRQ_ADC7_SR3_PRIO));
  #endif

  #if (IRQ_ADC8_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_VADCG8SR0.U,  IRQ_CLEAR_MASK , \
                     (IRQ_ADC8_SR0_TOS | IRQ_ADC8_SR0_PRIO));
  IRQ_SFR_MODIFY32 (SRC_VADCG8SR1.U,  IRQ_CLEAR_MASK , \
                     (IRQ_ADC8_SR1_TOS | IRQ_ADC8_SR1_PRIO));
  IRQ_SFR_MODIFY32 (SRC_VADCG8SR2.U,  IRQ_CLEAR_MASK , \
                     (IRQ_ADC8_SR2_TOS | IRQ_ADC8_SR2_PRIO));
  IRQ_SFR_MODIFY32 (SRC_VADCG8SR3.U,  IRQ_CLEAR_MASK , \
                     (IRQ_ADC8_SR3_TOS | IRQ_ADC8_SR3_PRIO));
  #endif

  #if (IRQ_ADC9_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_VADCG9SR0.U,  IRQ_CLEAR_MASK , \
                     (IRQ_ADC9_SR0_TOS | IRQ_ADC9_SR0_PRIO));
  IRQ_SFR_MODIFY32 (SRC_VADCG9SR1.U,  IRQ_CLEAR_MASK , \
                     (IRQ_ADC9_SR1_TOS | IRQ_ADC9_SR1_PRIO));
  IRQ_SFR_MODIFY32 (SRC_VADCG9SR2.U,  IRQ_CLEAR_MASK , \
                     (IRQ_ADC9_SR2_TOS | IRQ_ADC9_SR2_PRIO));
  IRQ_SFR_MODIFY32 (SRC_VADCG9SR3.U,  IRQ_CLEAR_MASK , \
                     (IRQ_ADC9_SR3_TOS | IRQ_ADC9_SR3_PRIO));
  #endif

  #if (IRQ_ADC10_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_VADCG10SR0.U,  IRQ_CLEAR_MASK , \
                     (IRQ_ADC10_SR0_TOS | IRQ_ADC10_SR0_PRIO));
  IRQ_SFR_MODIFY32 (SRC_VADCG10SR1.U,  IRQ_CLEAR_MASK , \
                     (IRQ_ADC10_SR1_TOS | IRQ_ADC10_SR1_PRIO));
  IRQ_SFR_MODIFY32 (SRC_VADCG10SR2.U,  IRQ_CLEAR_MASK , \
                     (IRQ_ADC10_SR2_TOS | IRQ_ADC10_SR2_PRIO));
  IRQ_SFR_MODIFY32 (SRC_VADCG10SR3.U,  IRQ_CLEAR_MASK , \
                     (IRQ_ADC10_SR3_TOS | IRQ_ADC10_SR3_PRIO));
  #endif

  #if (IRQ_ADCCG0_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_VADCCG0SR0.U,  IRQ_CLEAR_MASK , \
                     (IRQ_ADCCG0_SR0_TOS | IRQ_ADCCG0_SR0_PRIO));
  IRQ_SFR_MODIFY32 (SRC_VADCCG0SR1.U,  IRQ_CLEAR_MASK , \
                     (IRQ_ADCCG0_SR1_TOS | IRQ_ADCCG0_SR1_PRIO));
  IRQ_SFR_MODIFY32 (SRC_VADCCG0SR2.U,  IRQ_CLEAR_MASK , \
                     (IRQ_ADCCG0_SR2_TOS | IRQ_ADCCG0_SR2_PRIO));
  IRQ_SFR_MODIFY32 (SRC_VADCCG0SR3.U,  IRQ_CLEAR_MASK , \
                     (IRQ_ADCCG0_SR3_TOS | IRQ_ADCCG0_SR3_PRIO));
  #endif

  #if (IRQ_ADCCG1_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_VADCCG1SR0.U,  IRQ_CLEAR_MASK , \
                     (IRQ_ADCCG1_SR0_TOS | IRQ_ADCCG1_SR0_PRIO));
  IRQ_SFR_MODIFY32 (SRC_VADCCG1SR1.U,  IRQ_CLEAR_MASK , \
                     (IRQ_ADCCG1_SR1_TOS | IRQ_ADCCG1_SR1_PRIO));
  IRQ_SFR_MODIFY32 (SRC_VADCCG1SR2.U,  IRQ_CLEAR_MASK , \
                     (IRQ_ADCCG1_SR2_TOS | IRQ_ADCCG1_SR2_PRIO));
  IRQ_SFR_MODIFY32 (SRC_VADCCG1SR3.U,  IRQ_CLEAR_MASK , \
                     (IRQ_ADCCG1_SR3_TOS | IRQ_ADCCG1_SR3_PRIO));
  #endif


  #endif /* (IRQ_ADC_EXIST == STD_ON) */
}

/*******************************************************************************
** Syntax :  void IrqDsadc_Init(void)                                         **
**                                                                            **
** Service ID:  none                                                          **
**                                                                            **
** Sync/Async:  Synchronous                                                   **
**                                                                            **
** Reentrancy:  non reentrant                                                 **
**                                                                            **
** Parameters (in): none                                                      **
**                                                                            **
** Parameters (out): none                                                     **
**                                                                            **
** Return value: none                                                         **
**                                                                            **
** Description : To set the interrupt priority for various                    **
**               service nodes according to priority configurartion.          **
**                                                                            **
*******************************************************************************/
void IrqDsadc_Init(void)
{
  #if (IRQ_DSADC_EXIST == STD_ON)

  #if (IRQ_DSADC_A0_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_DSADCSRA0.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DSADC_SRA0_TOS | IRQ_DSADC_SRA0_PRIO));
  #endif

  #if (IRQ_DSADC_A1_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_DSADCSRA1.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DSADC_SRA1_TOS | IRQ_DSADC_SRA1_PRIO));
  #endif
  

  #if (IRQ_DSADC_A2_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_DSADCSRA2.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DSADC_SRA2_TOS | IRQ_DSADC_SRA2_PRIO));
  #endif

  #if (IRQ_DSADC_A3_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_DSADCSRA3.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DSADC_SRA3_TOS | IRQ_DSADC_SRA3_PRIO));
  #endif

  #if (IRQ_DSADC_A4_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_DSADCSRA4.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DSADC_SRA4_TOS | IRQ_DSADC_SRA4_PRIO));
  #endif

  #if (IRQ_DSADC_A5_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_DSADCSRA5.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DSADC_SRA5_TOS | IRQ_DSADC_SRA5_PRIO));
  #endif

  #if (IRQ_DSADC_A6_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_DSADCSRA6.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DSADC_SRA6_TOS | IRQ_DSADC_SRA6_PRIO));
  #endif

  #if (IRQ_DSADC_A7_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_DSADCSRA7.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DSADC_SRA7_TOS | IRQ_DSADC_SRA7_PRIO));
  #endif

  #if (IRQ_DSADC_A8_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_DSADCSRA8.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DSADC_SRA8_TOS | IRQ_DSADC_SRA8_PRIO));
  #endif

  #if (IRQ_DSADC_A9_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_DSADCSRA9.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DSADC_SRA9_TOS | IRQ_DSADC_SRA9_PRIO));
  #endif

  #if (IRQ_DSADC_M0_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_DSADCSRM0.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DSADC_SRM0_TOS | IRQ_DSADC_SRM0_PRIO));
  #endif

  #if (IRQ_DSADC_M1_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_DSADCSRM1.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DSADC_SRM1_TOS | IRQ_DSADC_SRM1_PRIO));
  #endif

  #if (IRQ_DSADC_M2_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_DSADCSRM2.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DSADC_SRM2_TOS | IRQ_DSADC_SRM2_PRIO));
  #endif

  #if (IRQ_DSADC_M3_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_DSADCSRM3.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DSADC_SRM3_TOS | IRQ_DSADC_SRM3_PRIO));
  #endif

  #if (IRQ_DSADC_M4_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_DSADCSRM4.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DSADC_SRM4_TOS | IRQ_DSADC_SRM4_PRIO));
  #endif

  #if (IRQ_DSADC_M5_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_DSADCSRM5.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DSADC_SRM5_TOS | IRQ_DSADC_SRM5_PRIO));
  #endif

  #if (IRQ_DSADC_M6_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_DSADCSRM6.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DSADC_SRM6_TOS | IRQ_DSADC_SRM6_PRIO));
  #endif

  #if (IRQ_DSADC_M7_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_DSADCSRM7.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DSADC_SRM7_TOS | IRQ_DSADC_SRM7_PRIO));
  #endif

  #if (IRQ_DSADC_M8_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_DSADCSRM8.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DSADC_SRM8_TOS | IRQ_DSADC_SRM8_PRIO));
  #endif

  #if (IRQ_DSADC_M9_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_DSADCSRM9.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DSADC_SRM9_TOS | IRQ_DSADC_SRM9_PRIO));
  #endif

  #endif
}

/*******************************************************************************
** Syntax :  void IrqMsc_Init(void)                                           **
**                                                                            **
** Service ID:  none                                                          **
**                                                                            **
** Sync/Async:  Synchronous                                                   **
**                                                                            **
** Reentrancy:  non reentrant                                                 **
**                                                                            **
** Parameters (in): none                                                      **
**                                                                            **
** Parameters (out): none                                                     **
**                                                                            **
** Return value: none                                                         **
**                                                                            **
** Description : To set the interrupt priority for                            **
**               service nodes according to priority configurartion.          **
**                                                                            **
*******************************************************************************/

void IrqMsc_Init(void)
{

  #if (IRQ_MSC_EXIST == STD_ON)

  #if (IRQ_MSC0_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_MSC0SR0.U,  IRQ_CLEAR_MASK , \
                     (IRQ_MSC0_SR0_TOS | IRQ_MSC0_SR0_PRIO));
  IRQ_SFR_MODIFY32 (SRC_MSC0SR1.U,  IRQ_CLEAR_MASK , \
                     (IRQ_MSC0_SR1_TOS | IRQ_MSC0_SR1_PRIO));
  IRQ_SFR_MODIFY32 (SRC_MSC0SR2.U,  IRQ_CLEAR_MASK , \
                     (IRQ_MSC0_SR2_TOS | IRQ_MSC0_SR2_PRIO));
  IRQ_SFR_MODIFY32 (SRC_MSC0SR3.U,  IRQ_CLEAR_MASK , \
                     (IRQ_MSC0_SR3_TOS | IRQ_MSC0_SR3_PRIO));
  IRQ_SFR_MODIFY32 (SRC_MSC0SR4.U,  IRQ_CLEAR_MASK , \
                     (IRQ_MSC0_SR4_TOS | IRQ_MSC0_SR4_PRIO));
  #endif/* End for IRQ_MSC0_EXIST == STD_ON*/

  #if (IRQ_MSC1_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_MSC1SR0.U,  IRQ_CLEAR_MASK , \
                     (IRQ_MSC1_SR0_TOS | IRQ_MSC1_SR0_PRIO));
  IRQ_SFR_MODIFY32 (SRC_MSC1SR1.U,  IRQ_CLEAR_MASK , \
                     (IRQ_MSC1_SR1_TOS | IRQ_MSC1_SR1_PRIO));
  IRQ_SFR_MODIFY32 (SRC_MSC1SR2.U,  IRQ_CLEAR_MASK , \
                     (IRQ_MSC1_SR2_TOS | IRQ_MSC1_SR2_PRIO));
  IRQ_SFR_MODIFY32 (SRC_MSC1SR3.U,  IRQ_CLEAR_MASK , \
                     (IRQ_MSC1_SR3_TOS | IRQ_MSC1_SR3_PRIO));
  IRQ_SFR_MODIFY32 (SRC_MSC1SR4.U,  IRQ_CLEAR_MASK , \
                     (IRQ_MSC1_SR4_TOS | IRQ_MSC1_SR4_PRIO));
  #endif/* End for IRQ_MSC1_EXIST == STD_ON*/

  #if (IRQ_MSC2_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_MSC2SR0.U,  IRQ_CLEAR_MASK , \
                     (IRQ_MSC2_SR0_TOS | IRQ_MSC2_SR0_PRIO));
  IRQ_SFR_MODIFY32 (SRC_MSC2SR1.U,  IRQ_CLEAR_MASK , \
                     (IRQ_MSC2_SR1_TOS | IRQ_MSC2_SR1_PRIO));
  IRQ_SFR_MODIFY32 (SRC_MSC2SR2.U,  IRQ_CLEAR_MASK , \
                     (IRQ_MSC2_SR2_TOS | IRQ_MSC2_SR2_PRIO));
  IRQ_SFR_MODIFY32 (SRC_MSC2SR3.U,  IRQ_CLEAR_MASK , \
                     (IRQ_MSC2_SR3_TOS | IRQ_MSC2_SR3_PRIO));
  IRQ_SFR_MODIFY32 (SRC_MSC2SR4.U,  IRQ_CLEAR_MASK , \
                     (IRQ_MSC2_SR4_TOS | IRQ_MSC2_SR4_PRIO));
  #endif/* End for IRQ_MSC2_EXIST == STD_ON*/

  #endif /*End for IRQ_MSC_EXIST == STD_ON*/
}

/*******************************************************************************
** Syntax :  void IrqEray_Init(void)                                          **
**                                                                            **
** Service ID:  none                                                          **
**                                                                            **
** Sync/Async:  Synchronous                                                   **
**                                                                            **
** Reentrancy:  non reentrant                                                 **
**                                                                            **
** Parameters (in): none                                                      **
**                                                                            **
** Parameters (out): none                                                     **
**                                                                            **
** Return value: none                                                         **
**                                                                            **
** Description : To set the interrupt priority for                            **
**               service nodes according to priority configurartion.          **
**                                                                            **
*******************************************************************************/

void IrqFlexray_Init(void)
{
  #if (IRQ_FLEXRAY_EXIST == STD_ON)

  #if (IRQ_FLEXRAY0_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_ERAY_ERAY0_INT0.U,  IRQ_CLEAR_MASK , \
                     (IRQ_FLEXRAY0_SR0_TOS | IRQ_FLEXRAY0_SR0_PRIO));
  IRQ_SFR_MODIFY32 (SRC_ERAY_ERAY0_INT1.U,  IRQ_CLEAR_MASK , \
                     (IRQ_FLEXRAY0_SR1_TOS | IRQ_FLEXRAY0_SR1_PRIO));
  IRQ_SFR_MODIFY32 (SRC_ERAY_ERAY0_TINT0.U,  IRQ_CLEAR_MASK , \
                     (IRQ_FLEXRAY0_TIMER_INT0_TOS | IRQ_FLEXRAY0_TIMER_INT0_PRIO));
  IRQ_SFR_MODIFY32 (SRC_ERAY_ERAY0_TINT1.U,  IRQ_CLEAR_MASK , \
                (IRQ_FLEXRAY0_TIMER_INT1_TOS | IRQ_FLEXRAY0_TIMER_INT1_PRIO));
  IRQ_SFR_MODIFY32 (SRC_ERAY_ERAY0_NDAT0.U,  IRQ_CLEAR_MASK , \
                    (IRQ_FLEXRAY0_NEW_DATA0_TOS | IRQ_FLEXRAY0_NEW_DATA0_PRIO));
  IRQ_SFR_MODIFY32 (SRC_ERAY_ERAY0_NDAT1.U ,  IRQ_CLEAR_MASK , \
                    (IRQ_FLEXRAY0_NEW_DATA1_TOS | IRQ_FLEXRAY0_NEW_DATA1_PRIO));
  IRQ_SFR_MODIFY32 (SRC_ERAY_ERAY0_MBSC0.U,  IRQ_CLEAR_MASK , \
                       (IRQ_FLEXRAY0_MBSC0_TOS | IRQ_FLEXRAY0_MBSC0_PRIO));
  IRQ_SFR_MODIFY32 (SRC_ERAY_ERAY0_MBSC1.U,  IRQ_CLEAR_MASK , \
                       (IRQ_FLEXRAY0_MBSC1_TOS | IRQ_FLEXRAY0_MBSC1_PRIO));
  IRQ_SFR_MODIFY32 (SRC_ERAY_ERAY0_OBUSY.U,  IRQ_CLEAR_MASK , \
                     (IRQ_FLEXRAY0_OB_BUSY_TOS | IRQ_FLEXRAY0_OB_BUSY_PRIO));
  IRQ_SFR_MODIFY32 (SRC_ERAY_ERAY0_IBUSY.U,  IRQ_CLEAR_MASK , \
                     (IRQ_FLEXRAY0_IB_BUSY_TOS | IRQ_FLEXRAY0_IB_BUSY_PRIO));
  #endif

  #if (IRQ_FLEXRAY1_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_ERAY_ERAY1_INT0.U,  IRQ_CLEAR_MASK , \
                     (IRQ_FLEXRAY1_SR0_TOS | IRQ_FLEXRAY1_SR0_PRIO));
  IRQ_SFR_MODIFY32 (SRC_ERAY_ERAY1_INT1.U,  IRQ_CLEAR_MASK , \
                     (IRQ_FLEXRAY1_SR1_TOS | IRQ_FLEXRAY1_SR1_PRIO));
  IRQ_SFR_MODIFY32 (SRC_ERAY_ERAY1_TINT0.U,  IRQ_CLEAR_MASK , \
                  (IRQ_FLEXRAY1_TIMER_INT0_TOS | IRQ_FLEXRAY1_TIMER_INT0_PRIO));
  IRQ_SFR_MODIFY32 (SRC_ERAY_ERAY1_TINT1.U,  IRQ_CLEAR_MASK , \
                  (IRQ_FLEXRAY1_TIMER_INT1_TOS | IRQ_FLEXRAY1_TIMER_INT1_PRIO));
  IRQ_SFR_MODIFY32 (SRC_ERAY_ERAY1_NDAT0.U,  IRQ_CLEAR_MASK , \
                    (IRQ_FLEXRAY1_NEW_DATA0_TOS | IRQ_FLEXRAY1_NEW_DATA0_PRIO));
  IRQ_SFR_MODIFY32 (SRC_ERAY_ERAY1_NDAT1.U,  IRQ_CLEAR_MASK , \
                    (IRQ_FLEXRAY1_NEW_DATA1_TOS | IRQ_FLEXRAY1_NEW_DATA1_PRIO));
  IRQ_SFR_MODIFY32 (SRC_ERAY_ERAY1_MBSC0.U,  IRQ_CLEAR_MASK , \
                     (IRQ_FLEXRAY1_MBSC0_TOS | IRQ_FLEXRAY1_MBSC0_PRIO));
  IRQ_SFR_MODIFY32 (SRC_ERAY_ERAY1_MBSC1.U,  IRQ_CLEAR_MASK , \
                     (IRQ_FLEXRAY1_MBSC1_TOS | IRQ_FLEXRAY1_MBSC1_PRIO));
  IRQ_SFR_MODIFY32 (SRC_ERAY_ERAY1_OBUSY.U,  IRQ_CLEAR_MASK , \
                     (IRQ_FLEXRAY1_OB_BUSY_TOS | IRQ_FLEXRAY1_OB_BUSY_PRIO));
  IRQ_SFR_MODIFY32 (SRC_ERAY_ERAY1_IBUSY.U,  IRQ_CLEAR_MASK , \
                     (IRQ_FLEXRAY1_IB_BUSY_TOS | IRQ_FLEXRAY1_IB_BUSY_PRIO));
  #endif

  #endif
}

/*******************************************************************************
** Syntax :  void IrqEthernet_Init(void)                                      **
**                                                                            **
** Service ID:  none                                                          **
**                                                                            **
** Sync/Async:  Synchronous                                                   **
**                                                                            **
** Reentrancy:  non reentrant                                                 **
**                                                                            **
** Parameters (in): none                                                      **
**                                                                            **
** Parameters (out): none                                                     **
**                                                                            **
** Return value: none                                                         **
**                                                                            **
** Description : To set the interrupt priority for                            **
**               service nodes according to priority configurartion.          **
**                                                                            **
*******************************************************************************/

void IrqEthernet_Init(void)
{
  #if (IRQ_ETH_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_ETH.U , IRQ_CLEAR_MASK , \
                     (IRQ_ETH_SR_TOS | IRQ_ETH_SR_PRIO));
  #endif
}

/*******************************************************************************
** Syntax :  void IrqDma_Init(void)                                           **
**                                                                            **
** Service ID:  none                                                          **
**                                                                            **
** Sync/Async:  Synchronous                                                   **
**                                                                            **
** Reentrancy:  non reentrant                                                 **
**                                                                            **
** Parameters (in): none                                                      **
**                                                                            **
** Parameters (out): none                                                     **
**                                                                            **
** Return value: none                                                         **
**                                                                            **
** Description : To set the interrupt priority for                            **
**               service nodes according to priority configurartion.          **
**                                                                            **
*******************************************************************************/

void IrqDma_Init(void)
{
  #if (IRQ_DMA_EXIST == STD_ON)

    IRQ_SFR_MODIFY32 (SRC_DMAERR.U , IRQ_CLEAR_MASK , \
                       (IRQ_DMA_ERR_SR_TOS | IRQ_DMA_ERR_SR_PRIO));

  #if (IRQ_DMA_CH0TO47_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_DMACH0.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL0_SR_TOS | IRQ_DMA_CHANNEL0_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH1.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL1_SR_TOS | IRQ_DMA_CHANNEL1_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH2.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL2_SR_TOS | IRQ_DMA_CHANNEL2_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH3.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL3_SR_TOS | IRQ_DMA_CHANNEL3_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH4.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL4_SR_TOS | IRQ_DMA_CHANNEL4_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH5.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL5_SR_TOS | IRQ_DMA_CHANNEL5_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH6.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL6_SR_TOS | IRQ_DMA_CHANNEL6_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH7.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL7_SR_TOS | IRQ_DMA_CHANNEL7_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH8.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL8_SR_TOS | IRQ_DMA_CHANNEL8_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH9.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL9_SR_TOS | IRQ_DMA_CHANNEL9_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH10.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL10_SR_TOS | IRQ_DMA_CHANNEL10_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH11.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL11_SR_TOS | IRQ_DMA_CHANNEL11_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH12.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL12_SR_TOS | IRQ_DMA_CHANNEL12_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH13.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL13_SR_TOS | IRQ_DMA_CHANNEL13_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH14.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL14_SR_TOS | IRQ_DMA_CHANNEL14_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH15.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL15_SR_TOS | IRQ_DMA_CHANNEL15_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH16.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL16_SR_TOS | IRQ_DMA_CHANNEL16_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH17.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL17_SR_TOS | IRQ_DMA_CHANNEL17_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH18.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL18_SR_TOS | IRQ_DMA_CHANNEL18_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH19.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL19_SR_TOS | IRQ_DMA_CHANNEL19_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH20.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL20_SR_TOS | IRQ_DMA_CHANNEL20_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH21.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL21_SR_TOS | IRQ_DMA_CHANNEL21_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH22.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL22_SR_TOS | IRQ_DMA_CHANNEL22_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH23.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL23_SR_TOS | IRQ_DMA_CHANNEL23_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH24.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL24_SR_TOS | IRQ_DMA_CHANNEL24_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH25.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL25_SR_TOS | IRQ_DMA_CHANNEL25_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH26.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL26_SR_TOS | IRQ_DMA_CHANNEL26_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH27.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL27_SR_TOS | IRQ_DMA_CHANNEL27_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH28.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL28_SR_TOS | IRQ_DMA_CHANNEL28_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH29.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL29_SR_TOS | IRQ_DMA_CHANNEL29_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH30.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL30_SR_TOS | IRQ_DMA_CHANNEL30_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH31.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL31_SR_TOS | IRQ_DMA_CHANNEL31_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH32.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL32_SR_TOS | IRQ_DMA_CHANNEL32_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH33.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL33_SR_TOS | IRQ_DMA_CHANNEL33_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH34.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL34_SR_TOS | IRQ_DMA_CHANNEL34_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH35.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL35_SR_TOS | IRQ_DMA_CHANNEL35_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH36.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL36_SR_TOS | IRQ_DMA_CHANNEL36_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH37.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL37_SR_TOS | IRQ_DMA_CHANNEL37_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH38.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL38_SR_TOS | IRQ_DMA_CHANNEL38_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH39.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL39_SR_TOS | IRQ_DMA_CHANNEL39_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH40.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL40_SR_TOS | IRQ_DMA_CHANNEL40_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH41.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL41_SR_TOS | IRQ_DMA_CHANNEL41_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH42.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL42_SR_TOS | IRQ_DMA_CHANNEL42_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH43.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL43_SR_TOS | IRQ_DMA_CHANNEL43_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH44.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL44_SR_TOS | IRQ_DMA_CHANNEL44_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH45.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL45_SR_TOS | IRQ_DMA_CHANNEL45_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH46.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL46_SR_TOS | IRQ_DMA_CHANNEL46_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH47.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL47_SR_TOS | IRQ_DMA_CHANNEL47_SR_PRIO));
  #endif

  #if (IRQ_DMA_CH48TO63_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_DMACH48.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL48_SR_TOS | IRQ_DMA_CHANNEL48_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH49.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL49_SR_TOS | IRQ_DMA_CHANNEL49_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH50.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL50_SR_TOS | IRQ_DMA_CHANNEL50_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH51.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL51_SR_TOS | IRQ_DMA_CHANNEL51_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH52.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL52_SR_TOS | IRQ_DMA_CHANNEL52_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH53.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL53_SR_TOS | IRQ_DMA_CHANNEL53_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH54.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL54_SR_TOS | IRQ_DMA_CHANNEL54_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH55.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL55_SR_TOS | IRQ_DMA_CHANNEL55_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH56.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL56_SR_TOS | IRQ_DMA_CHANNEL56_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH57.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL57_SR_TOS | IRQ_DMA_CHANNEL57_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH58.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL58_SR_TOS | IRQ_DMA_CHANNEL58_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH59.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL59_SR_TOS | IRQ_DMA_CHANNEL59_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH60.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL60_SR_TOS | IRQ_DMA_CHANNEL60_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH61.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL61_SR_TOS | IRQ_DMA_CHANNEL61_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH62.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL62_SR_TOS | IRQ_DMA_CHANNEL62_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH63.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL63_SR_TOS | IRQ_DMA_CHANNEL63_SR_PRIO));
  #endif

  #if (IRQ_DMA_CH64TO127_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_DMACH64.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL64_SR_TOS | IRQ_DMA_CHANNEL64_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH65.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL65_SR_TOS | IRQ_DMA_CHANNEL65_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH66.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL66_SR_TOS | IRQ_DMA_CHANNEL66_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH67.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL67_SR_TOS | IRQ_DMA_CHANNEL67_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH68.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL68_SR_TOS | IRQ_DMA_CHANNEL68_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH69.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL69_SR_TOS | IRQ_DMA_CHANNEL69_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH70.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL70_SR_TOS | IRQ_DMA_CHANNEL70_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH71.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL71_SR_TOS | IRQ_DMA_CHANNEL71_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH72.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL72_SR_TOS | IRQ_DMA_CHANNEL72_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH73.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL73_SR_TOS | IRQ_DMA_CHANNEL73_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH74.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL74_SR_TOS | IRQ_DMA_CHANNEL74_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH75.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL75_SR_TOS | IRQ_DMA_CHANNEL75_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH76.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL76_SR_TOS | IRQ_DMA_CHANNEL76_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH77.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL77_SR_TOS | IRQ_DMA_CHANNEL77_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH78.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL78_SR_TOS | IRQ_DMA_CHANNEL78_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH79.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL79_SR_TOS | IRQ_DMA_CHANNEL79_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH80.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL80_SR_TOS | IRQ_DMA_CHANNEL80_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH81.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL81_SR_TOS | IRQ_DMA_CHANNEL81_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH82.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL82_SR_TOS | IRQ_DMA_CHANNEL82_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH83.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL83_SR_TOS | IRQ_DMA_CHANNEL83_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH84.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL84_SR_TOS | IRQ_DMA_CHANNEL84_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH85.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL85_SR_TOS | IRQ_DMA_CHANNEL85_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH86.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL86_SR_TOS | IRQ_DMA_CHANNEL86_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH87.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL87_SR_TOS | IRQ_DMA_CHANNEL87_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH88.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL88_SR_TOS | IRQ_DMA_CHANNEL88_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH89.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL89_SR_TOS | IRQ_DMA_CHANNEL89_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH90.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL90_SR_TOS | IRQ_DMA_CHANNEL90_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH91.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL91_SR_TOS | IRQ_DMA_CHANNEL91_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH92.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL92_SR_TOS | IRQ_DMA_CHANNEL92_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH93.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL93_SR_TOS | IRQ_DMA_CHANNEL93_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH94.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL94_SR_TOS | IRQ_DMA_CHANNEL94_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH95.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL95_SR_TOS | IRQ_DMA_CHANNEL95_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH96.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL96_SR_TOS | IRQ_DMA_CHANNEL96_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH97.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL97_SR_TOS | IRQ_DMA_CHANNEL97_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH98.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL98_SR_TOS | IRQ_DMA_CHANNEL98_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH99.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL99_SR_TOS | IRQ_DMA_CHANNEL99_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH100.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL100_SR_TOS | IRQ_DMA_CHANNEL100_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH101.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL101_SR_TOS | IRQ_DMA_CHANNEL101_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH102.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL102_SR_TOS | IRQ_DMA_CHANNEL102_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH103.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL103_SR_TOS | IRQ_DMA_CHANNEL103_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH104.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL104_SR_TOS | IRQ_DMA_CHANNEL104_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH105.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL104_SR_TOS | IRQ_DMA_CHANNEL104_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH106.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL106_SR_TOS | IRQ_DMA_CHANNEL106_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH107.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL107_SR_TOS | IRQ_DMA_CHANNEL107_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH108.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL108_SR_TOS | IRQ_DMA_CHANNEL108_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH109.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL109_SR_TOS | IRQ_DMA_CHANNEL109_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH110.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL110_SR_TOS | IRQ_DMA_CHANNEL110_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH111.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL111_SR_TOS | IRQ_DMA_CHANNEL111_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH112.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL112_SR_TOS | IRQ_DMA_CHANNEL112_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH113.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL113_SR_TOS | IRQ_DMA_CHANNEL113_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH114.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL114_SR_TOS | IRQ_DMA_CHANNEL114_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH115.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL115_SR_TOS | IRQ_DMA_CHANNEL115_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH116.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL116_SR_TOS | IRQ_DMA_CHANNEL116_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH117.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL117_SR_TOS | IRQ_DMA_CHANNEL117_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH118.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL118_SR_TOS | IRQ_DMA_CHANNEL118_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH119.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL119_SR_TOS | IRQ_DMA_CHANNEL119_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH120.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL120_SR_TOS | IRQ_DMA_CHANNEL120_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH121.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL121_SR_TOS | IRQ_DMA_CHANNEL121_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH122.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL122_SR_TOS | IRQ_DMA_CHANNEL122_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH123.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL123_SR_TOS | IRQ_DMA_CHANNEL123_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH124.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL124_SR_TOS | IRQ_DMA_CHANNEL124_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH125.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL125_SR_TOS | IRQ_DMA_CHANNEL125_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH126.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL126_SR_TOS | IRQ_DMA_CHANNEL126_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_DMACH127.U,  IRQ_CLEAR_MASK , \
                     (IRQ_DMA_CHANNEL127_SR_TOS | IRQ_DMA_CHANNEL127_SR_PRIO));
  #endif

  #endif/*End of IRQ_DMA_EXIST*/
}
#endif /* (IFX_MCAL_USED == STD_ON) */
/*******************************************************************************
** Syntax :  void IrqStm_Init(void)                                           **
**                                                                            **
** Service ID:  none                                                          **
**                                                                            **
** Sync/Async:  Synchronous                                                   **
**                                                                            **
** Reentrancy:  non reentrant                                                 **
**                                                                            **
** Parameters (in): none                                                      **
**                                                                            **
** Parameters (out): none                                                     **
**                                                                            **
** Return value: none                                                         **
**                                                                            **
** Description : To set the interrupt priority for                            **
**               service nodes according to priority configurartion.          **
**                                                                            **
*******************************************************************************/

void IrqStm_Init(void)
{
  #if (IRQ_STM_EXIST == STD_ON)

  #if (IRQ_STM0_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_STM0SR0.U,  IRQ_CLEAR_MASK , \
                     (IRQ_STM0_SR0_TOS | IRQ_STM0_SR0_PRIO));
  IRQ_SFR_MODIFY32 (SRC_STM0SR1.U,  IRQ_CLEAR_MASK , \
                     (IRQ_STM0_SR1_TOS | IRQ_STM0_SR1_PRIO));
  #endif

  #if (IRQ_STM1_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_STM1SR0.U,  IRQ_CLEAR_MASK , \
                     (IRQ_STM1_SR0_TOS | IRQ_STM1_SR0_PRIO));
  IRQ_SFR_MODIFY32 (SRC_STM1SR1.U,  IRQ_CLEAR_MASK , \
                     (IRQ_STM1_SR1_TOS | IRQ_STM1_SR1_PRIO));
  #endif

  #if (IRQ_STM2_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_STM2SR0.U,  IRQ_CLEAR_MASK , \
                     (IRQ_STM2_SR0_TOS | IRQ_STM2_SR0_PRIO));
  IRQ_SFR_MODIFY32 (SRC_STM2SR1.U,  IRQ_CLEAR_MASK , \
                     (IRQ_STM2_SR1_TOS | IRQ_STM2_SR1_PRIO));
  #endif

  #endif
}

#if (IFX_MCAL_USED == STD_ON)
/*******************************************************************************
** Syntax :  void IrqScu_Init(void)                                           **
**                                                                            **
** Service ID:  none                                                          **
**                                                                            **
** Sync/Async:  Synchronous                                                   **
**                                                                            **
** Reentrancy:  non reentrant                                                 **
**                                                                            **
** Parameters (in): none                                                      **
**                                                                            **
** Parameters (out): none                                                     **
**                                                                            **
** Return value: none                                                         **
**                                                                            **
** Description : To set the interrupt priority for                            **
**               service nodes according to priority configurartion.          **
**                                                                            **
*******************************************************************************/

void IrqScu_Init(void)
{
  #if (IRQ_SCU_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_SCUDTS.U ,  IRQ_CLEAR_MASK , \
                     (IRQ_SCU_DTS_BUSY_SR_TOS | IRQ_SCU_DTS_BUSY_SR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_SCUERU0.U,  IRQ_CLEAR_MASK , \
                     (IRQ_SCU_ERU_SR0_TOS | IRQ_SCU_ERU_SR0_PRIO));
  IRQ_SFR_MODIFY32 (SRC_SCUERU1.U,  IRQ_CLEAR_MASK , \
                     (IRQ_SCU_ERU_SR1_TOS | IRQ_SCU_ERU_SR1_PRIO));
  IRQ_SFR_MODIFY32 (SRC_SCUERU2.U,  IRQ_CLEAR_MASK , \
                     (IRQ_SCU_ERU_SR2_TOS | IRQ_SCU_ERU_SR2_PRIO));
  IRQ_SFR_MODIFY32 (SRC_SCUERU3.U,  IRQ_CLEAR_MASK , \
                     (IRQ_SCU_ERU_SR3_TOS | IRQ_SCU_ERU_SR3_PRIO));
  #endif


}

/*******************************************************************************
** Syntax :  void IrqPmu_Init(void)                                           **
**                                                                            **
** Service ID:  none                                                          **
**                                                                            **
** Sync/Async:  Synchronous                                                   **
**                                                                            **
** Reentrancy:  non reentrant                                                 **
**                                                                            **
** Parameters (in): none                                                      **
**                                                                            **
** Parameters (out): none                                                     **
**                                                                            **
** Return value: none                                                         **
**                                                                            **
** Description : To set the interrupt priority for                            **
**               service nodes according to priority configurartion.          **
**                                                                            **
*******************************************************************************/
void IrqPmu_Init(void)
{
  #if (IRQ_PMU0_EXIST == STD_ON)

  #if (IRQ_PMU0_SR0_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_PMU00.U,  IRQ_CLEAR_MASK , \
                     (IRQ_PMU0_SR0_TOS | IRQ_PMU0_SR0_PRIO));
  #endif

  #if (IRQ_PMU0_SR1_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_PMU01.U,  IRQ_CLEAR_MASK , \
                     (IRQ_PMU0_SR1_TOS | IRQ_PMU0_SR1_PRIO));
  #endif

  #endif
}


/*******************************************************************************
** Syntax :  void IrqSent_Init(void)                                          **
**                                                                            **
** Service ID:  none                                                          **
**                                                                            **
** Sync/Async:  Synchronous                                                   **
**                                                                            **
** Reentrancy:  non reentrant                                                 **
**                                                                            **
** Parameters (in): none                                                      **
**                                                                            **
** Parameters (out): none                                                     **
**                                                                            **
** Return value: none                                                         **
**                                                                            **
** Description : To set the interrupt priority for                            **
**               service nodes according to priority configurartion.          **
**                                                                            **
*******************************************************************************/

void IrqSent_Init(void)
{
  #if (IRQ_SENT_EXIST == STD_ON)

  #if (IRQ_SENT0_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_SENT0.U,  IRQ_CLEAR_MASK , \
                     (IRQ_SENT_SR0_TOS | IRQ_SENT_SR0_PRIO));
  #endif
  #if (IRQ_SENT1_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_SENT1.U,  IRQ_CLEAR_MASK , \
                     (IRQ_SENT_SR1_TOS | IRQ_SENT_SR1_PRIO));
  #endif
  #if (IRQ_SENT2_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_SENT2.U,  IRQ_CLEAR_MASK , \
                     (IRQ_SENT_SR2_TOS | IRQ_SENT_SR2_PRIO));
  #endif
  #if (IRQ_SENT3_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_SENT3.U,  IRQ_CLEAR_MASK , \
                     (IRQ_SENT_SR3_TOS | IRQ_SENT_SR3_PRIO));
  #endif
  #if (IRQ_SENT4_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_SENT4.U,  IRQ_CLEAR_MASK , \
                     (IRQ_SENT_SR4_TOS | IRQ_SENT_SR4_PRIO));
  #endif
  #if (IRQ_SENT5_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_SENT5.U,  IRQ_CLEAR_MASK , \
                     (IRQ_SENT_SR5_TOS | IRQ_SENT_SR5_PRIO));
  #endif
  #if (IRQ_SENT6_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_SENT6.U,  IRQ_CLEAR_MASK , \
                     (IRQ_SENT_SR6_TOS | IRQ_SENT_SR6_PRIO));
  #endif
  #if (IRQ_SENT7_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_SENT7.U,  IRQ_CLEAR_MASK , \
                     (IRQ_SENT_SR7_TOS | IRQ_SENT_SR7_PRIO));
  #endif
  #if (IRQ_SENT8_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_SENT8.U,  IRQ_CLEAR_MASK , \
                     (IRQ_SENT_SR8_TOS | IRQ_SENT_SR8_PRIO));
  #endif
  #if (IRQ_SENT9_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_SENT9.U,  IRQ_CLEAR_MASK , \
                     (IRQ_SENT_SR9_TOS | IRQ_SENT_SR9_PRIO));
  #endif
  #if (IRQ_SENT10_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_SENT10.U,  IRQ_CLEAR_MASK , \
                     (IRQ_SENT_SR10_TOS | IRQ_SENT_SR10_PRIO));
  #endif
  #if (IRQ_SENT11_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_SENT11.U,  IRQ_CLEAR_MASK , \
                     (IRQ_SENT_SR11_TOS | IRQ_SENT_SR11_PRIO));
  #endif
  #if (IRQ_SENT12_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_SENT12.U,  IRQ_CLEAR_MASK , \
                     (IRQ_SENT_SR12_TOS | IRQ_SENT_SR12_PRIO));
  #endif
  #if (IRQ_SENT13_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_SENT13.U,  IRQ_CLEAR_MASK , \
                     (IRQ_SENT_SR13_TOS | IRQ_SENT_SR13_PRIO));
  #endif
  #if (IRQ_SENT14_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_SENT14.U,  IRQ_CLEAR_MASK , \
                     (IRQ_SENT_SR14_TOS | IRQ_SENT_SR14_PRIO));
  #endif

  #endif
}

/*******************************************************************************
** Syntax :  void IrqI2c_Init(void)                                           **
**                                                                            **
** Service ID:  none                                                          **
**                                                                            **
** Sync/Async:  Synchronous                                                   **
**                                                                            **
** Reentrancy:  non reentrant                                                 **
**                                                                            **
** Parameters (in): none                                                      **
**                                                                            **
** Parameters (out): none                                                     **
**                                                                            **
** Return value: none                                                         **
**                                                                            **
** Description : To set the interrupt priority for                            **
**               service nodes according to priority configurartion.          **
**                                                                            **
*******************************************************************************/

void IrqI2c_Init(void)
{

  #if (IRQ_I2C_EXIST == STD_ON)

  #if (IRQ_I2C0_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_I2C0BREQ.U,  IRQ_CLEAR_MASK , \
                     (IRQ_I2C0_BREQ_TOS | IRQ_I2C0_BREQ_PRIO));
  IRQ_SFR_MODIFY32 (SRC_I2C0LBREQ.U,  IRQ_CLEAR_MASK , \
                     (IRQ_I2C0_LBREQ_TOS | IRQ_I2C0_LBREQ_PRIO));
  IRQ_SFR_MODIFY32 (SRC_I2C0SREQ.U,  IRQ_CLEAR_MASK , \
                     (IRQ_I2C0_SREQ_TOS | IRQ_I2C0_SREQ_PRIO));
  IRQ_SFR_MODIFY32 (SRC_I2C0LSREQ.U,  IRQ_CLEAR_MASK , \
                     (IRQ_I2C0_LSREQ_TOS | IRQ_I2C0_LSREQ_PRIO));
  IRQ_SFR_MODIFY32 (SRC_I2C0ERR.U ,  IRQ_CLEAR_MASK , \
                     (IRQ_I2C0_ERR_TOS | IRQ_I2C0_ERR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_I2C0P.U   ,  IRQ_CLEAR_MASK , \
                     (IRQ_I2C0_P_TOS | IRQ_I2C0_P_PRIO));

  #endif/* End for IRQ_I2C0_EXIST == STD_ON*/

  #if (IRQ_I2C1_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_I2C1BREQ.U,  IRQ_CLEAR_MASK , \
                     (IRQ_I2C1_BREQ_TOS | IRQ_I2C1_BREQ_PRIO));
  IRQ_SFR_MODIFY32 (SRC_I2C1LBREQ.U,  IRQ_CLEAR_MASK , \
                     (IRQ_I2C1_LBREQ_TOS | IRQ_I2C1_LBREQ_PRIO));
  IRQ_SFR_MODIFY32 (SRC_I2C1SREQ.U,  IRQ_CLEAR_MASK , \
                     (IRQ_I2C1_SREQ_TOS | IRQ_I2C1_SREQ_PRIO));
  IRQ_SFR_MODIFY32 (SRC_I2C1LSREQ.U,  IRQ_CLEAR_MASK , \
                     (IRQ_I2C1_LSREQ_TOS | IRQ_I2C1_LSREQ_PRIO));
  IRQ_SFR_MODIFY32 (SRC_I2C1ERR.U ,  IRQ_CLEAR_MASK , \
                     (IRQ_I2C1_ERR_TOS | IRQ_I2C1_ERR_PRIO));
  IRQ_SFR_MODIFY32 (SRC_I2C1P.U   ,  IRQ_CLEAR_MASK , \
                     (IRQ_I2C1_P_TOS | IRQ_I2C1_P_PRIO));

  #endif/* End for IRQ_I2C1_EXIST == STD_ON*/

  #endif /*End for IRQ_I2C_EXIST == STD_ON*/
}

/*******************************************************************************
** Syntax :  void IrqHssl_Init(void)                                          **
**                                                                            **
** Service ID:  none                                                          **
**                                                                            **
** Sync/Async:  Synchronous                                                   **
**                                                                            **
** Reentrancy:  non reentrant                                                 **
**                                                                            **
** Parameters (in): none                                                      **
**                                                                            **
** Parameters (out): none                                                     **
**                                                                            **
** Return value: none                                                         **
**                                                                            **
** Description : To set the interrupt priority for various                    **
**               service nodes according to priority configurartion.          **
**                                                                            **
*******************************************************************************/

void IrqHssl_Init(void)
{
  #if (IRQ_HSSL_EXIST == STD_ON)

  #if (IRQ_HSSL0_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_HSSLCOK0.U   ,  IRQ_CLEAR_MASK , \
                     (IRQ_HSSL0_COK_TOS | IRQ_HSSL0_COK_PRIO));
  IRQ_SFR_MODIFY32 (SRC_HSSLRDI0.U   ,  IRQ_CLEAR_MASK , \
                     (IRQ_HSSL0_RDI_TOS | IRQ_HSSL0_RDI_PRIO));
  IRQ_SFR_MODIFY32 (SRC_HSSLTRG0.U   ,  IRQ_CLEAR_MASK , \
                     (IRQ_HSSL0_TRG_TOS | IRQ_HSSL0_TRG_PRIO));
  IRQ_SFR_MODIFY32 (SRC_HSSLERR0.U   ,  IRQ_CLEAR_MASK , \
                     (IRQ_HSSL0_ERR_TOS | IRQ_HSSL0_ERR_PRIO));
  #endif

  #if (IRQ_HSSL1_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_HSSLCOK1.U   ,  IRQ_CLEAR_MASK , \
                     (IRQ_HSSL1_COK_TOS | IRQ_HSSL1_COK_PRIO));
  IRQ_SFR_MODIFY32 (SRC_HSSLRDI1.U   ,  IRQ_CLEAR_MASK , \
                     (IRQ_HSSL1_RDI_TOS | IRQ_HSSL1_RDI_PRIO));
  IRQ_SFR_MODIFY32 (SRC_HSSLTRG1.U   ,  IRQ_CLEAR_MASK , \
                     (IRQ_HSSL1_TRG_TOS | IRQ_HSSL1_TRG_PRIO));
  IRQ_SFR_MODIFY32 (SRC_HSSLERR1.U   ,  IRQ_CLEAR_MASK , \
                     (IRQ_HSSL1_ERR_TOS | IRQ_HSSL1_ERR_PRIO));
  #endif

  #if (IRQ_HSSL2_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_HSSLCOK2.U   ,  IRQ_CLEAR_MASK , \
                     (IRQ_HSSL2_COK_TOS | IRQ_HSSL2_COK_PRIO));
  IRQ_SFR_MODIFY32 (SRC_HSSLRDI2.U   ,  IRQ_CLEAR_MASK , \
                     (IRQ_HSSL2_RDI_TOS | IRQ_HSSL2_RDI_PRIO));
  IRQ_SFR_MODIFY32 (SRC_HSSLTRG2.U   ,  IRQ_CLEAR_MASK , \
                     (IRQ_HSSL2_TRG_TOS | IRQ_HSSL2_TRG_PRIO));
  IRQ_SFR_MODIFY32 (SRC_HSSLERR2.U   ,  IRQ_CLEAR_MASK , \
                     (IRQ_HSSL2_ERR_TOS | IRQ_HSSL2_ERR_PRIO));
  #endif

  #if (IRQ_HSSL3_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_HSSLCOK3.U   ,  IRQ_CLEAR_MASK , \
                     (IRQ_HSSL3_COK_TOS | IRQ_HSSL3_COK_PRIO));
  IRQ_SFR_MODIFY32 (SRC_HSSLRDI3.U   ,  IRQ_CLEAR_MASK , \
                     (IRQ_HSSL3_RDI_TOS | IRQ_HSSL3_RDI_PRIO));
  IRQ_SFR_MODIFY32 (SRC_HSSLTRG3.U   ,  IRQ_CLEAR_MASK , \
                     (IRQ_HSSL3_TRG_TOS | IRQ_HSSL3_TRG_PRIO));
  IRQ_SFR_MODIFY32 (SRC_HSSLERR3.U   ,  IRQ_CLEAR_MASK , \
                     (IRQ_HSSL3_ERR_TOS | IRQ_HSSL3_ERR_PRIO));
  #endif

  #if (IRQ_HSSL_EXI_SRN_EXIST == STD_ON)
  IRQ_SFR_MODIFY32 (SRC_HSSLEXI.U    ,  IRQ_CLEAR_MASK , \
                     (IRQ_HSSL_EXI_TOS | IRQ_HSSL_EXI_PRIO));
  #endif

  #endif
}

/*******************************************************************************
** Syntax :  void Irq_ClearAllInterruptFlags(void)                            **
**                                                                            **
** Service ID:  none                                                          **
**                                                                            **
** Sync/Async:  Synchronous                                                   **
**                                                                            **
** Reentrancy:  non reentrant                                                 **
**                                                                            **
** Parameters (in): none                                                      **
**                                                                            **
** Parameters (out): none                                                     **
**                                                                            **
** Return value: none                                                         **
**                                                                            **
** Description : To clear all SRR and corresponding SRE bits.This ensures     **
** Standby mode can be entered if no pending interrupts are available.        **
**                                                                            **
*******************************************************************************/
void Irq_ClearAllInterruptFlags(void)
{
  Mcal_DisableAllInterrupts();
  
  #if (IRQ_ASCLIN_EXIST == STD_ON)
  Irq_ClearAsclinIntFlags();
  #endif

  #if (IRQ_CCU6_EXIST == STD_ON)
  Irq_ClearCcu6IntFlags();
  #endif

  #if (IRQ_GPT_EXIST == STD_ON)
  Irq_ClearGptIntFlags();
  #endif

  #if (IRQ_GTM_EXIST == STD_ON)
  Irq_ClearGtmIntFlags();
  #endif

  #if (IRQ_CAN_EXIST == STD_ON)
  Irq_ClearCanIntFlags();
  #endif

  #if ((IRQ_HSM0_EXIST == STD_ON) || (IRQ_HSM1_EXIST == STD_ON))
  Irq_ClearHsmIntFlags();
  #endif

  #if (IRQ_GPSRGROUP_EXIST == STD_ON)
  Irq_ClearGpsrGroupIntFlags();
  #endif
  
  #if (IRQ_QSPI_EXIST == STD_ON)
  Irq_ClearSpiIntFlags();
  #endif

  #if (IRQ_ADC_EXIST == STD_ON)
  Irq_ClearAdcIntFlags();
  #endif

  #if (IRQ_DSADC_EXIST == STD_ON)
  Irq_ClearDsadcIntFlags();
  #endif

  #if (IRQ_MSC_EXIST == STD_ON)
  Irq_ClearMscIntFlags();
  #endif

  #if (IRQ_FLEXRAY_EXIST == STD_ON)
  Irq_ClearFlexrayIntFlags();
  #endif

  #if (IRQ_ETH_EXIST == STD_ON)
  Irq_ClearEthernetIntFlags();
  #endif

  #if (IRQ_DMA_EXIST == STD_ON)
  Irq_ClearDmaIntFlags();
  #endif

  #if (IRQ_STM_EXIST == STD_ON)
  Irq_ClearStmIntFlags();
  #endif
  
  #if (IRQ_SCU_EXIST == STD_ON)
  Irq_ClearScuIntFlags();
  #endif

  #if (IRQ_PMU0_EXIST == STD_ON)
  Irq_ClearPmuIntFlags();
  #endif

  #if (IRQ_SENT_EXIST == STD_ON)
  Irq_ClearSentIntFlags();
  #endif

  #if (IRQ_I2C_EXIST == STD_ON)
  Irq_ClearI2cIntFlags();
  #endif

  #if (IRQ_HSSL_EXIST == STD_ON)
  Irq_ClearHsslIntFlags();
  #endif

}
#endif /* (IFX_MCAL_USED == STD_ON) */

#if (IFX_MCAL_USED == STD_ON)
#define IRQ_STOP_SEC_CODE
#include "MemMap.h"
#else
#define IFX_IRQ_STOP_SEC_CODE_ASIL_B
#include "Ifx_MemMap.h"
#endif


