/** @file     Rte_Memory_SWC.h
  *
  * @brief    Application header file
  *
  * @note     AUTOMATICALLY GENERATED FILE! DO NOT EDIT!
  *
  * @note     Generated by ETAS RTA-RTE
  * @note     Version 6.5.0 
  *
  * @date     Thu Mar  7 11:39:19 2019
  */

#ifndef RTE_MEMORY_SWC_H
#define RTE_MEMORY_SWC_H

#ifndef RTE_CORE
#ifdef RTE_APPLICATION_HEADER_FILE
#error Multiple application header files included.
#endif /* RTE_APPLICATION_HEADER_FILE */
#define RTE_APPLICATION_HEADER_FILE
#endif /* RTE_CORE */

/*******************************************************
 ***
 *** Includes
 ***
 *******************************************************/

#include "Rte.h"
#include "Rte_Intl.h"
#include "Rte_Memory_SWC_Type.h"

#include "Rte_DataHandleType.h"

#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */

#if defined(RTE_RUNNABLEAPI_RE_Memory_SWC)
   /* Do nothing for this and all elif clauses below (rte_sws_2751) */
#else
   /* None of above defined so define value including all APIs (rte_sws_2751) */
   #define RTE_PRV_ALL_API
#endif

/*******************************************************
 ***
 *** Constants
 ***
 *******************************************************/

#ifndef RTE_CORE
#define RTE_E_NvMService_E_NOT_OK ((Std_ReturnType)1)
#endif /* RTE_CORE */

/*******************************************************
 ***
 *** Public Types
 ***
 *******************************************************/

/* BEGIN: SWC types (core visible) */
struct Rte_CDS_Memory_SWC {
   /* Data handles */
   P2VAR(Rte_DE_uint8                       , AUTOMATIC, RTE_DATA) RE_Memory_SWC_RPort_TST_DiagMeM_test_TST_DiagMeM_test;
   P2VAR(Rte_DE_uint8                       , AUTOMATIC, RTE_DATA) RE_Memory_SWC_RPort_TST_PIM_FirstByte_TST_PIM_FirstByte;
   P2VAR(Rte_DE_uint8                       , AUTOMATIC, RTE_DATA) RE_Memory_SWC_RPort_TST_PIM_LastByte_TST_PIM_LastByte;
   /* Per-Instance Memorys (sic) */
   P2VAR(Rte_PimType_Memory_SWC_PIM_Swc_Type, AUTOMATIC, RTE_DATA) Pim_PIM_SWC_01;
   P2VAR(Rte_PimType_Memory_SWC_PIM_Swc_Type, AUTOMATIC, RTE_DATA) Pim_PIM_SWC_02;
   P2VAR(Rte_PimType_Memory_SWC_PIM_Swc_Type, AUTOMATIC, RTE_DATA) Pim_PIM_SWC_03;
};
typedef struct Rte_CDS_Memory_SWC Rte_CDS_Memory_SWC;
/* END: SWC types (core visible) */

/*******************************************************
 ***
 *** Private Types
 ***
 *******************************************************/

/* BEGIN: SWC types (private) */
#ifndef RTE_CORE
typedef Rte_PimType_Memory_SWC_PIM_Swc_Type PIM_Swc_Type;
#endif /* RTE_CORE */

/* END: SWC types (private) */

/*******************************************************
 ***
 *** Instance Declarations
 ***
 *******************************************************/

#define RTE_START_SEC_CONST_UNSPECIFIED
#include "Rte_MemMap.h" /*lint !e537 permit multiple inclusion */
extern CONST(struct Rte_CDS_Memory_SWC, RTE_CONST) Rte_Inst_Memory_SWC;
#define RTE_STOP_SEC_CONST_UNSPECIFIED
#include "Rte_MemMap.h" /*lint !e537 permit multiple inclusion */


#ifndef RTE_CORE
typedef CONSTP2CONST(struct Rte_CDS_Memory_SWC, AUTOMATIC, RTE_CONST) Rte_Instance;
#endif /* RTE_CORE */

/*******************************************************
 ***
 *** API Mapping macros
 ***
 *******************************************************/

/* API Mapping Macros */
#ifndef RTE_CORE

#define NvM_START_SEC_CODE
#include "NvM_MemMap.h" /*lint !e537 permit multiple inclusion */
FUNC(Std_ReturnType, NvM_CODE) NvM_ReadBlock(VAR(NvM_BlockIdType, AUTOMATIC) Rte_PDAV0,
                                             VAR(NvM_Rb_VoidPtr, AUTOMATIC) DstPtr);

FUNC(Std_ReturnType, NvM_CODE) NvM_SetRamBlockStatus(VAR(NvM_BlockIdType, AUTOMATIC) Rte_PDAV0,
                                                     VAR(boolean, AUTOMATIC) BlockChanged);

FUNC(Std_ReturnType, NvM_CODE) NvM_WriteBlock(VAR(NvM_BlockIdType, AUTOMATIC) Rte_PDAV0,
                                              VAR(NvM_Rb_ConstVoidPtr, AUTOMATIC) SrcPtr);

#define NvM_STOP_SEC_CODE
#include "NvM_MemMap.h" /*lint !e537 permit multiple inclusion */
#define RTE_START_SEC_CODE
#include "Rte_MemMap.h" /*lint !e537 permit multiple inclusion */
FUNC(Std_ReturnType, RTE_CODE) Rte_Write_Memory_SWC_PPort_Pim1_First_Pim1_First(VAR(uint8, AUTOMATIC) data);
FUNC(Std_ReturnType, RTE_CODE) Rte_Write_Memory_SWC_PPort_Pim1_Last_Pim1_Last(VAR(uint8, AUTOMATIC) data);
FUNC(Std_ReturnType, RTE_CODE) Rte_Write_Memory_SWC_PPort_Pim2_First_Pim2_First(VAR(uint8, AUTOMATIC) data);
FUNC(Std_ReturnType, RTE_CODE) Rte_Write_Memory_SWC_PPort_Pim2_Last_Pim2_Last(VAR(uint8, AUTOMATIC) data);
FUNC(Std_ReturnType, RTE_CODE) Rte_Write_Memory_SWC_PPort_Pim3_First_Pim3_First(VAR(uint8, AUTOMATIC) data);
FUNC(Std_ReturnType, RTE_CODE) Rte_Write_Memory_SWC_PPort_Pim3_Last_Pim3_Last(VAR(uint8, AUTOMATIC) data);
#define RTE_STOP_SEC_CODE
#include "Rte_MemMap.h" /*lint !e537 permit multiple inclusion */
#define RTE_START_SEC_CONST_UNSPECIFIED
#include "Rte_MemMap.h" /*lint !e537 permit multiple inclusion */
extern CONST(Rte_SelfType_NvM, RTE_CONST) Rte_Self_CPT_NvM;
#define RTE_STOP_SEC_CONST_UNSPECIFIED
#include "Rte_MemMap.h" /*lint !e537 permit multiple inclusion */
#define RTE_START_SEC_VAR_CLEARED_UNSPECIFIED
#include "Rte_MemMap.h" /*lint !e537 permit multiple inclusion */
extern VAR(Rte_PimType_Memory_SWC_PIM_Swc_Type, RTE_APPL_DATA) Rte_CPim_Memory_SWC_PIM_SWC_01;
#define RTE_STOP_SEC_VAR_CLEARED_UNSPECIFIED
#include "Rte_MemMap.h" /*lint !e537 permit multiple inclusion */
#define RTE_START_SEC_VAR_CLEARED_UNSPECIFIED
#include "Rte_MemMap.h" /*lint !e537 permit multiple inclusion */
extern VAR(Rte_PimType_Memory_SWC_PIM_Swc_Type, RTE_APPL_DATA) Rte_CPim_Memory_SWC_PIM_SWC_02;
#define RTE_STOP_SEC_VAR_CLEARED_UNSPECIFIED
#include "Rte_MemMap.h" /*lint !e537 permit multiple inclusion */
#define RTE_START_SEC_VAR_CLEARED_UNSPECIFIED
#include "Rte_MemMap.h" /*lint !e537 permit multiple inclusion */
extern VAR(Rte_PimType_Memory_SWC_PIM_Swc_Type, RTE_APPL_DATA) Rte_CPim_Memory_SWC_PIM_SWC_03;
#define RTE_STOP_SEC_VAR_CLEARED_UNSPECIFIED
#include "Rte_MemMap.h" /*lint !e537 permit multiple inclusion */
#define RTE_START_SEC_VAR_CLEARED_32
#include "Rte_MemMap.h" /*lint !e537 permit multiple inclusion */
extern VAR(Rte_ImplicitBufsType, RTE_DATA) Rte_ImplicitBufs;
#define RTE_STOP_SEC_VAR_CLEARED_32
#include "Rte_MemMap.h" /*lint !e537 permit multiple inclusion */
#define RTE_START_SEC_VAR_CLEARED_8
#include "Rte_MemMap.h" /*lint !e537 permit multiple inclusion */
extern VAR(uint8, RTE_DATA) Rte_Rx_000027;
#define RTE_STOP_SEC_VAR_CLEARED_8
#include "Rte_MemMap.h" /*lint !e537 permit multiple inclusion */
#if defined(RTE_PRV_ALL_API) || defined(RTE_RUNNABLEAPI_RE_Memory_SWC)
/* Inline function call optimization; Rte_Call_RPort_NvM_NativeBlock_2_ReadBlock to NvM_ReadBlock */
#define Rte_Call_RPort_NvM_NativeBlock_2_ReadBlock( DstPtr ) NvM_ReadBlock(((VAR(NvM_BlockIdType, AUTOMATIC))11), DstPtr)

#endif
#if defined(RTE_PRV_ALL_API) || defined(RTE_RUNNABLEAPI_RE_Memory_SWC)
/* Inline function call optimization; Rte_Call_RPort_NvM_NativeBlock_2_SetRamBlockStatus to NvM_SetRamBlockStatus */
#define Rte_Call_RPort_NvM_NativeBlock_2_SetRamBlockStatus( BlockChanged ) NvM_SetRamBlockStatus(((VAR(NvM_BlockIdType, AUTOMATIC))11), BlockChanged)

#endif
#if defined(RTE_PRV_ALL_API) || defined(RTE_RUNNABLEAPI_RE_Memory_SWC)
/* Inline function call optimization; Rte_Call_RPort_NvM_NativeBlock_2_WriteBlock to NvM_WriteBlock */
#define Rte_Call_RPort_NvM_NativeBlock_2_WriteBlock( SrcPtr ) NvM_WriteBlock(((VAR(NvM_BlockIdType, AUTOMATIC))11), SrcPtr)

#endif
#if defined(RTE_PRV_ALL_API) || defined(RTE_RUNNABLEAPI_RE_Memory_SWC)
/* Inline function call optimization; Rte_Call_RPort_NvM_NativeBlock_3_ReadBlock to NvM_ReadBlock */
#define Rte_Call_RPort_NvM_NativeBlock_3_ReadBlock( DstPtr ) NvM_ReadBlock(((VAR(NvM_BlockIdType, AUTOMATIC))12), DstPtr)

#endif
#if defined(RTE_PRV_ALL_API) || defined(RTE_RUNNABLEAPI_RE_Memory_SWC)
/* Inline function call optimization; Rte_Call_RPort_NvM_NativeBlock_3_SetRamBlockStatus to NvM_SetRamBlockStatus */
#define Rte_Call_RPort_NvM_NativeBlock_3_SetRamBlockStatus( BlockChanged ) NvM_SetRamBlockStatus(((VAR(NvM_BlockIdType, AUTOMATIC))12), BlockChanged)

#endif
#if defined(RTE_PRV_ALL_API) || defined(RTE_RUNNABLEAPI_RE_Memory_SWC)
/* Inline function call optimization; Rte_Call_RPort_NvM_NativeBlock_3_WriteBlock to NvM_WriteBlock */
#define Rte_Call_RPort_NvM_NativeBlock_3_WriteBlock( SrcPtr ) NvM_WriteBlock(((VAR(NvM_BlockIdType, AUTOMATIC))12), SrcPtr)

#endif
#if defined(RTE_PRV_ALL_API) || defined(RTE_RUNNABLEAPI_RE_Memory_SWC)
/* Inline function call optimization; Rte_Call_RPort_NvM_NativeBlock_4_ReadBlock to NvM_ReadBlock */
#define Rte_Call_RPort_NvM_NativeBlock_4_ReadBlock( DstPtr ) NvM_ReadBlock(((VAR(NvM_BlockIdType, AUTOMATIC))13), DstPtr)

#endif
#if defined(RTE_PRV_ALL_API) || defined(RTE_RUNNABLEAPI_RE_Memory_SWC)
/* Inline function call optimization; Rte_Call_RPort_NvM_NativeBlock_4_SetRamBlockStatus to NvM_SetRamBlockStatus */
#define Rte_Call_RPort_NvM_NativeBlock_4_SetRamBlockStatus( BlockChanged ) NvM_SetRamBlockStatus(((VAR(NvM_BlockIdType, AUTOMATIC))13), BlockChanged)

#endif
#if defined(RTE_PRV_ALL_API) || defined(RTE_RUNNABLEAPI_RE_Memory_SWC)
/* Inline function call optimization; Rte_Call_RPort_NvM_NativeBlock_4_WriteBlock to NvM_WriteBlock */
#define Rte_Call_RPort_NvM_NativeBlock_4_WriteBlock( SrcPtr ) NvM_WriteBlock(((VAR(NvM_BlockIdType, AUTOMATIC))13), SrcPtr)

#endif
#if defined(RTE_PRV_ALL_API) || defined(RTE_RUNNABLEAPI_RE_Memory_SWC)
/* Inline read optimization; Rte_IRead_RE_Memory_SWC_RPort_TST_DiagMeM_test_TST_DiagMeM_test to implicit access macro */
#define Rte_IRead_RE_Memory_SWC_RPort_TST_DiagMeM_test_TST_DiagMeM_test()  ( (CONST(uint8, RTE_DATA)) Rte_ImplicitBufs.isa_15.Rte_OsTask_ASW.rbuf2.value )
#endif
#if defined(RTE_PRV_ALL_API) || defined(RTE_RUNNABLEAPI_RE_Memory_SWC)
/* Inline read optimization; Rte_IRead_RE_Memory_SWC_RPort_TST_PIM_FirstByte_TST_PIM_FirstByte to implicit access macro */
#define Rte_IRead_RE_Memory_SWC_RPort_TST_PIM_FirstByte_TST_PIM_FirstByte()  ( (CONST(uint8, RTE_DATA)) Rte_ImplicitBufs.isa_15.Rte_OsTask_ASW.rbuf1.value )
#endif
#if defined(RTE_PRV_ALL_API) || defined(RTE_RUNNABLEAPI_RE_Memory_SWC)
/* Inline read optimization; Rte_IRead_RE_Memory_SWC_RPort_TST_PIM_LastByte_TST_PIM_LastByte to implicit access macro */
#define Rte_IRead_RE_Memory_SWC_RPort_TST_PIM_LastByte_TST_PIM_LastByte()  ( (CONST(uint8, RTE_DATA)) Rte_ImplicitBufs.isa_15.Rte_OsTask_ASW.rbuf0.value )
#endif
/* Inline read optimization; Rte_Pim_PIM_SWC_01 to direct read */
#define Rte_Pim_PIM_SWC_01()  ( (P2VAR(PIM_Swc_Type, AUTOMATIC, RTE_APPL_DATA)) &Rte_CPim_Memory_SWC_PIM_SWC_01 )
/* Inline read optimization; Rte_Pim_PIM_SWC_02 to direct read */
#define Rte_Pim_PIM_SWC_02()  ( (P2VAR(PIM_Swc_Type, AUTOMATIC, RTE_APPL_DATA)) &Rte_CPim_Memory_SWC_PIM_SWC_02 )
/* Inline read optimization; Rte_Pim_PIM_SWC_03 to direct read */
#define Rte_Pim_PIM_SWC_03()  ( (P2VAR(PIM_Swc_Type, AUTOMATIC, RTE_APPL_DATA)) &Rte_CPim_Memory_SWC_PIM_SWC_03 )
#if defined(RTE_PRV_ALL_API) || defined(RTE_RUNNABLEAPI_RE_Memory_SWC)
#define Rte_Write_PPort_Pim1_First_Pim1_First( data ) (Rte_Write_Memory_SWC_PPort_Pim1_First_Pim1_First(data))
#endif
#if defined(RTE_PRV_ALL_API) || defined(RTE_RUNNABLEAPI_RE_Memory_SWC)
#define Rte_Write_PPort_Pim1_Last_Pim1_Last( data ) (Rte_Write_Memory_SWC_PPort_Pim1_Last_Pim1_Last(data))
#endif
#if defined(RTE_PRV_ALL_API) || defined(RTE_RUNNABLEAPI_RE_Memory_SWC)
#define Rte_Write_PPort_Pim2_First_Pim2_First( data ) (Rte_Write_Memory_SWC_PPort_Pim2_First_Pim2_First(data))
#endif
#if defined(RTE_PRV_ALL_API) || defined(RTE_RUNNABLEAPI_RE_Memory_SWC)
#define Rte_Write_PPort_Pim2_Last_Pim2_Last( data ) (Rte_Write_Memory_SWC_PPort_Pim2_Last_Pim2_Last(data))
#endif
#if defined(RTE_PRV_ALL_API) || defined(RTE_RUNNABLEAPI_RE_Memory_SWC)
#define Rte_Write_PPort_Pim3_First_Pim3_First( data ) (Rte_Write_Memory_SWC_PPort_Pim3_First_Pim3_First(data))
#endif
#if defined(RTE_PRV_ALL_API) || defined(RTE_RUNNABLEAPI_RE_Memory_SWC)
#define Rte_Write_PPort_Pim3_Last_Pim3_Last( data ) (Rte_Write_Memory_SWC_PPort_Pim3_Last_Pim3_Last(data))
#endif
#if defined(RTE_PRV_ALL_API) || defined(RTE_RUNNABLEAPI_RE_Memory_SWC)
/* Inline Write optimization; Rte_Write_PPort_TST_Diag_TestNumber_uint8_Impl to direct write */
#define Rte_Write_PPort_TST_Diag_TestNumber_uint8_Impl( data ) ( (Rte_Rx_000027 = data), RTE_E_OK )
#endif

#endif /* RTE_CORE */

/*******************************************************
 ***
 *** RE Prototypes
 ***
 *******************************************************/

#define Memory_SWC_START_SEC_CODE
#include "Memory_SWC_MemMap.h" /*lint !e537 permit multiple inclusion */
FUNC(void, Memory_SWC_CODE) RE_Memory_SWC(void);
#define Memory_SWC_STOP_SEC_CODE
#include "Memory_SWC_MemMap.h" /*lint !e537 permit multiple inclusion */

/* Initial values for data element prototypes */

#ifdef __cplusplus
} /* extern C */
#endif /* __cplusplus */

#endif /* !RTE_MEMORY_SWC_H */
