/**
 * \file IfxGtm_bf.h
 * \brief
 * \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
 *
 * Version: TC26XB_UM_V1.2.R1
 * Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
 * MAY BE CHANGED BY USER [yes/no]: No
 *
 *                                 IMPORTANT NOTICE
 *
 * Infineon Technologies AG (Infineon) is supplying this file for use
 * exclusively with Infineon's microcontroller products. This file can be freely
 * distributed within development tools that are supporting such microcontroller
 * products.
 *
 * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
 * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
 * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
 *
 * \defgroup IfxLld_Gtm_BitfieldsMask Bitfields mask and offset
 * \ingroup IfxLld_Gtm
 * 
 */
#ifndef IFXGTM_BF_H
#define IFXGTM_BF_H 1
/******************************************************************************/
/******************************************************************************/
/** \addtogroup IfxLld_Gtm_BitfieldsMask
 * \{  */

/** \brief  Length for Ifx_GTM_ACCEN0_Bits.EN0 */
#define IFX_GTM_ACCEN0_EN0_LEN (1u)

/** \brief  Mask for Ifx_GTM_ACCEN0_Bits.EN0 */
#define IFX_GTM_ACCEN0_EN0_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ACCEN0_Bits.EN0 */
#define IFX_GTM_ACCEN0_EN0_OFF (0u)

/** \brief  Length for Ifx_GTM_ACCEN0_Bits.EN10 */
#define IFX_GTM_ACCEN0_EN10_LEN (1u)

/** \brief  Mask for Ifx_GTM_ACCEN0_Bits.EN10 */
#define IFX_GTM_ACCEN0_EN10_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ACCEN0_Bits.EN10 */
#define IFX_GTM_ACCEN0_EN10_OFF (10u)

/** \brief  Length for Ifx_GTM_ACCEN0_Bits.EN11 */
#define IFX_GTM_ACCEN0_EN11_LEN (1u)

/** \brief  Mask for Ifx_GTM_ACCEN0_Bits.EN11 */
#define IFX_GTM_ACCEN0_EN11_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ACCEN0_Bits.EN11 */
#define IFX_GTM_ACCEN0_EN11_OFF (11u)

/** \brief  Length for Ifx_GTM_ACCEN0_Bits.EN12 */
#define IFX_GTM_ACCEN0_EN12_LEN (1u)

/** \brief  Mask for Ifx_GTM_ACCEN0_Bits.EN12 */
#define IFX_GTM_ACCEN0_EN12_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ACCEN0_Bits.EN12 */
#define IFX_GTM_ACCEN0_EN12_OFF (12u)

/** \brief  Length for Ifx_GTM_ACCEN0_Bits.EN13 */
#define IFX_GTM_ACCEN0_EN13_LEN (1u)

/** \brief  Mask for Ifx_GTM_ACCEN0_Bits.EN13 */
#define IFX_GTM_ACCEN0_EN13_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ACCEN0_Bits.EN13 */
#define IFX_GTM_ACCEN0_EN13_OFF (13u)

/** \brief  Length for Ifx_GTM_ACCEN0_Bits.EN14 */
#define IFX_GTM_ACCEN0_EN14_LEN (1u)

/** \brief  Mask for Ifx_GTM_ACCEN0_Bits.EN14 */
#define IFX_GTM_ACCEN0_EN14_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ACCEN0_Bits.EN14 */
#define IFX_GTM_ACCEN0_EN14_OFF (14u)

/** \brief  Length for Ifx_GTM_ACCEN0_Bits.EN15 */
#define IFX_GTM_ACCEN0_EN15_LEN (1u)

/** \brief  Mask for Ifx_GTM_ACCEN0_Bits.EN15 */
#define IFX_GTM_ACCEN0_EN15_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ACCEN0_Bits.EN15 */
#define IFX_GTM_ACCEN0_EN15_OFF (15u)

/** \brief  Length for Ifx_GTM_ACCEN0_Bits.EN16 */
#define IFX_GTM_ACCEN0_EN16_LEN (1u)

/** \brief  Mask for Ifx_GTM_ACCEN0_Bits.EN16 */
#define IFX_GTM_ACCEN0_EN16_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ACCEN0_Bits.EN16 */
#define IFX_GTM_ACCEN0_EN16_OFF (16u)

/** \brief  Length for Ifx_GTM_ACCEN0_Bits.EN17 */
#define IFX_GTM_ACCEN0_EN17_LEN (1u)

/** \brief  Mask for Ifx_GTM_ACCEN0_Bits.EN17 */
#define IFX_GTM_ACCEN0_EN17_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ACCEN0_Bits.EN17 */
#define IFX_GTM_ACCEN0_EN17_OFF (17u)

/** \brief  Length for Ifx_GTM_ACCEN0_Bits.EN18 */
#define IFX_GTM_ACCEN0_EN18_LEN (1u)

/** \brief  Mask for Ifx_GTM_ACCEN0_Bits.EN18 */
#define IFX_GTM_ACCEN0_EN18_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ACCEN0_Bits.EN18 */
#define IFX_GTM_ACCEN0_EN18_OFF (18u)

/** \brief  Length for Ifx_GTM_ACCEN0_Bits.EN19 */
#define IFX_GTM_ACCEN0_EN19_LEN (1u)

/** \brief  Mask for Ifx_GTM_ACCEN0_Bits.EN19 */
#define IFX_GTM_ACCEN0_EN19_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ACCEN0_Bits.EN19 */
#define IFX_GTM_ACCEN0_EN19_OFF (19u)

/** \brief  Length for Ifx_GTM_ACCEN0_Bits.EN1 */
#define IFX_GTM_ACCEN0_EN1_LEN (1u)

/** \brief  Mask for Ifx_GTM_ACCEN0_Bits.EN1 */
#define IFX_GTM_ACCEN0_EN1_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ACCEN0_Bits.EN1 */
#define IFX_GTM_ACCEN0_EN1_OFF (1u)

/** \brief  Length for Ifx_GTM_ACCEN0_Bits.EN20 */
#define IFX_GTM_ACCEN0_EN20_LEN (1u)

/** \brief  Mask for Ifx_GTM_ACCEN0_Bits.EN20 */
#define IFX_GTM_ACCEN0_EN20_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ACCEN0_Bits.EN20 */
#define IFX_GTM_ACCEN0_EN20_OFF (20u)

/** \brief  Length for Ifx_GTM_ACCEN0_Bits.EN21 */
#define IFX_GTM_ACCEN0_EN21_LEN (1u)

/** \brief  Mask for Ifx_GTM_ACCEN0_Bits.EN21 */
#define IFX_GTM_ACCEN0_EN21_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ACCEN0_Bits.EN21 */
#define IFX_GTM_ACCEN0_EN21_OFF (21u)

/** \brief  Length for Ifx_GTM_ACCEN0_Bits.EN22 */
#define IFX_GTM_ACCEN0_EN22_LEN (1u)

/** \brief  Mask for Ifx_GTM_ACCEN0_Bits.EN22 */
#define IFX_GTM_ACCEN0_EN22_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ACCEN0_Bits.EN22 */
#define IFX_GTM_ACCEN0_EN22_OFF (22u)

/** \brief  Length for Ifx_GTM_ACCEN0_Bits.EN23 */
#define IFX_GTM_ACCEN0_EN23_LEN (1u)

/** \brief  Mask for Ifx_GTM_ACCEN0_Bits.EN23 */
#define IFX_GTM_ACCEN0_EN23_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ACCEN0_Bits.EN23 */
#define IFX_GTM_ACCEN0_EN23_OFF (23u)

/** \brief  Length for Ifx_GTM_ACCEN0_Bits.EN24 */
#define IFX_GTM_ACCEN0_EN24_LEN (1u)

/** \brief  Mask for Ifx_GTM_ACCEN0_Bits.EN24 */
#define IFX_GTM_ACCEN0_EN24_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ACCEN0_Bits.EN24 */
#define IFX_GTM_ACCEN0_EN24_OFF (24u)

/** \brief  Length for Ifx_GTM_ACCEN0_Bits.EN25 */
#define IFX_GTM_ACCEN0_EN25_LEN (1u)

/** \brief  Mask for Ifx_GTM_ACCEN0_Bits.EN25 */
#define IFX_GTM_ACCEN0_EN25_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ACCEN0_Bits.EN25 */
#define IFX_GTM_ACCEN0_EN25_OFF (25u)

/** \brief  Length for Ifx_GTM_ACCEN0_Bits.EN26 */
#define IFX_GTM_ACCEN0_EN26_LEN (1u)

/** \brief  Mask for Ifx_GTM_ACCEN0_Bits.EN26 */
#define IFX_GTM_ACCEN0_EN26_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ACCEN0_Bits.EN26 */
#define IFX_GTM_ACCEN0_EN26_OFF (26u)

/** \brief  Length for Ifx_GTM_ACCEN0_Bits.EN27 */
#define IFX_GTM_ACCEN0_EN27_LEN (1u)

/** \brief  Mask for Ifx_GTM_ACCEN0_Bits.EN27 */
#define IFX_GTM_ACCEN0_EN27_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ACCEN0_Bits.EN27 */
#define IFX_GTM_ACCEN0_EN27_OFF (27u)

/** \brief  Length for Ifx_GTM_ACCEN0_Bits.EN28 */
#define IFX_GTM_ACCEN0_EN28_LEN (1u)

/** \brief  Mask for Ifx_GTM_ACCEN0_Bits.EN28 */
#define IFX_GTM_ACCEN0_EN28_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ACCEN0_Bits.EN28 */
#define IFX_GTM_ACCEN0_EN28_OFF (28u)

/** \brief  Length for Ifx_GTM_ACCEN0_Bits.EN29 */
#define IFX_GTM_ACCEN0_EN29_LEN (1u)

/** \brief  Mask for Ifx_GTM_ACCEN0_Bits.EN29 */
#define IFX_GTM_ACCEN0_EN29_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ACCEN0_Bits.EN29 */
#define IFX_GTM_ACCEN0_EN29_OFF (29u)

/** \brief  Length for Ifx_GTM_ACCEN0_Bits.EN2 */
#define IFX_GTM_ACCEN0_EN2_LEN (1u)

/** \brief  Mask for Ifx_GTM_ACCEN0_Bits.EN2 */
#define IFX_GTM_ACCEN0_EN2_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ACCEN0_Bits.EN2 */
#define IFX_GTM_ACCEN0_EN2_OFF (2u)

/** \brief  Length for Ifx_GTM_ACCEN0_Bits.EN30 */
#define IFX_GTM_ACCEN0_EN30_LEN (1u)

/** \brief  Mask for Ifx_GTM_ACCEN0_Bits.EN30 */
#define IFX_GTM_ACCEN0_EN30_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ACCEN0_Bits.EN30 */
#define IFX_GTM_ACCEN0_EN30_OFF (30u)

/** \brief  Length for Ifx_GTM_ACCEN0_Bits.EN31 */
#define IFX_GTM_ACCEN0_EN31_LEN (1u)

/** \brief  Mask for Ifx_GTM_ACCEN0_Bits.EN31 */
#define IFX_GTM_ACCEN0_EN31_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ACCEN0_Bits.EN31 */
#define IFX_GTM_ACCEN0_EN31_OFF (31u)

/** \brief  Length for Ifx_GTM_ACCEN0_Bits.EN3 */
#define IFX_GTM_ACCEN0_EN3_LEN (1u)

/** \brief  Mask for Ifx_GTM_ACCEN0_Bits.EN3 */
#define IFX_GTM_ACCEN0_EN3_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ACCEN0_Bits.EN3 */
#define IFX_GTM_ACCEN0_EN3_OFF (3u)

/** \brief  Length for Ifx_GTM_ACCEN0_Bits.EN4 */
#define IFX_GTM_ACCEN0_EN4_LEN (1u)

/** \brief  Mask for Ifx_GTM_ACCEN0_Bits.EN4 */
#define IFX_GTM_ACCEN0_EN4_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ACCEN0_Bits.EN4 */
#define IFX_GTM_ACCEN0_EN4_OFF (4u)

/** \brief  Length for Ifx_GTM_ACCEN0_Bits.EN5 */
#define IFX_GTM_ACCEN0_EN5_LEN (1u)

/** \brief  Mask for Ifx_GTM_ACCEN0_Bits.EN5 */
#define IFX_GTM_ACCEN0_EN5_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ACCEN0_Bits.EN5 */
#define IFX_GTM_ACCEN0_EN5_OFF (5u)

/** \brief  Length for Ifx_GTM_ACCEN0_Bits.EN6 */
#define IFX_GTM_ACCEN0_EN6_LEN (1u)

/** \brief  Mask for Ifx_GTM_ACCEN0_Bits.EN6 */
#define IFX_GTM_ACCEN0_EN6_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ACCEN0_Bits.EN6 */
#define IFX_GTM_ACCEN0_EN6_OFF (6u)

/** \brief  Length for Ifx_GTM_ACCEN0_Bits.EN7 */
#define IFX_GTM_ACCEN0_EN7_LEN (1u)

/** \brief  Mask for Ifx_GTM_ACCEN0_Bits.EN7 */
#define IFX_GTM_ACCEN0_EN7_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ACCEN0_Bits.EN7 */
#define IFX_GTM_ACCEN0_EN7_OFF (7u)

/** \brief  Length for Ifx_GTM_ACCEN0_Bits.EN8 */
#define IFX_GTM_ACCEN0_EN8_LEN (1u)

/** \brief  Mask for Ifx_GTM_ACCEN0_Bits.EN8 */
#define IFX_GTM_ACCEN0_EN8_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ACCEN0_Bits.EN8 */
#define IFX_GTM_ACCEN0_EN8_OFF (8u)

/** \brief  Length for Ifx_GTM_ACCEN0_Bits.EN9 */
#define IFX_GTM_ACCEN0_EN9_LEN (1u)

/** \brief  Mask for Ifx_GTM_ACCEN0_Bits.EN9 */
#define IFX_GTM_ACCEN0_EN9_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ACCEN0_Bits.EN9 */
#define IFX_GTM_ACCEN0_EN9_OFF (9u)

/** \brief  Length for Ifx_GTM_ADCTRIG0OUT0_Bits.SEL0 */
#define IFX_GTM_ADCTRIG0OUT0_SEL0_LEN (4u)

/** \brief  Mask for Ifx_GTM_ADCTRIG0OUT0_Bits.SEL0 */
#define IFX_GTM_ADCTRIG0OUT0_SEL0_MSK (0xfu)

/** \brief  Offset for Ifx_GTM_ADCTRIG0OUT0_Bits.SEL0 */
#define IFX_GTM_ADCTRIG0OUT0_SEL0_OFF (0u)

/** \brief  Length for Ifx_GTM_ADCTRIG0OUT0_Bits.SEL1 */
#define IFX_GTM_ADCTRIG0OUT0_SEL1_LEN (4u)

/** \brief  Mask for Ifx_GTM_ADCTRIG0OUT0_Bits.SEL1 */
#define IFX_GTM_ADCTRIG0OUT0_SEL1_MSK (0xfu)

/** \brief  Offset for Ifx_GTM_ADCTRIG0OUT0_Bits.SEL1 */
#define IFX_GTM_ADCTRIG0OUT0_SEL1_OFF (4u)

/** \brief  Length for Ifx_GTM_ADCTRIG0OUT0_Bits.SEL2 */
#define IFX_GTM_ADCTRIG0OUT0_SEL2_LEN (4u)

/** \brief  Mask for Ifx_GTM_ADCTRIG0OUT0_Bits.SEL2 */
#define IFX_GTM_ADCTRIG0OUT0_SEL2_MSK (0xfu)

/** \brief  Offset for Ifx_GTM_ADCTRIG0OUT0_Bits.SEL2 */
#define IFX_GTM_ADCTRIG0OUT0_SEL2_OFF (8u)

/** \brief  Length for Ifx_GTM_ADCTRIG0OUT0_Bits.SEL3 */
#define IFX_GTM_ADCTRIG0OUT0_SEL3_LEN (4u)

/** \brief  Mask for Ifx_GTM_ADCTRIG0OUT0_Bits.SEL3 */
#define IFX_GTM_ADCTRIG0OUT0_SEL3_MSK (0xfu)

/** \brief  Offset for Ifx_GTM_ADCTRIG0OUT0_Bits.SEL3 */
#define IFX_GTM_ADCTRIG0OUT0_SEL3_OFF (12u)

/** \brief  Length for Ifx_GTM_ADCTRIG0OUT0_Bits.SEL4 */
#define IFX_GTM_ADCTRIG0OUT0_SEL4_LEN (4u)

/** \brief  Mask for Ifx_GTM_ADCTRIG0OUT0_Bits.SEL4 */
#define IFX_GTM_ADCTRIG0OUT0_SEL4_MSK (0xfu)

/** \brief  Offset for Ifx_GTM_ADCTRIG0OUT0_Bits.SEL4 */
#define IFX_GTM_ADCTRIG0OUT0_SEL4_OFF (16u)

/** \brief  Length for Ifx_GTM_ADCTRIG1OUT0_Bits.SEL0 */
#define IFX_GTM_ADCTRIG1OUT0_SEL0_LEN (4u)

/** \brief  Mask for Ifx_GTM_ADCTRIG1OUT0_Bits.SEL0 */
#define IFX_GTM_ADCTRIG1OUT0_SEL0_MSK (0xfu)

/** \brief  Offset for Ifx_GTM_ADCTRIG1OUT0_Bits.SEL0 */
#define IFX_GTM_ADCTRIG1OUT0_SEL0_OFF (0u)

/** \brief  Length for Ifx_GTM_ADCTRIG1OUT0_Bits.SEL1 */
#define IFX_GTM_ADCTRIG1OUT0_SEL1_LEN (4u)

/** \brief  Mask for Ifx_GTM_ADCTRIG1OUT0_Bits.SEL1 */
#define IFX_GTM_ADCTRIG1OUT0_SEL1_MSK (0xfu)

/** \brief  Offset for Ifx_GTM_ADCTRIG1OUT0_Bits.SEL1 */
#define IFX_GTM_ADCTRIG1OUT0_SEL1_OFF (4u)

/** \brief  Length for Ifx_GTM_ADCTRIG1OUT0_Bits.SEL2 */
#define IFX_GTM_ADCTRIG1OUT0_SEL2_LEN (4u)

/** \brief  Mask for Ifx_GTM_ADCTRIG1OUT0_Bits.SEL2 */
#define IFX_GTM_ADCTRIG1OUT0_SEL2_MSK (0xfu)

/** \brief  Offset for Ifx_GTM_ADCTRIG1OUT0_Bits.SEL2 */
#define IFX_GTM_ADCTRIG1OUT0_SEL2_OFF (8u)

/** \brief  Length for Ifx_GTM_ADCTRIG1OUT0_Bits.SEL3 */
#define IFX_GTM_ADCTRIG1OUT0_SEL3_LEN (4u)

/** \brief  Mask for Ifx_GTM_ADCTRIG1OUT0_Bits.SEL3 */
#define IFX_GTM_ADCTRIG1OUT0_SEL3_MSK (0xfu)

/** \brief  Offset for Ifx_GTM_ADCTRIG1OUT0_Bits.SEL3 */
#define IFX_GTM_ADCTRIG1OUT0_SEL3_OFF (12u)

/** \brief  Length for Ifx_GTM_ADCTRIG1OUT0_Bits.SEL4 */
#define IFX_GTM_ADCTRIG1OUT0_SEL4_LEN (4u)

/** \brief  Mask for Ifx_GTM_ADCTRIG1OUT0_Bits.SEL4 */
#define IFX_GTM_ADCTRIG1OUT0_SEL4_MSK (0xfu)

/** \brief  Offset for Ifx_GTM_ADCTRIG1OUT0_Bits.SEL4 */
#define IFX_GTM_ADCTRIG1OUT0_SEL4_OFF (16u)

/** \brief  Length for Ifx_GTM_AEI_ADDR_XPT_Bits.TO_ADDR */
#define IFX_GTM_AEI_ADDR_XPT_TO_ADDR_LEN (20u)

/** \brief  Mask for Ifx_GTM_AEI_ADDR_XPT_Bits.TO_ADDR */
#define IFX_GTM_AEI_ADDR_XPT_TO_ADDR_MSK (0xfffffu)

/** \brief  Offset for Ifx_GTM_AEI_ADDR_XPT_Bits.TO_ADDR */
#define IFX_GTM_AEI_ADDR_XPT_TO_ADDR_OFF (0u)

/** \brief  Length for Ifx_GTM_AEI_ADDR_XPT_Bits.TO_W1R0 */
#define IFX_GTM_AEI_ADDR_XPT_TO_W1R0_LEN (1u)

/** \brief  Mask for Ifx_GTM_AEI_ADDR_XPT_Bits.TO_W1R0 */
#define IFX_GTM_AEI_ADDR_XPT_TO_W1R0_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_AEI_ADDR_XPT_Bits.TO_W1R0 */
#define IFX_GTM_AEI_ADDR_XPT_TO_W1R0_OFF (20u)

/** \brief  Length for Ifx_GTM_AFD_CH_BUF_ACC_Bits.DATA */
#define IFX_GTM_AFD_CH_BUF_ACC_DATA_LEN (29u)

/** \brief  Mask for Ifx_GTM_AFD_CH_BUF_ACC_Bits.DATA */
#define IFX_GTM_AFD_CH_BUF_ACC_DATA_MSK (0x1fffffffu)

/** \brief  Offset for Ifx_GTM_AFD_CH_BUF_ACC_Bits.DATA */
#define IFX_GTM_AFD_CH_BUF_ACC_DATA_OFF (0u)

/** \brief  Length for Ifx_GTM_ARU_ARU_ACCESS_Bits.ADDR */
#define IFX_GTM_ARU_ARU_ACCESS_ADDR_LEN (9u)

/** \brief  Mask for Ifx_GTM_ARU_ARU_ACCESS_Bits.ADDR */
#define IFX_GTM_ARU_ARU_ACCESS_ADDR_MSK (0x1ffu)

/** \brief  Offset for Ifx_GTM_ARU_ARU_ACCESS_Bits.ADDR */
#define IFX_GTM_ARU_ARU_ACCESS_ADDR_OFF (0u)

/** \brief  Length for Ifx_GTM_ARU_ARU_ACCESS_Bits.RREQ */
#define IFX_GTM_ARU_ARU_ACCESS_RREQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ARU_ARU_ACCESS_Bits.RREQ */
#define IFX_GTM_ARU_ARU_ACCESS_RREQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ARU_ARU_ACCESS_Bits.RREQ */
#define IFX_GTM_ARU_ARU_ACCESS_RREQ_OFF (12u)

/** \brief  Length for Ifx_GTM_ARU_ARU_ACCESS_Bits.WREQ */
#define IFX_GTM_ARU_ARU_ACCESS_WREQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ARU_ARU_ACCESS_Bits.WREQ */
#define IFX_GTM_ARU_ARU_ACCESS_WREQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ARU_ARU_ACCESS_Bits.WREQ */
#define IFX_GTM_ARU_ARU_ACCESS_WREQ_OFF (13u)

/** \brief  Length for Ifx_GTM_ARU_DATA_H_Bits.DATA */
#define IFX_GTM_ARU_DATA_H_DATA_LEN (29u)

/** \brief  Mask for Ifx_GTM_ARU_DATA_H_Bits.DATA */
#define IFX_GTM_ARU_DATA_H_DATA_MSK (0x1fffffffu)

/** \brief  Offset for Ifx_GTM_ARU_DATA_H_Bits.DATA */
#define IFX_GTM_ARU_DATA_H_DATA_OFF (0u)

/** \brief  Length for Ifx_GTM_ARU_DATA_L_Bits.DATA */
#define IFX_GTM_ARU_DATA_L_DATA_LEN (29u)

/** \brief  Mask for Ifx_GTM_ARU_DATA_L_Bits.DATA */
#define IFX_GTM_ARU_DATA_L_DATA_MSK (0x1fffffffu)

/** \brief  Offset for Ifx_GTM_ARU_DATA_L_Bits.DATA */
#define IFX_GTM_ARU_DATA_L_DATA_OFF (0u)

/** \brief  Length for Ifx_GTM_ARU_DBG_ACCESS0_Bits.ADDR */
#define IFX_GTM_ARU_DBG_ACCESS0_ADDR_LEN (9u)

/** \brief  Mask for Ifx_GTM_ARU_DBG_ACCESS0_Bits.ADDR */
#define IFX_GTM_ARU_DBG_ACCESS0_ADDR_MSK (0x1ffu)

/** \brief  Offset for Ifx_GTM_ARU_DBG_ACCESS0_Bits.ADDR */
#define IFX_GTM_ARU_DBG_ACCESS0_ADDR_OFF (0u)

/** \brief  Length for Ifx_GTM_ARU_DBG_ACCESS1_Bits.ADDR */
#define IFX_GTM_ARU_DBG_ACCESS1_ADDR_LEN (9u)

/** \brief  Mask for Ifx_GTM_ARU_DBG_ACCESS1_Bits.ADDR */
#define IFX_GTM_ARU_DBG_ACCESS1_ADDR_MSK (0x1ffu)

/** \brief  Offset for Ifx_GTM_ARU_DBG_ACCESS1_Bits.ADDR */
#define IFX_GTM_ARU_DBG_ACCESS1_ADDR_OFF (0u)

/** \brief  Length for Ifx_GTM_ARU_DBG_DATA0_H_Bits.DATA */
#define IFX_GTM_ARU_DBG_DATA0_H_DATA_LEN (29u)

/** \brief  Mask for Ifx_GTM_ARU_DBG_DATA0_H_Bits.DATA */
#define IFX_GTM_ARU_DBG_DATA0_H_DATA_MSK (0x1fffffffu)

/** \brief  Offset for Ifx_GTM_ARU_DBG_DATA0_H_Bits.DATA */
#define IFX_GTM_ARU_DBG_DATA0_H_DATA_OFF (0u)

/** \brief  Length for Ifx_GTM_ARU_DBG_DATA0_L_Bits.DATA */
#define IFX_GTM_ARU_DBG_DATA0_L_DATA_LEN (29u)

/** \brief  Mask for Ifx_GTM_ARU_DBG_DATA0_L_Bits.DATA */
#define IFX_GTM_ARU_DBG_DATA0_L_DATA_MSK (0x1fffffffu)

/** \brief  Offset for Ifx_GTM_ARU_DBG_DATA0_L_Bits.DATA */
#define IFX_GTM_ARU_DBG_DATA0_L_DATA_OFF (0u)

/** \brief  Length for Ifx_GTM_ARU_DBG_DATA1_H_Bits.DATA */
#define IFX_GTM_ARU_DBG_DATA1_H_DATA_LEN (29u)

/** \brief  Mask for Ifx_GTM_ARU_DBG_DATA1_H_Bits.DATA */
#define IFX_GTM_ARU_DBG_DATA1_H_DATA_MSK (0x1fffffffu)

/** \brief  Offset for Ifx_GTM_ARU_DBG_DATA1_H_Bits.DATA */
#define IFX_GTM_ARU_DBG_DATA1_H_DATA_OFF (0u)

/** \brief  Length for Ifx_GTM_ARU_DBG_DATA1_L_Bits.DATA */
#define IFX_GTM_ARU_DBG_DATA1_L_DATA_LEN (29u)

/** \brief  Mask for Ifx_GTM_ARU_DBG_DATA1_L_Bits.DATA */
#define IFX_GTM_ARU_DBG_DATA1_L_DATA_MSK (0x1fffffffu)

/** \brief  Offset for Ifx_GTM_ARU_DBG_DATA1_L_Bits.DATA */
#define IFX_GTM_ARU_DBG_DATA1_L_DATA_OFF (0u)

/** \brief  Length for Ifx_GTM_ARU_IRQ_EN_Bits.ACC_ACK_IRQ_EN */
#define IFX_GTM_ARU_IRQ_EN_ACC_ACK_IRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_ARU_IRQ_EN_Bits.ACC_ACK_IRQ_EN */
#define IFX_GTM_ARU_IRQ_EN_ACC_ACK_IRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ARU_IRQ_EN_Bits.ACC_ACK_IRQ_EN */
#define IFX_GTM_ARU_IRQ_EN_ACC_ACK_IRQ_EN_OFF (2u)

/** \brief  Length for Ifx_GTM_ARU_IRQ_EN_Bits.NEW_DATA0_IRQ_EN */
#define IFX_GTM_ARU_IRQ_EN_NEW_DATA0_IRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_ARU_IRQ_EN_Bits.NEW_DATA0_IRQ_EN */
#define IFX_GTM_ARU_IRQ_EN_NEW_DATA0_IRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ARU_IRQ_EN_Bits.NEW_DATA0_IRQ_EN */
#define IFX_GTM_ARU_IRQ_EN_NEW_DATA0_IRQ_EN_OFF (0u)

/** \brief  Length for Ifx_GTM_ARU_IRQ_EN_Bits.NEW_DATA1_IRQ_EN */
#define IFX_GTM_ARU_IRQ_EN_NEW_DATA1_IRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_ARU_IRQ_EN_Bits.NEW_DATA1_IRQ_EN */
#define IFX_GTM_ARU_IRQ_EN_NEW_DATA1_IRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ARU_IRQ_EN_Bits.NEW_DATA1_IRQ_EN */
#define IFX_GTM_ARU_IRQ_EN_NEW_DATA1_IRQ_EN_OFF (1u)

/** \brief  Length for Ifx_GTM_ARU_IRQ_FORCINT_Bits.TRG_ACC_ACK */
#define IFX_GTM_ARU_IRQ_FORCINT_TRG_ACC_ACK_LEN (1u)

/** \brief  Mask for Ifx_GTM_ARU_IRQ_FORCINT_Bits.TRG_ACC_ACK */
#define IFX_GTM_ARU_IRQ_FORCINT_TRG_ACC_ACK_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ARU_IRQ_FORCINT_Bits.TRG_ACC_ACK */
#define IFX_GTM_ARU_IRQ_FORCINT_TRG_ACC_ACK_OFF (2u)

/** \brief  Length for Ifx_GTM_ARU_IRQ_FORCINT_Bits.TRG_NEW_DATA0 */
#define IFX_GTM_ARU_IRQ_FORCINT_TRG_NEW_DATA0_LEN (1u)

/** \brief  Mask for Ifx_GTM_ARU_IRQ_FORCINT_Bits.TRG_NEW_DATA0 */
#define IFX_GTM_ARU_IRQ_FORCINT_TRG_NEW_DATA0_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ARU_IRQ_FORCINT_Bits.TRG_NEW_DATA0 */
#define IFX_GTM_ARU_IRQ_FORCINT_TRG_NEW_DATA0_OFF (0u)

/** \brief  Length for Ifx_GTM_ARU_IRQ_FORCINT_Bits.TRG_NEW_DATA */
#define IFX_GTM_ARU_IRQ_FORCINT_TRG_NEW_DATA_LEN (1u)

/** \brief  Mask for Ifx_GTM_ARU_IRQ_FORCINT_Bits.TRG_NEW_DATA */
#define IFX_GTM_ARU_IRQ_FORCINT_TRG_NEW_DATA_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ARU_IRQ_FORCINT_Bits.TRG_NEW_DATA */
#define IFX_GTM_ARU_IRQ_FORCINT_TRG_NEW_DATA_OFF (1u)

/** \brief  Length for Ifx_GTM_ARU_IRQ_MODE_Bits.IRQ_MODE */
#define IFX_GTM_ARU_IRQ_MODE_IRQ_MODE_LEN (2u)

/** \brief  Mask for Ifx_GTM_ARU_IRQ_MODE_Bits.IRQ_MODE */
#define IFX_GTM_ARU_IRQ_MODE_IRQ_MODE_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_ARU_IRQ_MODE_Bits.IRQ_MODE */
#define IFX_GTM_ARU_IRQ_MODE_IRQ_MODE_OFF (0u)

/** \brief  Length for Ifx_GTM_ARU_IRQ_NOTIFY_Bits.ACC_ACK */
#define IFX_GTM_ARU_IRQ_NOTIFY_ACC_ACK_LEN (1u)

/** \brief  Mask for Ifx_GTM_ARU_IRQ_NOTIFY_Bits.ACC_ACK */
#define IFX_GTM_ARU_IRQ_NOTIFY_ACC_ACK_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ARU_IRQ_NOTIFY_Bits.ACC_ACK */
#define IFX_GTM_ARU_IRQ_NOTIFY_ACC_ACK_OFF (2u)

/** \brief  Length for Ifx_GTM_ARU_IRQ_NOTIFY_Bits.NEW_DATA0 */
#define IFX_GTM_ARU_IRQ_NOTIFY_NEW_DATA0_LEN (1u)

/** \brief  Mask for Ifx_GTM_ARU_IRQ_NOTIFY_Bits.NEW_DATA0 */
#define IFX_GTM_ARU_IRQ_NOTIFY_NEW_DATA0_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ARU_IRQ_NOTIFY_Bits.NEW_DATA0 */
#define IFX_GTM_ARU_IRQ_NOTIFY_NEW_DATA0_OFF (0u)

/** \brief  Length for Ifx_GTM_ARU_IRQ_NOTIFY_Bits.NEW_DATA1 */
#define IFX_GTM_ARU_IRQ_NOTIFY_NEW_DATA1_LEN (1u)

/** \brief  Mask for Ifx_GTM_ARU_IRQ_NOTIFY_Bits.NEW_DATA1 */
#define IFX_GTM_ARU_IRQ_NOTIFY_NEW_DATA1_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ARU_IRQ_NOTIFY_Bits.NEW_DATA1 */
#define IFX_GTM_ARU_IRQ_NOTIFY_NEW_DATA1_OFF (1u)

/** \brief  Length for Ifx_GTM_ATOM_AGC_ACT_TB_Bits.ACT_TB */
#define IFX_GTM_ATOM_AGC_ACT_TB_ACT_TB_LEN (24u)

/** \brief  Mask for Ifx_GTM_ATOM_AGC_ACT_TB_Bits.ACT_TB */
#define IFX_GTM_ATOM_AGC_ACT_TB_ACT_TB_MSK (0xffffffu)

/** \brief  Offset for Ifx_GTM_ATOM_AGC_ACT_TB_Bits.ACT_TB */
#define IFX_GTM_ATOM_AGC_ACT_TB_ACT_TB_OFF (0u)

/** \brief  Length for Ifx_GTM_ATOM_AGC_ACT_TB_Bits.TB_TRIG */
#define IFX_GTM_ATOM_AGC_ACT_TB_TB_TRIG_LEN (1u)

/** \brief  Mask for Ifx_GTM_ATOM_AGC_ACT_TB_Bits.TB_TRIG */
#define IFX_GTM_ATOM_AGC_ACT_TB_TB_TRIG_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ATOM_AGC_ACT_TB_Bits.TB_TRIG */
#define IFX_GTM_ATOM_AGC_ACT_TB_TB_TRIG_OFF (24u)

/** \brief  Length for Ifx_GTM_ATOM_AGC_ACT_TB_Bits.TBU_SEL */
#define IFX_GTM_ATOM_AGC_ACT_TB_TBU_SEL_LEN (2u)

/** \brief  Mask for Ifx_GTM_ATOM_AGC_ACT_TB_Bits.TBU_SEL */
#define IFX_GTM_ATOM_AGC_ACT_TB_TBU_SEL_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_ATOM_AGC_ACT_TB_Bits.TBU_SEL */
#define IFX_GTM_ATOM_AGC_ACT_TB_TBU_SEL_OFF (25u)

/** \brief  Length for Ifx_GTM_ATOM_AGC_ENDIS_CTRL_Bits.ENDIS_CTRL0 */
#define IFX_GTM_ATOM_AGC_ENDIS_CTRL_ENDIS_CTRL0_LEN (2u)

/** \brief  Mask for Ifx_GTM_ATOM_AGC_ENDIS_CTRL_Bits.ENDIS_CTRL0 */
#define IFX_GTM_ATOM_AGC_ENDIS_CTRL_ENDIS_CTRL0_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_ATOM_AGC_ENDIS_CTRL_Bits.ENDIS_CTRL0 */
#define IFX_GTM_ATOM_AGC_ENDIS_CTRL_ENDIS_CTRL0_OFF (0u)

/** \brief  Length for Ifx_GTM_ATOM_AGC_ENDIS_CTRL_Bits.ENDIS_CTRL1 */
#define IFX_GTM_ATOM_AGC_ENDIS_CTRL_ENDIS_CTRL1_LEN (2u)

/** \brief  Mask for Ifx_GTM_ATOM_AGC_ENDIS_CTRL_Bits.ENDIS_CTRL1 */
#define IFX_GTM_ATOM_AGC_ENDIS_CTRL_ENDIS_CTRL1_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_ATOM_AGC_ENDIS_CTRL_Bits.ENDIS_CTRL1 */
#define IFX_GTM_ATOM_AGC_ENDIS_CTRL_ENDIS_CTRL1_OFF (2u)

/** \brief  Length for Ifx_GTM_ATOM_AGC_ENDIS_CTRL_Bits.ENDIS_CTRL2 */
#define IFX_GTM_ATOM_AGC_ENDIS_CTRL_ENDIS_CTRL2_LEN (2u)

/** \brief  Mask for Ifx_GTM_ATOM_AGC_ENDIS_CTRL_Bits.ENDIS_CTRL2 */
#define IFX_GTM_ATOM_AGC_ENDIS_CTRL_ENDIS_CTRL2_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_ATOM_AGC_ENDIS_CTRL_Bits.ENDIS_CTRL2 */
#define IFX_GTM_ATOM_AGC_ENDIS_CTRL_ENDIS_CTRL2_OFF (4u)

/** \brief  Length for Ifx_GTM_ATOM_AGC_ENDIS_CTRL_Bits.ENDIS_CTRL3 */
#define IFX_GTM_ATOM_AGC_ENDIS_CTRL_ENDIS_CTRL3_LEN (2u)

/** \brief  Mask for Ifx_GTM_ATOM_AGC_ENDIS_CTRL_Bits.ENDIS_CTRL3 */
#define IFX_GTM_ATOM_AGC_ENDIS_CTRL_ENDIS_CTRL3_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_ATOM_AGC_ENDIS_CTRL_Bits.ENDIS_CTRL3 */
#define IFX_GTM_ATOM_AGC_ENDIS_CTRL_ENDIS_CTRL3_OFF (6u)

/** \brief  Length for Ifx_GTM_ATOM_AGC_ENDIS_CTRL_Bits.ENDIS_CTRL4 */
#define IFX_GTM_ATOM_AGC_ENDIS_CTRL_ENDIS_CTRL4_LEN (2u)

/** \brief  Mask for Ifx_GTM_ATOM_AGC_ENDIS_CTRL_Bits.ENDIS_CTRL4 */
#define IFX_GTM_ATOM_AGC_ENDIS_CTRL_ENDIS_CTRL4_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_ATOM_AGC_ENDIS_CTRL_Bits.ENDIS_CTRL4 */
#define IFX_GTM_ATOM_AGC_ENDIS_CTRL_ENDIS_CTRL4_OFF (8u)

/** \brief  Length for Ifx_GTM_ATOM_AGC_ENDIS_CTRL_Bits.ENDIS_CTRL5 */
#define IFX_GTM_ATOM_AGC_ENDIS_CTRL_ENDIS_CTRL5_LEN (2u)

/** \brief  Mask for Ifx_GTM_ATOM_AGC_ENDIS_CTRL_Bits.ENDIS_CTRL5 */
#define IFX_GTM_ATOM_AGC_ENDIS_CTRL_ENDIS_CTRL5_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_ATOM_AGC_ENDIS_CTRL_Bits.ENDIS_CTRL5 */
#define IFX_GTM_ATOM_AGC_ENDIS_CTRL_ENDIS_CTRL5_OFF (10u)

/** \brief  Length for Ifx_GTM_ATOM_AGC_ENDIS_CTRL_Bits.ENDIS_CTRL6 */
#define IFX_GTM_ATOM_AGC_ENDIS_CTRL_ENDIS_CTRL6_LEN (2u)

/** \brief  Mask for Ifx_GTM_ATOM_AGC_ENDIS_CTRL_Bits.ENDIS_CTRL6 */
#define IFX_GTM_ATOM_AGC_ENDIS_CTRL_ENDIS_CTRL6_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_ATOM_AGC_ENDIS_CTRL_Bits.ENDIS_CTRL6 */
#define IFX_GTM_ATOM_AGC_ENDIS_CTRL_ENDIS_CTRL6_OFF (12u)

/** \brief  Length for Ifx_GTM_ATOM_AGC_ENDIS_CTRL_Bits.ENDIS_CTRL7 */
#define IFX_GTM_ATOM_AGC_ENDIS_CTRL_ENDIS_CTRL7_LEN (2u)

/** \brief  Mask for Ifx_GTM_ATOM_AGC_ENDIS_CTRL_Bits.ENDIS_CTRL7 */
#define IFX_GTM_ATOM_AGC_ENDIS_CTRL_ENDIS_CTRL7_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_ATOM_AGC_ENDIS_CTRL_Bits.ENDIS_CTRL7 */
#define IFX_GTM_ATOM_AGC_ENDIS_CTRL_ENDIS_CTRL7_OFF (14u)

/** \brief  Length for Ifx_GTM_ATOM_AGC_ENDIS_STAT_Bits.ENDIS_STAT0 */
#define IFX_GTM_ATOM_AGC_ENDIS_STAT_ENDIS_STAT0_LEN (2u)

/** \brief  Mask for Ifx_GTM_ATOM_AGC_ENDIS_STAT_Bits.ENDIS_STAT0 */
#define IFX_GTM_ATOM_AGC_ENDIS_STAT_ENDIS_STAT0_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_ATOM_AGC_ENDIS_STAT_Bits.ENDIS_STAT0 */
#define IFX_GTM_ATOM_AGC_ENDIS_STAT_ENDIS_STAT0_OFF (0u)

/** \brief  Length for Ifx_GTM_ATOM_AGC_ENDIS_STAT_Bits.ENDIS_STAT1 */
#define IFX_GTM_ATOM_AGC_ENDIS_STAT_ENDIS_STAT1_LEN (2u)

/** \brief  Mask for Ifx_GTM_ATOM_AGC_ENDIS_STAT_Bits.ENDIS_STAT1 */
#define IFX_GTM_ATOM_AGC_ENDIS_STAT_ENDIS_STAT1_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_ATOM_AGC_ENDIS_STAT_Bits.ENDIS_STAT1 */
#define IFX_GTM_ATOM_AGC_ENDIS_STAT_ENDIS_STAT1_OFF (2u)

/** \brief  Length for Ifx_GTM_ATOM_AGC_ENDIS_STAT_Bits.ENDIS_STAT2 */
#define IFX_GTM_ATOM_AGC_ENDIS_STAT_ENDIS_STAT2_LEN (2u)

/** \brief  Mask for Ifx_GTM_ATOM_AGC_ENDIS_STAT_Bits.ENDIS_STAT2 */
#define IFX_GTM_ATOM_AGC_ENDIS_STAT_ENDIS_STAT2_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_ATOM_AGC_ENDIS_STAT_Bits.ENDIS_STAT2 */
#define IFX_GTM_ATOM_AGC_ENDIS_STAT_ENDIS_STAT2_OFF (4u)

/** \brief  Length for Ifx_GTM_ATOM_AGC_ENDIS_STAT_Bits.ENDIS_STAT3 */
#define IFX_GTM_ATOM_AGC_ENDIS_STAT_ENDIS_STAT3_LEN (2u)

/** \brief  Mask for Ifx_GTM_ATOM_AGC_ENDIS_STAT_Bits.ENDIS_STAT3 */
#define IFX_GTM_ATOM_AGC_ENDIS_STAT_ENDIS_STAT3_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_ATOM_AGC_ENDIS_STAT_Bits.ENDIS_STAT3 */
#define IFX_GTM_ATOM_AGC_ENDIS_STAT_ENDIS_STAT3_OFF (6u)

/** \brief  Length for Ifx_GTM_ATOM_AGC_ENDIS_STAT_Bits.ENDIS_STAT4 */
#define IFX_GTM_ATOM_AGC_ENDIS_STAT_ENDIS_STAT4_LEN (2u)

/** \brief  Mask for Ifx_GTM_ATOM_AGC_ENDIS_STAT_Bits.ENDIS_STAT4 */
#define IFX_GTM_ATOM_AGC_ENDIS_STAT_ENDIS_STAT4_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_ATOM_AGC_ENDIS_STAT_Bits.ENDIS_STAT4 */
#define IFX_GTM_ATOM_AGC_ENDIS_STAT_ENDIS_STAT4_OFF (8u)

/** \brief  Length for Ifx_GTM_ATOM_AGC_ENDIS_STAT_Bits.ENDIS_STAT5 */
#define IFX_GTM_ATOM_AGC_ENDIS_STAT_ENDIS_STAT5_LEN (2u)

/** \brief  Mask for Ifx_GTM_ATOM_AGC_ENDIS_STAT_Bits.ENDIS_STAT5 */
#define IFX_GTM_ATOM_AGC_ENDIS_STAT_ENDIS_STAT5_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_ATOM_AGC_ENDIS_STAT_Bits.ENDIS_STAT5 */
#define IFX_GTM_ATOM_AGC_ENDIS_STAT_ENDIS_STAT5_OFF (10u)

/** \brief  Length for Ifx_GTM_ATOM_AGC_ENDIS_STAT_Bits.ENDIS_STAT6 */
#define IFX_GTM_ATOM_AGC_ENDIS_STAT_ENDIS_STAT6_LEN (2u)

/** \brief  Mask for Ifx_GTM_ATOM_AGC_ENDIS_STAT_Bits.ENDIS_STAT6 */
#define IFX_GTM_ATOM_AGC_ENDIS_STAT_ENDIS_STAT6_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_ATOM_AGC_ENDIS_STAT_Bits.ENDIS_STAT6 */
#define IFX_GTM_ATOM_AGC_ENDIS_STAT_ENDIS_STAT6_OFF (12u)

/** \brief  Length for Ifx_GTM_ATOM_AGC_ENDIS_STAT_Bits.ENDIS_STAT7 */
#define IFX_GTM_ATOM_AGC_ENDIS_STAT_ENDIS_STAT7_LEN (2u)

/** \brief  Mask for Ifx_GTM_ATOM_AGC_ENDIS_STAT_Bits.ENDIS_STAT7 */
#define IFX_GTM_ATOM_AGC_ENDIS_STAT_ENDIS_STAT7_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_ATOM_AGC_ENDIS_STAT_Bits.ENDIS_STAT7 */
#define IFX_GTM_ATOM_AGC_ENDIS_STAT_ENDIS_STAT7_OFF (14u)

/** \brief  Length for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.FUPD_CTRL0 */
#define IFX_GTM_ATOM_AGC_FUPD_CTRL_FUPD_CTRL0_LEN (2u)

/** \brief  Mask for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.FUPD_CTRL0 */
#define IFX_GTM_ATOM_AGC_FUPD_CTRL_FUPD_CTRL0_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.FUPD_CTRL0 */
#define IFX_GTM_ATOM_AGC_FUPD_CTRL_FUPD_CTRL0_OFF (0u)

/** \brief  Length for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.FUPD_CTRL1 */
#define IFX_GTM_ATOM_AGC_FUPD_CTRL_FUPD_CTRL1_LEN (2u)

/** \brief  Mask for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.FUPD_CTRL1 */
#define IFX_GTM_ATOM_AGC_FUPD_CTRL_FUPD_CTRL1_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.FUPD_CTRL1 */
#define IFX_GTM_ATOM_AGC_FUPD_CTRL_FUPD_CTRL1_OFF (2u)

/** \brief  Length for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.FUPD_CTRL2 */
#define IFX_GTM_ATOM_AGC_FUPD_CTRL_FUPD_CTRL2_LEN (2u)

/** \brief  Mask for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.FUPD_CTRL2 */
#define IFX_GTM_ATOM_AGC_FUPD_CTRL_FUPD_CTRL2_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.FUPD_CTRL2 */
#define IFX_GTM_ATOM_AGC_FUPD_CTRL_FUPD_CTRL2_OFF (4u)

/** \brief  Length for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.FUPD_CTRL3 */
#define IFX_GTM_ATOM_AGC_FUPD_CTRL_FUPD_CTRL3_LEN (2u)

/** \brief  Mask for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.FUPD_CTRL3 */
#define IFX_GTM_ATOM_AGC_FUPD_CTRL_FUPD_CTRL3_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.FUPD_CTRL3 */
#define IFX_GTM_ATOM_AGC_FUPD_CTRL_FUPD_CTRL3_OFF (6u)

/** \brief  Length for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.FUPD_CTRL4 */
#define IFX_GTM_ATOM_AGC_FUPD_CTRL_FUPD_CTRL4_LEN (2u)

/** \brief  Mask for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.FUPD_CTRL4 */
#define IFX_GTM_ATOM_AGC_FUPD_CTRL_FUPD_CTRL4_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.FUPD_CTRL4 */
#define IFX_GTM_ATOM_AGC_FUPD_CTRL_FUPD_CTRL4_OFF (8u)

/** \brief  Length for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.FUPD_CTRL5 */
#define IFX_GTM_ATOM_AGC_FUPD_CTRL_FUPD_CTRL5_LEN (2u)

/** \brief  Mask for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.FUPD_CTRL5 */
#define IFX_GTM_ATOM_AGC_FUPD_CTRL_FUPD_CTRL5_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.FUPD_CTRL5 */
#define IFX_GTM_ATOM_AGC_FUPD_CTRL_FUPD_CTRL5_OFF (10u)

/** \brief  Length for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.FUPD_CTRL6 */
#define IFX_GTM_ATOM_AGC_FUPD_CTRL_FUPD_CTRL6_LEN (2u)

/** \brief  Mask for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.FUPD_CTRL6 */
#define IFX_GTM_ATOM_AGC_FUPD_CTRL_FUPD_CTRL6_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.FUPD_CTRL6 */
#define IFX_GTM_ATOM_AGC_FUPD_CTRL_FUPD_CTRL6_OFF (12u)

/** \brief  Length for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.FUPD_CTRL7 */
#define IFX_GTM_ATOM_AGC_FUPD_CTRL_FUPD_CTRL7_LEN (2u)

/** \brief  Mask for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.FUPD_CTRL7 */
#define IFX_GTM_ATOM_AGC_FUPD_CTRL_FUPD_CTRL7_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.FUPD_CTRL7 */
#define IFX_GTM_ATOM_AGC_FUPD_CTRL_FUPD_CTRL7_OFF (14u)

/** \brief  Length for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.RSTCN0_CH0 */
#define IFX_GTM_ATOM_AGC_FUPD_CTRL_RSTCN0_CH0_LEN (2u)

/** \brief  Mask for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.RSTCN0_CH0 */
#define IFX_GTM_ATOM_AGC_FUPD_CTRL_RSTCN0_CH0_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.RSTCN0_CH0 */
#define IFX_GTM_ATOM_AGC_FUPD_CTRL_RSTCN0_CH0_OFF (16u)

/** \brief  Length for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.RSTCN0_CH1 */
#define IFX_GTM_ATOM_AGC_FUPD_CTRL_RSTCN0_CH1_LEN (2u)

/** \brief  Mask for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.RSTCN0_CH1 */
#define IFX_GTM_ATOM_AGC_FUPD_CTRL_RSTCN0_CH1_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.RSTCN0_CH1 */
#define IFX_GTM_ATOM_AGC_FUPD_CTRL_RSTCN0_CH1_OFF (18u)

/** \brief  Length for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.RSTCN0_CH2 */
#define IFX_GTM_ATOM_AGC_FUPD_CTRL_RSTCN0_CH2_LEN (2u)

/** \brief  Mask for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.RSTCN0_CH2 */
#define IFX_GTM_ATOM_AGC_FUPD_CTRL_RSTCN0_CH2_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.RSTCN0_CH2 */
#define IFX_GTM_ATOM_AGC_FUPD_CTRL_RSTCN0_CH2_OFF (20u)

/** \brief  Length for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.RSTCN0_CH3 */
#define IFX_GTM_ATOM_AGC_FUPD_CTRL_RSTCN0_CH3_LEN (2u)

/** \brief  Mask for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.RSTCN0_CH3 */
#define IFX_GTM_ATOM_AGC_FUPD_CTRL_RSTCN0_CH3_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.RSTCN0_CH3 */
#define IFX_GTM_ATOM_AGC_FUPD_CTRL_RSTCN0_CH3_OFF (22u)

/** \brief  Length for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.RSTCN0_CH4 */
#define IFX_GTM_ATOM_AGC_FUPD_CTRL_RSTCN0_CH4_LEN (2u)

/** \brief  Mask for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.RSTCN0_CH4 */
#define IFX_GTM_ATOM_AGC_FUPD_CTRL_RSTCN0_CH4_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.RSTCN0_CH4 */
#define IFX_GTM_ATOM_AGC_FUPD_CTRL_RSTCN0_CH4_OFF (24u)

/** \brief  Length for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.RSTCN0_CH5 */
#define IFX_GTM_ATOM_AGC_FUPD_CTRL_RSTCN0_CH5_LEN (2u)

/** \brief  Mask for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.RSTCN0_CH5 */
#define IFX_GTM_ATOM_AGC_FUPD_CTRL_RSTCN0_CH5_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.RSTCN0_CH5 */
#define IFX_GTM_ATOM_AGC_FUPD_CTRL_RSTCN0_CH5_OFF (26u)

/** \brief  Length for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.RSTCN0_CH6 */
#define IFX_GTM_ATOM_AGC_FUPD_CTRL_RSTCN0_CH6_LEN (2u)

/** \brief  Mask for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.RSTCN0_CH6 */
#define IFX_GTM_ATOM_AGC_FUPD_CTRL_RSTCN0_CH6_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.RSTCN0_CH6 */
#define IFX_GTM_ATOM_AGC_FUPD_CTRL_RSTCN0_CH6_OFF (28u)

/** \brief  Length for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.RSTCN0_CH7 */
#define IFX_GTM_ATOM_AGC_FUPD_CTRL_RSTCN0_CH7_LEN (2u)

/** \brief  Mask for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.RSTCN0_CH7 */
#define IFX_GTM_ATOM_AGC_FUPD_CTRL_RSTCN0_CH7_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_ATOM_AGC_FUPD_CTRL_Bits.RSTCN0_CH7 */
#define IFX_GTM_ATOM_AGC_FUPD_CTRL_RSTCN0_CH7_OFF (30u)

/** \brief  Length for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.HOST_TRIG */
#define IFX_GTM_ATOM_AGC_GLB_CTRL_HOST_TRIG_LEN (1u)

/** \brief  Mask for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.HOST_TRIG */
#define IFX_GTM_ATOM_AGC_GLB_CTRL_HOST_TRIG_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.HOST_TRIG */
#define IFX_GTM_ATOM_AGC_GLB_CTRL_HOST_TRIG_OFF (0u)

/** \brief  Length for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.RST_CH0 */
#define IFX_GTM_ATOM_AGC_GLB_CTRL_RST_CH0_LEN (1u)

/** \brief  Mask for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.RST_CH0 */
#define IFX_GTM_ATOM_AGC_GLB_CTRL_RST_CH0_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.RST_CH0 */
#define IFX_GTM_ATOM_AGC_GLB_CTRL_RST_CH0_OFF (8u)

/** \brief  Length for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.RST_CH1 */
#define IFX_GTM_ATOM_AGC_GLB_CTRL_RST_CH1_LEN (1u)

/** \brief  Mask for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.RST_CH1 */
#define IFX_GTM_ATOM_AGC_GLB_CTRL_RST_CH1_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.RST_CH1 */
#define IFX_GTM_ATOM_AGC_GLB_CTRL_RST_CH1_OFF (9u)

/** \brief  Length for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.RST_CH2 */
#define IFX_GTM_ATOM_AGC_GLB_CTRL_RST_CH2_LEN (1u)

/** \brief  Mask for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.RST_CH2 */
#define IFX_GTM_ATOM_AGC_GLB_CTRL_RST_CH2_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.RST_CH2 */
#define IFX_GTM_ATOM_AGC_GLB_CTRL_RST_CH2_OFF (10u)

/** \brief  Length for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.RST_CH3 */
#define IFX_GTM_ATOM_AGC_GLB_CTRL_RST_CH3_LEN (1u)

/** \brief  Mask for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.RST_CH3 */
#define IFX_GTM_ATOM_AGC_GLB_CTRL_RST_CH3_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.RST_CH3 */
#define IFX_GTM_ATOM_AGC_GLB_CTRL_RST_CH3_OFF (11u)

/** \brief  Length for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.RST_CH4 */
#define IFX_GTM_ATOM_AGC_GLB_CTRL_RST_CH4_LEN (1u)

/** \brief  Mask for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.RST_CH4 */
#define IFX_GTM_ATOM_AGC_GLB_CTRL_RST_CH4_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.RST_CH4 */
#define IFX_GTM_ATOM_AGC_GLB_CTRL_RST_CH4_OFF (12u)

/** \brief  Length for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.RST_CH5 */
#define IFX_GTM_ATOM_AGC_GLB_CTRL_RST_CH5_LEN (1u)

/** \brief  Mask for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.RST_CH5 */
#define IFX_GTM_ATOM_AGC_GLB_CTRL_RST_CH5_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.RST_CH5 */
#define IFX_GTM_ATOM_AGC_GLB_CTRL_RST_CH5_OFF (13u)

/** \brief  Length for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.RST_CH6 */
#define IFX_GTM_ATOM_AGC_GLB_CTRL_RST_CH6_LEN (1u)

/** \brief  Mask for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.RST_CH6 */
#define IFX_GTM_ATOM_AGC_GLB_CTRL_RST_CH6_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.RST_CH6 */
#define IFX_GTM_ATOM_AGC_GLB_CTRL_RST_CH6_OFF (14u)

/** \brief  Length for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.RST_CH7 */
#define IFX_GTM_ATOM_AGC_GLB_CTRL_RST_CH7_LEN (1u)

/** \brief  Mask for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.RST_CH7 */
#define IFX_GTM_ATOM_AGC_GLB_CTRL_RST_CH7_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.RST_CH7 */
#define IFX_GTM_ATOM_AGC_GLB_CTRL_RST_CH7_OFF (15u)

/** \brief  Length for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.UPEN_CTRL0 */
#define IFX_GTM_ATOM_AGC_GLB_CTRL_UPEN_CTRL0_LEN (2u)

/** \brief  Mask for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.UPEN_CTRL0 */
#define IFX_GTM_ATOM_AGC_GLB_CTRL_UPEN_CTRL0_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.UPEN_CTRL0 */
#define IFX_GTM_ATOM_AGC_GLB_CTRL_UPEN_CTRL0_OFF (16u)

/** \brief  Length for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.UPEN_CTRL1 */
#define IFX_GTM_ATOM_AGC_GLB_CTRL_UPEN_CTRL1_LEN (2u)

/** \brief  Mask for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.UPEN_CTRL1 */
#define IFX_GTM_ATOM_AGC_GLB_CTRL_UPEN_CTRL1_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.UPEN_CTRL1 */
#define IFX_GTM_ATOM_AGC_GLB_CTRL_UPEN_CTRL1_OFF (18u)

/** \brief  Length for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.UPEN_CTRL2 */
#define IFX_GTM_ATOM_AGC_GLB_CTRL_UPEN_CTRL2_LEN (2u)

/** \brief  Mask for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.UPEN_CTRL2 */
#define IFX_GTM_ATOM_AGC_GLB_CTRL_UPEN_CTRL2_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.UPEN_CTRL2 */
#define IFX_GTM_ATOM_AGC_GLB_CTRL_UPEN_CTRL2_OFF (20u)

/** \brief  Length for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.UPEN_CTRL3 */
#define IFX_GTM_ATOM_AGC_GLB_CTRL_UPEN_CTRL3_LEN (2u)

/** \brief  Mask for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.UPEN_CTRL3 */
#define IFX_GTM_ATOM_AGC_GLB_CTRL_UPEN_CTRL3_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.UPEN_CTRL3 */
#define IFX_GTM_ATOM_AGC_GLB_CTRL_UPEN_CTRL3_OFF (22u)

/** \brief  Length for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.UPEN_CTRL4 */
#define IFX_GTM_ATOM_AGC_GLB_CTRL_UPEN_CTRL4_LEN (2u)

/** \brief  Mask for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.UPEN_CTRL4 */
#define IFX_GTM_ATOM_AGC_GLB_CTRL_UPEN_CTRL4_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.UPEN_CTRL4 */
#define IFX_GTM_ATOM_AGC_GLB_CTRL_UPEN_CTRL4_OFF (24u)

/** \brief  Length for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.UPEN_CTRL5 */
#define IFX_GTM_ATOM_AGC_GLB_CTRL_UPEN_CTRL5_LEN (2u)

/** \brief  Mask for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.UPEN_CTRL5 */
#define IFX_GTM_ATOM_AGC_GLB_CTRL_UPEN_CTRL5_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.UPEN_CTRL5 */
#define IFX_GTM_ATOM_AGC_GLB_CTRL_UPEN_CTRL5_OFF (26u)

/** \brief  Length for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.UPEN_CTRL6 */
#define IFX_GTM_ATOM_AGC_GLB_CTRL_UPEN_CTRL6_LEN (2u)

/** \brief  Mask for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.UPEN_CTRL6 */
#define IFX_GTM_ATOM_AGC_GLB_CTRL_UPEN_CTRL6_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.UPEN_CTRL6 */
#define IFX_GTM_ATOM_AGC_GLB_CTRL_UPEN_CTRL6_OFF (28u)

/** \brief  Length for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.UPEN_CTRL7 */
#define IFX_GTM_ATOM_AGC_GLB_CTRL_UPEN_CTRL7_LEN (2u)

/** \brief  Mask for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.UPEN_CTRL7 */
#define IFX_GTM_ATOM_AGC_GLB_CTRL_UPEN_CTRL7_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_ATOM_AGC_GLB_CTRL_Bits.UPEN_CTRL7 */
#define IFX_GTM_ATOM_AGC_GLB_CTRL_UPEN_CTRL7_OFF (30u)

/** \brief  Length for Ifx_GTM_ATOM_AGC_INT_TRIG_Bits.INT_TRIG0 */
#define IFX_GTM_ATOM_AGC_INT_TRIG_INT_TRIG0_LEN (2u)

/** \brief  Mask for Ifx_GTM_ATOM_AGC_INT_TRIG_Bits.INT_TRIG0 */
#define IFX_GTM_ATOM_AGC_INT_TRIG_INT_TRIG0_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_ATOM_AGC_INT_TRIG_Bits.INT_TRIG0 */
#define IFX_GTM_ATOM_AGC_INT_TRIG_INT_TRIG0_OFF (0u)

/** \brief  Length for Ifx_GTM_ATOM_AGC_INT_TRIG_Bits.INT_TRIG1 */
#define IFX_GTM_ATOM_AGC_INT_TRIG_INT_TRIG1_LEN (2u)

/** \brief  Mask for Ifx_GTM_ATOM_AGC_INT_TRIG_Bits.INT_TRIG1 */
#define IFX_GTM_ATOM_AGC_INT_TRIG_INT_TRIG1_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_ATOM_AGC_INT_TRIG_Bits.INT_TRIG1 */
#define IFX_GTM_ATOM_AGC_INT_TRIG_INT_TRIG1_OFF (2u)

/** \brief  Length for Ifx_GTM_ATOM_AGC_INT_TRIG_Bits.INT_TRIG2 */
#define IFX_GTM_ATOM_AGC_INT_TRIG_INT_TRIG2_LEN (2u)

/** \brief  Mask for Ifx_GTM_ATOM_AGC_INT_TRIG_Bits.INT_TRIG2 */
#define IFX_GTM_ATOM_AGC_INT_TRIG_INT_TRIG2_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_ATOM_AGC_INT_TRIG_Bits.INT_TRIG2 */
#define IFX_GTM_ATOM_AGC_INT_TRIG_INT_TRIG2_OFF (4u)

/** \brief  Length for Ifx_GTM_ATOM_AGC_INT_TRIG_Bits.INT_TRIG3 */
#define IFX_GTM_ATOM_AGC_INT_TRIG_INT_TRIG3_LEN (2u)

/** \brief  Mask for Ifx_GTM_ATOM_AGC_INT_TRIG_Bits.INT_TRIG3 */
#define IFX_GTM_ATOM_AGC_INT_TRIG_INT_TRIG3_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_ATOM_AGC_INT_TRIG_Bits.INT_TRIG3 */
#define IFX_GTM_ATOM_AGC_INT_TRIG_INT_TRIG3_OFF (6u)

/** \brief  Length for Ifx_GTM_ATOM_AGC_INT_TRIG_Bits.INT_TRIG4 */
#define IFX_GTM_ATOM_AGC_INT_TRIG_INT_TRIG4_LEN (2u)

/** \brief  Mask for Ifx_GTM_ATOM_AGC_INT_TRIG_Bits.INT_TRIG4 */
#define IFX_GTM_ATOM_AGC_INT_TRIG_INT_TRIG4_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_ATOM_AGC_INT_TRIG_Bits.INT_TRIG4 */
#define IFX_GTM_ATOM_AGC_INT_TRIG_INT_TRIG4_OFF (8u)

/** \brief  Length for Ifx_GTM_ATOM_AGC_INT_TRIG_Bits.INT_TRIG5 */
#define IFX_GTM_ATOM_AGC_INT_TRIG_INT_TRIG5_LEN (2u)

/** \brief  Mask for Ifx_GTM_ATOM_AGC_INT_TRIG_Bits.INT_TRIG5 */
#define IFX_GTM_ATOM_AGC_INT_TRIG_INT_TRIG5_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_ATOM_AGC_INT_TRIG_Bits.INT_TRIG5 */
#define IFX_GTM_ATOM_AGC_INT_TRIG_INT_TRIG5_OFF (10u)

/** \brief  Length for Ifx_GTM_ATOM_AGC_INT_TRIG_Bits.INT_TRIG6 */
#define IFX_GTM_ATOM_AGC_INT_TRIG_INT_TRIG6_LEN (2u)

/** \brief  Mask for Ifx_GTM_ATOM_AGC_INT_TRIG_Bits.INT_TRIG6 */
#define IFX_GTM_ATOM_AGC_INT_TRIG_INT_TRIG6_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_ATOM_AGC_INT_TRIG_Bits.INT_TRIG6 */
#define IFX_GTM_ATOM_AGC_INT_TRIG_INT_TRIG6_OFF (12u)

/** \brief  Length for Ifx_GTM_ATOM_AGC_INT_TRIG_Bits.INT_TRIG7 */
#define IFX_GTM_ATOM_AGC_INT_TRIG_INT_TRIG7_LEN (2u)

/** \brief  Mask for Ifx_GTM_ATOM_AGC_INT_TRIG_Bits.INT_TRIG7 */
#define IFX_GTM_ATOM_AGC_INT_TRIG_INT_TRIG7_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_ATOM_AGC_INT_TRIG_Bits.INT_TRIG7 */
#define IFX_GTM_ATOM_AGC_INT_TRIG_INT_TRIG7_OFF (14u)

/** \brief  Length for Ifx_GTM_ATOM_AGC_OUTEN_CTRL_Bits.OUTEN_CTRL0 */
#define IFX_GTM_ATOM_AGC_OUTEN_CTRL_OUTEN_CTRL0_LEN (2u)

/** \brief  Mask for Ifx_GTM_ATOM_AGC_OUTEN_CTRL_Bits.OUTEN_CTRL0 */
#define IFX_GTM_ATOM_AGC_OUTEN_CTRL_OUTEN_CTRL0_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_ATOM_AGC_OUTEN_CTRL_Bits.OUTEN_CTRL0 */
#define IFX_GTM_ATOM_AGC_OUTEN_CTRL_OUTEN_CTRL0_OFF (0u)

/** \brief  Length for Ifx_GTM_ATOM_AGC_OUTEN_CTRL_Bits.OUTEN_CTRL1 */
#define IFX_GTM_ATOM_AGC_OUTEN_CTRL_OUTEN_CTRL1_LEN (2u)

/** \brief  Mask for Ifx_GTM_ATOM_AGC_OUTEN_CTRL_Bits.OUTEN_CTRL1 */
#define IFX_GTM_ATOM_AGC_OUTEN_CTRL_OUTEN_CTRL1_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_ATOM_AGC_OUTEN_CTRL_Bits.OUTEN_CTRL1 */
#define IFX_GTM_ATOM_AGC_OUTEN_CTRL_OUTEN_CTRL1_OFF (2u)

/** \brief  Length for Ifx_GTM_ATOM_AGC_OUTEN_CTRL_Bits.OUTEN_CTRL2 */
#define IFX_GTM_ATOM_AGC_OUTEN_CTRL_OUTEN_CTRL2_LEN (2u)

/** \brief  Mask for Ifx_GTM_ATOM_AGC_OUTEN_CTRL_Bits.OUTEN_CTRL2 */
#define IFX_GTM_ATOM_AGC_OUTEN_CTRL_OUTEN_CTRL2_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_ATOM_AGC_OUTEN_CTRL_Bits.OUTEN_CTRL2 */
#define IFX_GTM_ATOM_AGC_OUTEN_CTRL_OUTEN_CTRL2_OFF (4u)

/** \brief  Length for Ifx_GTM_ATOM_AGC_OUTEN_CTRL_Bits.OUTEN_CTRL3 */
#define IFX_GTM_ATOM_AGC_OUTEN_CTRL_OUTEN_CTRL3_LEN (2u)

/** \brief  Mask for Ifx_GTM_ATOM_AGC_OUTEN_CTRL_Bits.OUTEN_CTRL3 */
#define IFX_GTM_ATOM_AGC_OUTEN_CTRL_OUTEN_CTRL3_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_ATOM_AGC_OUTEN_CTRL_Bits.OUTEN_CTRL3 */
#define IFX_GTM_ATOM_AGC_OUTEN_CTRL_OUTEN_CTRL3_OFF (6u)

/** \brief  Length for Ifx_GTM_ATOM_AGC_OUTEN_CTRL_Bits.OUTEN_CTRL4 */
#define IFX_GTM_ATOM_AGC_OUTEN_CTRL_OUTEN_CTRL4_LEN (2u)

/** \brief  Mask for Ifx_GTM_ATOM_AGC_OUTEN_CTRL_Bits.OUTEN_CTRL4 */
#define IFX_GTM_ATOM_AGC_OUTEN_CTRL_OUTEN_CTRL4_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_ATOM_AGC_OUTEN_CTRL_Bits.OUTEN_CTRL4 */
#define IFX_GTM_ATOM_AGC_OUTEN_CTRL_OUTEN_CTRL4_OFF (8u)

/** \brief  Length for Ifx_GTM_ATOM_AGC_OUTEN_CTRL_Bits.OUTEN_CTRL5 */
#define IFX_GTM_ATOM_AGC_OUTEN_CTRL_OUTEN_CTRL5_LEN (2u)

/** \brief  Mask for Ifx_GTM_ATOM_AGC_OUTEN_CTRL_Bits.OUTEN_CTRL5 */
#define IFX_GTM_ATOM_AGC_OUTEN_CTRL_OUTEN_CTRL5_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_ATOM_AGC_OUTEN_CTRL_Bits.OUTEN_CTRL5 */
#define IFX_GTM_ATOM_AGC_OUTEN_CTRL_OUTEN_CTRL5_OFF (10u)

/** \brief  Length for Ifx_GTM_ATOM_AGC_OUTEN_CTRL_Bits.OUTEN_CTRL6 */
#define IFX_GTM_ATOM_AGC_OUTEN_CTRL_OUTEN_CTRL6_LEN (2u)

/** \brief  Mask for Ifx_GTM_ATOM_AGC_OUTEN_CTRL_Bits.OUTEN_CTRL6 */
#define IFX_GTM_ATOM_AGC_OUTEN_CTRL_OUTEN_CTRL6_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_ATOM_AGC_OUTEN_CTRL_Bits.OUTEN_CTRL6 */
#define IFX_GTM_ATOM_AGC_OUTEN_CTRL_OUTEN_CTRL6_OFF (12u)

/** \brief  Length for Ifx_GTM_ATOM_AGC_OUTEN_CTRL_Bits.OUTEN_CTRL7 */
#define IFX_GTM_ATOM_AGC_OUTEN_CTRL_OUTEN_CTRL7_LEN (2u)

/** \brief  Mask for Ifx_GTM_ATOM_AGC_OUTEN_CTRL_Bits.OUTEN_CTRL7 */
#define IFX_GTM_ATOM_AGC_OUTEN_CTRL_OUTEN_CTRL7_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_ATOM_AGC_OUTEN_CTRL_Bits.OUTEN_CTRL7 */
#define IFX_GTM_ATOM_AGC_OUTEN_CTRL_OUTEN_CTRL7_OFF (14u)

/** \brief  Length for Ifx_GTM_ATOM_AGC_OUTEN_STAT_Bits.OUTEN_STAT0 */
#define IFX_GTM_ATOM_AGC_OUTEN_STAT_OUTEN_STAT0_LEN (2u)

/** \brief  Mask for Ifx_GTM_ATOM_AGC_OUTEN_STAT_Bits.OUTEN_STAT0 */
#define IFX_GTM_ATOM_AGC_OUTEN_STAT_OUTEN_STAT0_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_ATOM_AGC_OUTEN_STAT_Bits.OUTEN_STAT0 */
#define IFX_GTM_ATOM_AGC_OUTEN_STAT_OUTEN_STAT0_OFF (0u)

/** \brief  Length for Ifx_GTM_ATOM_AGC_OUTEN_STAT_Bits.OUTEN_STAT1 */
#define IFX_GTM_ATOM_AGC_OUTEN_STAT_OUTEN_STAT1_LEN (2u)

/** \brief  Mask for Ifx_GTM_ATOM_AGC_OUTEN_STAT_Bits.OUTEN_STAT1 */
#define IFX_GTM_ATOM_AGC_OUTEN_STAT_OUTEN_STAT1_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_ATOM_AGC_OUTEN_STAT_Bits.OUTEN_STAT1 */
#define IFX_GTM_ATOM_AGC_OUTEN_STAT_OUTEN_STAT1_OFF (2u)

/** \brief  Length for Ifx_GTM_ATOM_AGC_OUTEN_STAT_Bits.OUTEN_STAT2 */
#define IFX_GTM_ATOM_AGC_OUTEN_STAT_OUTEN_STAT2_LEN (2u)

/** \brief  Mask for Ifx_GTM_ATOM_AGC_OUTEN_STAT_Bits.OUTEN_STAT2 */
#define IFX_GTM_ATOM_AGC_OUTEN_STAT_OUTEN_STAT2_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_ATOM_AGC_OUTEN_STAT_Bits.OUTEN_STAT2 */
#define IFX_GTM_ATOM_AGC_OUTEN_STAT_OUTEN_STAT2_OFF (4u)

/** \brief  Length for Ifx_GTM_ATOM_AGC_OUTEN_STAT_Bits.OUTEN_STAT3 */
#define IFX_GTM_ATOM_AGC_OUTEN_STAT_OUTEN_STAT3_LEN (2u)

/** \brief  Mask for Ifx_GTM_ATOM_AGC_OUTEN_STAT_Bits.OUTEN_STAT3 */
#define IFX_GTM_ATOM_AGC_OUTEN_STAT_OUTEN_STAT3_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_ATOM_AGC_OUTEN_STAT_Bits.OUTEN_STAT3 */
#define IFX_GTM_ATOM_AGC_OUTEN_STAT_OUTEN_STAT3_OFF (6u)

/** \brief  Length for Ifx_GTM_ATOM_AGC_OUTEN_STAT_Bits.OUTEN_STAT4 */
#define IFX_GTM_ATOM_AGC_OUTEN_STAT_OUTEN_STAT4_LEN (2u)

/** \brief  Mask for Ifx_GTM_ATOM_AGC_OUTEN_STAT_Bits.OUTEN_STAT4 */
#define IFX_GTM_ATOM_AGC_OUTEN_STAT_OUTEN_STAT4_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_ATOM_AGC_OUTEN_STAT_Bits.OUTEN_STAT4 */
#define IFX_GTM_ATOM_AGC_OUTEN_STAT_OUTEN_STAT4_OFF (8u)

/** \brief  Length for Ifx_GTM_ATOM_AGC_OUTEN_STAT_Bits.OUTEN_STAT5 */
#define IFX_GTM_ATOM_AGC_OUTEN_STAT_OUTEN_STAT5_LEN (2u)

/** \brief  Mask for Ifx_GTM_ATOM_AGC_OUTEN_STAT_Bits.OUTEN_STAT5 */
#define IFX_GTM_ATOM_AGC_OUTEN_STAT_OUTEN_STAT5_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_ATOM_AGC_OUTEN_STAT_Bits.OUTEN_STAT5 */
#define IFX_GTM_ATOM_AGC_OUTEN_STAT_OUTEN_STAT5_OFF (10u)

/** \brief  Length for Ifx_GTM_ATOM_AGC_OUTEN_STAT_Bits.OUTEN_STAT6 */
#define IFX_GTM_ATOM_AGC_OUTEN_STAT_OUTEN_STAT6_LEN (2u)

/** \brief  Mask for Ifx_GTM_ATOM_AGC_OUTEN_STAT_Bits.OUTEN_STAT6 */
#define IFX_GTM_ATOM_AGC_OUTEN_STAT_OUTEN_STAT6_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_ATOM_AGC_OUTEN_STAT_Bits.OUTEN_STAT6 */
#define IFX_GTM_ATOM_AGC_OUTEN_STAT_OUTEN_STAT6_OFF (12u)

/** \brief  Length for Ifx_GTM_ATOM_AGC_OUTEN_STAT_Bits.OUTEN_STAT7 */
#define IFX_GTM_ATOM_AGC_OUTEN_STAT_OUTEN_STAT7_LEN (2u)

/** \brief  Mask for Ifx_GTM_ATOM_AGC_OUTEN_STAT_Bits.OUTEN_STAT7 */
#define IFX_GTM_ATOM_AGC_OUTEN_STAT_OUTEN_STAT7_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_ATOM_AGC_OUTEN_STAT_Bits.OUTEN_STAT7 */
#define IFX_GTM_ATOM_AGC_OUTEN_STAT_OUTEN_STAT7_OFF (14u)

/** \brief  Length for Ifx_GTM_ATOM_CH_CM0_Bits.CM0 */
#define IFX_GTM_ATOM_CH_CM0_CM0_LEN (24u)

/** \brief  Mask for Ifx_GTM_ATOM_CH_CM0_Bits.CM0 */
#define IFX_GTM_ATOM_CH_CM0_CM0_MSK (0xffffffu)

/** \brief  Offset for Ifx_GTM_ATOM_CH_CM0_Bits.CM0 */
#define IFX_GTM_ATOM_CH_CM0_CM0_OFF (0u)

/** \brief  Length for Ifx_GTM_ATOM_CH_CM1_Bits.CM1 */
#define IFX_GTM_ATOM_CH_CM1_CM1_LEN (24u)

/** \brief  Mask for Ifx_GTM_ATOM_CH_CM1_Bits.CM1 */
#define IFX_GTM_ATOM_CH_CM1_CM1_MSK (0xffffffu)

/** \brief  Offset for Ifx_GTM_ATOM_CH_CM1_Bits.CM1 */
#define IFX_GTM_ATOM_CH_CM1_CM1_OFF (0u)

/** \brief  Length for Ifx_GTM_ATOM_CH_CN0_Bits.CN0 */
#define IFX_GTM_ATOM_CH_CN0_CN0_LEN (24u)

/** \brief  Mask for Ifx_GTM_ATOM_CH_CN0_Bits.CN0 */
#define IFX_GTM_ATOM_CH_CN0_CN0_MSK (0xffffffu)

/** \brief  Offset for Ifx_GTM_ATOM_CH_CN0_Bits.CN0 */
#define IFX_GTM_ATOM_CH_CN0_CN0_OFF (0u)

/** \brief  Length for Ifx_GTM_ATOM_CH_CTRL_Bits.ABM */
#define IFX_GTM_ATOM_CH_CTRL_ABM_LEN (1u)

/** \brief  Mask for Ifx_GTM_ATOM_CH_CTRL_Bits.ABM */
#define IFX_GTM_ATOM_CH_CTRL_ABM_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ATOM_CH_CTRL_Bits.ABM */
#define IFX_GTM_ATOM_CH_CTRL_ABM_OFF (27u)

/** \brief  Length for Ifx_GTM_ATOM_CH_CTRL_Bits.ACB */
#define IFX_GTM_ATOM_CH_CTRL_ACB_LEN (5u)

/** \brief  Mask for Ifx_GTM_ATOM_CH_CTRL_Bits.ACB */
#define IFX_GTM_ATOM_CH_CTRL_ACB_MSK (0x1fu)

/** \brief  Offset for Ifx_GTM_ATOM_CH_CTRL_Bits.ACB */
#define IFX_GTM_ATOM_CH_CTRL_ACB_OFF (4u)

/** \brief  Length for Ifx_GTM_ATOM_CH_CTRL_Bits.ARU_EN */
#define IFX_GTM_ATOM_CH_CTRL_ARU_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_ATOM_CH_CTRL_Bits.ARU_EN */
#define IFX_GTM_ATOM_CH_CTRL_ARU_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ATOM_CH_CTRL_Bits.ARU_EN */
#define IFX_GTM_ATOM_CH_CTRL_ARU_EN_OFF (3u)

/** \brief  Length for Ifx_GTM_ATOM_CH_CTRL_Bits.CLK_SRC */
#define IFX_GTM_ATOM_CH_CTRL_CLK_SRC_LEN (3u)

/** \brief  Mask for Ifx_GTM_ATOM_CH_CTRL_Bits.CLK_SRC */
#define IFX_GTM_ATOM_CH_CTRL_CLK_SRC_MSK (0x7u)

/** \brief  Offset for Ifx_GTM_ATOM_CH_CTRL_Bits.CLK_SRC */
#define IFX_GTM_ATOM_CH_CTRL_CLK_SRC_OFF (12u)

/** \brief  Length for Ifx_GTM_ATOM_CH_CTRL_Bits.CMP_CTRL */
#define IFX_GTM_ATOM_CH_CTRL_CMP_CTRL_LEN (1u)

/** \brief  Mask for Ifx_GTM_ATOM_CH_CTRL_Bits.CMP_CTRL */
#define IFX_GTM_ATOM_CH_CTRL_CMP_CTRL_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ATOM_CH_CTRL_Bits.CMP_CTRL */
#define IFX_GTM_ATOM_CH_CTRL_CMP_CTRL_OFF (9u)

/** \brief  Length for Ifx_GTM_ATOM_CH_CTRL_Bits.MODE */
#define IFX_GTM_ATOM_CH_CTRL_MODE_LEN (2u)

/** \brief  Mask for Ifx_GTM_ATOM_CH_CTRL_Bits.MODE */
#define IFX_GTM_ATOM_CH_CTRL_MODE_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_ATOM_CH_CTRL_Bits.MODE */
#define IFX_GTM_ATOM_CH_CTRL_MODE_OFF (0u)

/** \brief  Length for Ifx_GTM_ATOM_CH_CTRL_Bits.OSM */
#define IFX_GTM_ATOM_CH_CTRL_OSM_LEN (1u)

/** \brief  Mask for Ifx_GTM_ATOM_CH_CTRL_Bits.OSM */
#define IFX_GTM_ATOM_CH_CTRL_OSM_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ATOM_CH_CTRL_Bits.OSM */
#define IFX_GTM_ATOM_CH_CTRL_OSM_OFF (26u)

/** \brief  Length for Ifx_GTM_ATOM_CH_CTRL_Bits.RST_CCU0 */
#define IFX_GTM_ATOM_CH_CTRL_RST_CCU0_LEN (1u)

/** \brief  Mask for Ifx_GTM_ATOM_CH_CTRL_Bits.RST_CCU0 */
#define IFX_GTM_ATOM_CH_CTRL_RST_CCU0_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ATOM_CH_CTRL_Bits.RST_CCU0 */
#define IFX_GTM_ATOM_CH_CTRL_RST_CCU0_OFF (20u)

/** \brief  Length for Ifx_GTM_ATOM_CH_CTRL_Bits.SL */
#define IFX_GTM_ATOM_CH_CTRL_SL_LEN (1u)

/** \brief  Mask for Ifx_GTM_ATOM_CH_CTRL_Bits.SL */
#define IFX_GTM_ATOM_CH_CTRL_SL_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ATOM_CH_CTRL_Bits.SL */
#define IFX_GTM_ATOM_CH_CTRL_SL_OFF (11u)

/** \brief  Length for Ifx_GTM_ATOM_CH_CTRL_Bits.SLA */
#define IFX_GTM_ATOM_CH_CTRL_SLA_LEN (1u)

/** \brief  Mask for Ifx_GTM_ATOM_CH_CTRL_Bits.SLA */
#define IFX_GTM_ATOM_CH_CTRL_SLA_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ATOM_CH_CTRL_Bits.SLA */
#define IFX_GTM_ATOM_CH_CTRL_SLA_OFF (25u)

/** \brief  Length for Ifx_GTM_ATOM_CH_CTRL_Bits.TB12_SEL */
#define IFX_GTM_ATOM_CH_CTRL_TB12_SEL_LEN (1u)

/** \brief  Mask for Ifx_GTM_ATOM_CH_CTRL_Bits.TB12_SEL */
#define IFX_GTM_ATOM_CH_CTRL_TB12_SEL_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ATOM_CH_CTRL_Bits.TB12_SEL */
#define IFX_GTM_ATOM_CH_CTRL_TB12_SEL_OFF (2u)

/** \brief  Length for Ifx_GTM_ATOM_CH_CTRL_Bits.TRIGOUT */
#define IFX_GTM_ATOM_CH_CTRL_TRIGOUT_LEN (1u)

/** \brief  Mask for Ifx_GTM_ATOM_CH_CTRL_Bits.TRIGOUT */
#define IFX_GTM_ATOM_CH_CTRL_TRIGOUT_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ATOM_CH_CTRL_Bits.TRIGOUT */
#define IFX_GTM_ATOM_CH_CTRL_TRIGOUT_OFF (24u)

/** \brief  Length for Ifx_GTM_ATOM_CH_CTRL_Bits.WR_REQ */
#define IFX_GTM_ATOM_CH_CTRL_WR_REQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ATOM_CH_CTRL_Bits.WR_REQ */
#define IFX_GTM_ATOM_CH_CTRL_WR_REQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ATOM_CH_CTRL_Bits.WR_REQ */
#define IFX_GTM_ATOM_CH_CTRL_WR_REQ_OFF (16u)

/** \brief  Length for Ifx_GTM_ATOM_CH_IRQ_EN_Bits.CCU0TC_IRQ_EN */
#define IFX_GTM_ATOM_CH_IRQ_EN_CCU0TC_IRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_ATOM_CH_IRQ_EN_Bits.CCU0TC_IRQ_EN */
#define IFX_GTM_ATOM_CH_IRQ_EN_CCU0TC_IRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ATOM_CH_IRQ_EN_Bits.CCU0TC_IRQ_EN */
#define IFX_GTM_ATOM_CH_IRQ_EN_CCU0TC_IRQ_EN_OFF (0u)

/** \brief  Length for Ifx_GTM_ATOM_CH_IRQ_EN_Bits.CCU1TC_IRQ_EN */
#define IFX_GTM_ATOM_CH_IRQ_EN_CCU1TC_IRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_ATOM_CH_IRQ_EN_Bits.CCU1TC_IRQ_EN */
#define IFX_GTM_ATOM_CH_IRQ_EN_CCU1TC_IRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ATOM_CH_IRQ_EN_Bits.CCU1TC_IRQ_EN */
#define IFX_GTM_ATOM_CH_IRQ_EN_CCU1TC_IRQ_EN_OFF (1u)

/** \brief  Length for Ifx_GTM_ATOM_CH_IRQ_FORCINT_Bits.TRG_CCU0TC */
#define IFX_GTM_ATOM_CH_IRQ_FORCINT_TRG_CCU0TC_LEN (1u)

/** \brief  Mask for Ifx_GTM_ATOM_CH_IRQ_FORCINT_Bits.TRG_CCU0TC */
#define IFX_GTM_ATOM_CH_IRQ_FORCINT_TRG_CCU0TC_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ATOM_CH_IRQ_FORCINT_Bits.TRG_CCU0TC */
#define IFX_GTM_ATOM_CH_IRQ_FORCINT_TRG_CCU0TC_OFF (0u)

/** \brief  Length for Ifx_GTM_ATOM_CH_IRQ_FORCINT_Bits.TRG_CCU1TC */
#define IFX_GTM_ATOM_CH_IRQ_FORCINT_TRG_CCU1TC_LEN (1u)

/** \brief  Mask for Ifx_GTM_ATOM_CH_IRQ_FORCINT_Bits.TRG_CCU1TC */
#define IFX_GTM_ATOM_CH_IRQ_FORCINT_TRG_CCU1TC_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ATOM_CH_IRQ_FORCINT_Bits.TRG_CCU1TC */
#define IFX_GTM_ATOM_CH_IRQ_FORCINT_TRG_CCU1TC_OFF (1u)

/** \brief  Length for Ifx_GTM_ATOM_CH_IRQ_MODE_Bits.IRQ_MODE */
#define IFX_GTM_ATOM_CH_IRQ_MODE_IRQ_MODE_LEN (2u)

/** \brief  Mask for Ifx_GTM_ATOM_CH_IRQ_MODE_Bits.IRQ_MODE */
#define IFX_GTM_ATOM_CH_IRQ_MODE_IRQ_MODE_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_ATOM_CH_IRQ_MODE_Bits.IRQ_MODE */
#define IFX_GTM_ATOM_CH_IRQ_MODE_IRQ_MODE_OFF (0u)

/** \brief  Length for Ifx_GTM_ATOM_CH_IRQ_NOTIFY_Bits.CCU0TC */
#define IFX_GTM_ATOM_CH_IRQ_NOTIFY_CCU0TC_LEN (1u)

/** \brief  Mask for Ifx_GTM_ATOM_CH_IRQ_NOTIFY_Bits.CCU0TC */
#define IFX_GTM_ATOM_CH_IRQ_NOTIFY_CCU0TC_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ATOM_CH_IRQ_NOTIFY_Bits.CCU0TC */
#define IFX_GTM_ATOM_CH_IRQ_NOTIFY_CCU0TC_OFF (0u)

/** \brief  Length for Ifx_GTM_ATOM_CH_IRQ_NOTIFY_Bits.CCU1TC */
#define IFX_GTM_ATOM_CH_IRQ_NOTIFY_CCU1TC_LEN (1u)

/** \brief  Mask for Ifx_GTM_ATOM_CH_IRQ_NOTIFY_Bits.CCU1TC */
#define IFX_GTM_ATOM_CH_IRQ_NOTIFY_CCU1TC_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ATOM_CH_IRQ_NOTIFY_Bits.CCU1TC */
#define IFX_GTM_ATOM_CH_IRQ_NOTIFY_CCU1TC_OFF (1u)

/** \brief  Length for Ifx_GTM_ATOM_CH_RDADDR_Bits.RDADDR0 */
#define IFX_GTM_ATOM_CH_RDADDR_RDADDR0_LEN (9u)

/** \brief  Mask for Ifx_GTM_ATOM_CH_RDADDR_Bits.RDADDR0 */
#define IFX_GTM_ATOM_CH_RDADDR_RDADDR0_MSK (0x1ffu)

/** \brief  Offset for Ifx_GTM_ATOM_CH_RDADDR_Bits.RDADDR0 */
#define IFX_GTM_ATOM_CH_RDADDR_RDADDR0_OFF (0u)

/** \brief  Length for Ifx_GTM_ATOM_CH_RDADDR_Bits.RDADDR1 */
#define IFX_GTM_ATOM_CH_RDADDR_RDADDR1_LEN (9u)

/** \brief  Mask for Ifx_GTM_ATOM_CH_RDADDR_Bits.RDADDR1 */
#define IFX_GTM_ATOM_CH_RDADDR_RDADDR1_MSK (0x1ffu)

/** \brief  Offset for Ifx_GTM_ATOM_CH_RDADDR_Bits.RDADDR1 */
#define IFX_GTM_ATOM_CH_RDADDR_RDADDR1_OFF (16u)

/** \brief  Length for Ifx_GTM_ATOM_CH_SOMC_Bits.ABM */
#define IFX_GTM_ATOM_CH_SOMC_ABM_LEN (1u)

/** \brief  Mask for Ifx_GTM_ATOM_CH_SOMC_Bits.ABM */
#define IFX_GTM_ATOM_CH_SOMC_ABM_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ATOM_CH_SOMC_Bits.ABM */
#define IFX_GTM_ATOM_CH_SOMC_ABM_OFF (27u)

/** \brief  Length for Ifx_GTM_ATOM_CH_SOMC_Bits.ACB10 */
#define IFX_GTM_ATOM_CH_SOMC_ACB10_LEN (2u)

/** \brief  Mask for Ifx_GTM_ATOM_CH_SOMC_Bits.ACB10 */
#define IFX_GTM_ATOM_CH_SOMC_ACB10_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_ATOM_CH_SOMC_Bits.ACB10 */
#define IFX_GTM_ATOM_CH_SOMC_ACB10_OFF (4u)

/** \brief  Length for Ifx_GTM_ATOM_CH_SOMC_Bits.ACB42 */
#define IFX_GTM_ATOM_CH_SOMC_ACB42_LEN (3u)

/** \brief  Mask for Ifx_GTM_ATOM_CH_SOMC_Bits.ACB42 */
#define IFX_GTM_ATOM_CH_SOMC_ACB42_MSK (0x7u)

/** \brief  Offset for Ifx_GTM_ATOM_CH_SOMC_Bits.ACB42 */
#define IFX_GTM_ATOM_CH_SOMC_ACB42_OFF (6u)

/** \brief  Length for Ifx_GTM_ATOM_CH_SOMC_Bits.ARU_EN */
#define IFX_GTM_ATOM_CH_SOMC_ARU_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_ATOM_CH_SOMC_Bits.ARU_EN */
#define IFX_GTM_ATOM_CH_SOMC_ARU_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ATOM_CH_SOMC_Bits.ARU_EN */
#define IFX_GTM_ATOM_CH_SOMC_ARU_EN_OFF (3u)

/** \brief  Length for Ifx_GTM_ATOM_CH_SOMC_Bits.CMP_CTRL */
#define IFX_GTM_ATOM_CH_SOMC_CMP_CTRL_LEN (1u)

/** \brief  Mask for Ifx_GTM_ATOM_CH_SOMC_Bits.CMP_CTRL */
#define IFX_GTM_ATOM_CH_SOMC_CMP_CTRL_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ATOM_CH_SOMC_Bits.CMP_CTRL */
#define IFX_GTM_ATOM_CH_SOMC_CMP_CTRL_OFF (9u)

/** \brief  Length for Ifx_GTM_ATOM_CH_SOMC_Bits.MODE */
#define IFX_GTM_ATOM_CH_SOMC_MODE_LEN (2u)

/** \brief  Mask for Ifx_GTM_ATOM_CH_SOMC_Bits.MODE */
#define IFX_GTM_ATOM_CH_SOMC_MODE_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_ATOM_CH_SOMC_Bits.MODE */
#define IFX_GTM_ATOM_CH_SOMC_MODE_OFF (0u)

/** \brief  Length for Ifx_GTM_ATOM_CH_SOMC_Bits.SL */
#define IFX_GTM_ATOM_CH_SOMC_SL_LEN (1u)

/** \brief  Mask for Ifx_GTM_ATOM_CH_SOMC_Bits.SL */
#define IFX_GTM_ATOM_CH_SOMC_SL_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ATOM_CH_SOMC_Bits.SL */
#define IFX_GTM_ATOM_CH_SOMC_SL_OFF (11u)

/** \brief  Length for Ifx_GTM_ATOM_CH_SOMC_Bits.SLA */
#define IFX_GTM_ATOM_CH_SOMC_SLA_LEN (1u)

/** \brief  Mask for Ifx_GTM_ATOM_CH_SOMC_Bits.SLA */
#define IFX_GTM_ATOM_CH_SOMC_SLA_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ATOM_CH_SOMC_Bits.SLA */
#define IFX_GTM_ATOM_CH_SOMC_SLA_OFF (25u)

/** \brief  Length for Ifx_GTM_ATOM_CH_SOMC_Bits.TB12_SEL */
#define IFX_GTM_ATOM_CH_SOMC_TB12_SEL_LEN (1u)

/** \brief  Mask for Ifx_GTM_ATOM_CH_SOMC_Bits.TB12_SEL */
#define IFX_GTM_ATOM_CH_SOMC_TB12_SEL_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ATOM_CH_SOMC_Bits.TB12_SEL */
#define IFX_GTM_ATOM_CH_SOMC_TB12_SEL_OFF (2u)

/** \brief  Length for Ifx_GTM_ATOM_CH_SOMC_Bits.TRIGOUT */
#define IFX_GTM_ATOM_CH_SOMC_TRIGOUT_LEN (1u)

/** \brief  Mask for Ifx_GTM_ATOM_CH_SOMC_Bits.TRIGOUT */
#define IFX_GTM_ATOM_CH_SOMC_TRIGOUT_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ATOM_CH_SOMC_Bits.TRIGOUT */
#define IFX_GTM_ATOM_CH_SOMC_TRIGOUT_OFF (24u)

/** \brief  Length for Ifx_GTM_ATOM_CH_SOMC_Bits.WR_REQ */
#define IFX_GTM_ATOM_CH_SOMC_WR_REQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ATOM_CH_SOMC_Bits.WR_REQ */
#define IFX_GTM_ATOM_CH_SOMC_WR_REQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ATOM_CH_SOMC_Bits.WR_REQ */
#define IFX_GTM_ATOM_CH_SOMC_WR_REQ_OFF (16u)

/** \brief  Length for Ifx_GTM_ATOM_CH_SOMI_Bits.ACB0 */
#define IFX_GTM_ATOM_CH_SOMI_ACB0_LEN (1u)

/** \brief  Mask for Ifx_GTM_ATOM_CH_SOMI_Bits.ACB0 */
#define IFX_GTM_ATOM_CH_SOMI_ACB0_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ATOM_CH_SOMI_Bits.ACB0 */
#define IFX_GTM_ATOM_CH_SOMI_ACB0_OFF (4u)

/** \brief  Length for Ifx_GTM_ATOM_CH_SOMI_Bits.ARU_EN */
#define IFX_GTM_ATOM_CH_SOMI_ARU_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_ATOM_CH_SOMI_Bits.ARU_EN */
#define IFX_GTM_ATOM_CH_SOMI_ARU_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ATOM_CH_SOMI_Bits.ARU_EN */
#define IFX_GTM_ATOM_CH_SOMI_ARU_EN_OFF (3u)

/** \brief  Length for Ifx_GTM_ATOM_CH_SOMI_Bits.MODE */
#define IFX_GTM_ATOM_CH_SOMI_MODE_LEN (2u)

/** \brief  Mask for Ifx_GTM_ATOM_CH_SOMI_Bits.MODE */
#define IFX_GTM_ATOM_CH_SOMI_MODE_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_ATOM_CH_SOMI_Bits.MODE */
#define IFX_GTM_ATOM_CH_SOMI_MODE_OFF (0u)

/** \brief  Length for Ifx_GTM_ATOM_CH_SOMI_Bits.SL */
#define IFX_GTM_ATOM_CH_SOMI_SL_LEN (1u)

/** \brief  Mask for Ifx_GTM_ATOM_CH_SOMI_Bits.SL */
#define IFX_GTM_ATOM_CH_SOMI_SL_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ATOM_CH_SOMI_Bits.SL */
#define IFX_GTM_ATOM_CH_SOMI_SL_OFF (11u)

/** \brief  Length for Ifx_GTM_ATOM_CH_SOMP_Bits.ADL */
#define IFX_GTM_ATOM_CH_SOMP_ADL_LEN (2u)

/** \brief  Mask for Ifx_GTM_ATOM_CH_SOMP_Bits.ADL */
#define IFX_GTM_ATOM_CH_SOMP_ADL_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_ATOM_CH_SOMP_Bits.ADL */
#define IFX_GTM_ATOM_CH_SOMP_ADL_OFF (4u)

/** \brief  Length for Ifx_GTM_ATOM_CH_SOMP_Bits.ARU_EN */
#define IFX_GTM_ATOM_CH_SOMP_ARU_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_ATOM_CH_SOMP_Bits.ARU_EN */
#define IFX_GTM_ATOM_CH_SOMP_ARU_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ATOM_CH_SOMP_Bits.ARU_EN */
#define IFX_GTM_ATOM_CH_SOMP_ARU_EN_OFF (3u)

/** \brief  Length for Ifx_GTM_ATOM_CH_SOMP_Bits.CLK_SRC_SR */
#define IFX_GTM_ATOM_CH_SOMP_CLK_SRC_SR_LEN (3u)

/** \brief  Mask for Ifx_GTM_ATOM_CH_SOMP_Bits.CLK_SRC_SR */
#define IFX_GTM_ATOM_CH_SOMP_CLK_SRC_SR_MSK (0x7u)

/** \brief  Offset for Ifx_GTM_ATOM_CH_SOMP_Bits.CLK_SRC_SR */
#define IFX_GTM_ATOM_CH_SOMP_CLK_SRC_SR_OFF (12u)

/** \brief  Length for Ifx_GTM_ATOM_CH_SOMP_Bits.MODE */
#define IFX_GTM_ATOM_CH_SOMP_MODE_LEN (2u)

/** \brief  Mask for Ifx_GTM_ATOM_CH_SOMP_Bits.MODE */
#define IFX_GTM_ATOM_CH_SOMP_MODE_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_ATOM_CH_SOMP_Bits.MODE */
#define IFX_GTM_ATOM_CH_SOMP_MODE_OFF (0u)

/** \brief  Length for Ifx_GTM_ATOM_CH_SOMP_Bits.OSM */
#define IFX_GTM_ATOM_CH_SOMP_OSM_LEN (1u)

/** \brief  Mask for Ifx_GTM_ATOM_CH_SOMP_Bits.OSM */
#define IFX_GTM_ATOM_CH_SOMP_OSM_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ATOM_CH_SOMP_Bits.OSM */
#define IFX_GTM_ATOM_CH_SOMP_OSM_OFF (26u)

/** \brief  Length for Ifx_GTM_ATOM_CH_SOMP_Bits.RST_CCU0 */
#define IFX_GTM_ATOM_CH_SOMP_RST_CCU0_LEN (1u)

/** \brief  Mask for Ifx_GTM_ATOM_CH_SOMP_Bits.RST_CCU0 */
#define IFX_GTM_ATOM_CH_SOMP_RST_CCU0_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ATOM_CH_SOMP_Bits.RST_CCU0 */
#define IFX_GTM_ATOM_CH_SOMP_RST_CCU0_OFF (20u)

/** \brief  Length for Ifx_GTM_ATOM_CH_SOMP_Bits.SL */
#define IFX_GTM_ATOM_CH_SOMP_SL_LEN (1u)

/** \brief  Mask for Ifx_GTM_ATOM_CH_SOMP_Bits.SL */
#define IFX_GTM_ATOM_CH_SOMP_SL_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ATOM_CH_SOMP_Bits.SL */
#define IFX_GTM_ATOM_CH_SOMP_SL_OFF (11u)

/** \brief  Length for Ifx_GTM_ATOM_CH_SOMP_Bits.TRIGOUT */
#define IFX_GTM_ATOM_CH_SOMP_TRIGOUT_LEN (1u)

/** \brief  Mask for Ifx_GTM_ATOM_CH_SOMP_Bits.TRIGOUT */
#define IFX_GTM_ATOM_CH_SOMP_TRIGOUT_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ATOM_CH_SOMP_Bits.TRIGOUT */
#define IFX_GTM_ATOM_CH_SOMP_TRIGOUT_OFF (24u)

/** \brief  Length for Ifx_GTM_ATOM_CH_SOMS_Bits.ACB0 */
#define IFX_GTM_ATOM_CH_SOMS_ACB0_LEN (1u)

/** \brief  Mask for Ifx_GTM_ATOM_CH_SOMS_Bits.ACB0 */
#define IFX_GTM_ATOM_CH_SOMS_ACB0_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ATOM_CH_SOMS_Bits.ACB0 */
#define IFX_GTM_ATOM_CH_SOMS_ACB0_OFF (4u)

/** \brief  Length for Ifx_GTM_ATOM_CH_SOMS_Bits.ARU_EN */
#define IFX_GTM_ATOM_CH_SOMS_ARU_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_ATOM_CH_SOMS_Bits.ARU_EN */
#define IFX_GTM_ATOM_CH_SOMS_ARU_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ATOM_CH_SOMS_Bits.ARU_EN */
#define IFX_GTM_ATOM_CH_SOMS_ARU_EN_OFF (3u)

/** \brief  Length for Ifx_GTM_ATOM_CH_SOMS_Bits.CLK_SRC */
#define IFX_GTM_ATOM_CH_SOMS_CLK_SRC_LEN (3u)

/** \brief  Mask for Ifx_GTM_ATOM_CH_SOMS_Bits.CLK_SRC */
#define IFX_GTM_ATOM_CH_SOMS_CLK_SRC_MSK (0x7u)

/** \brief  Offset for Ifx_GTM_ATOM_CH_SOMS_Bits.CLK_SRC */
#define IFX_GTM_ATOM_CH_SOMS_CLK_SRC_OFF (12u)

/** \brief  Length for Ifx_GTM_ATOM_CH_SOMS_Bits.MODE */
#define IFX_GTM_ATOM_CH_SOMS_MODE_LEN (2u)

/** \brief  Mask for Ifx_GTM_ATOM_CH_SOMS_Bits.MODE */
#define IFX_GTM_ATOM_CH_SOMS_MODE_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_ATOM_CH_SOMS_Bits.MODE */
#define IFX_GTM_ATOM_CH_SOMS_MODE_OFF (0u)

/** \brief  Length for Ifx_GTM_ATOM_CH_SOMS_Bits.OSM */
#define IFX_GTM_ATOM_CH_SOMS_OSM_LEN (1u)

/** \brief  Mask for Ifx_GTM_ATOM_CH_SOMS_Bits.OSM */
#define IFX_GTM_ATOM_CH_SOMS_OSM_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ATOM_CH_SOMS_Bits.OSM */
#define IFX_GTM_ATOM_CH_SOMS_OSM_OFF (26u)

/** \brief  Length for Ifx_GTM_ATOM_CH_SOMS_Bits.SL */
#define IFX_GTM_ATOM_CH_SOMS_SL_LEN (1u)

/** \brief  Mask for Ifx_GTM_ATOM_CH_SOMS_Bits.SL */
#define IFX_GTM_ATOM_CH_SOMS_SL_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ATOM_CH_SOMS_Bits.SL */
#define IFX_GTM_ATOM_CH_SOMS_SL_OFF (11u)

/** \brief  Length for Ifx_GTM_ATOM_CH_SR0_Bits.SR0 */
#define IFX_GTM_ATOM_CH_SR0_SR0_LEN (24u)

/** \brief  Mask for Ifx_GTM_ATOM_CH_SR0_Bits.SR0 */
#define IFX_GTM_ATOM_CH_SR0_SR0_MSK (0xffffffu)

/** \brief  Offset for Ifx_GTM_ATOM_CH_SR0_Bits.SR0 */
#define IFX_GTM_ATOM_CH_SR0_SR0_OFF (0u)

/** \brief  Length for Ifx_GTM_ATOM_CH_SR1_Bits.SR1 */
#define IFX_GTM_ATOM_CH_SR1_SR1_LEN (24u)

/** \brief  Mask for Ifx_GTM_ATOM_CH_SR1_Bits.SR1 */
#define IFX_GTM_ATOM_CH_SR1_SR1_MSK (0xffffffu)

/** \brief  Offset for Ifx_GTM_ATOM_CH_SR1_Bits.SR1 */
#define IFX_GTM_ATOM_CH_SR1_SR1_OFF (0u)

/** \brief  Length for Ifx_GTM_ATOM_CH_STAT_Bits.ACBI */
#define IFX_GTM_ATOM_CH_STAT_ACBI_LEN (5u)

/** \brief  Mask for Ifx_GTM_ATOM_CH_STAT_Bits.ACBI */
#define IFX_GTM_ATOM_CH_STAT_ACBI_MSK (0x1fu)

/** \brief  Offset for Ifx_GTM_ATOM_CH_STAT_Bits.ACBI */
#define IFX_GTM_ATOM_CH_STAT_ACBI_OFF (16u)

/** \brief  Length for Ifx_GTM_ATOM_CH_STAT_Bits.ACBO */
#define IFX_GTM_ATOM_CH_STAT_ACBO_LEN (5u)

/** \brief  Mask for Ifx_GTM_ATOM_CH_STAT_Bits.ACBO */
#define IFX_GTM_ATOM_CH_STAT_ACBO_MSK (0x1fu)

/** \brief  Offset for Ifx_GTM_ATOM_CH_STAT_Bits.ACBO */
#define IFX_GTM_ATOM_CH_STAT_ACBO_OFF (24u)

/** \brief  Length for Ifx_GTM_ATOM_CH_STAT_Bits.DV */
#define IFX_GTM_ATOM_CH_STAT_DV_LEN (1u)

/** \brief  Mask for Ifx_GTM_ATOM_CH_STAT_Bits.DV */
#define IFX_GTM_ATOM_CH_STAT_DV_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ATOM_CH_STAT_Bits.DV */
#define IFX_GTM_ATOM_CH_STAT_DV_OFF (21u)

/** \brief  Length for Ifx_GTM_ATOM_CH_STAT_Bits.OL */
#define IFX_GTM_ATOM_CH_STAT_OL_LEN (1u)

/** \brief  Mask for Ifx_GTM_ATOM_CH_STAT_Bits.OL */
#define IFX_GTM_ATOM_CH_STAT_OL_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ATOM_CH_STAT_Bits.OL */
#define IFX_GTM_ATOM_CH_STAT_OL_OFF (0u)

/** \brief  Length for Ifx_GTM_ATOM_CH_STAT_Bits.WRF */
#define IFX_GTM_ATOM_CH_STAT_WRF_LEN (1u)

/** \brief  Mask for Ifx_GTM_ATOM_CH_STAT_Bits.WRF */
#define IFX_GTM_ATOM_CH_STAT_WRF_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ATOM_CH_STAT_Bits.WRF */
#define IFX_GTM_ATOM_CH_STAT_WRF_OFF (22u)

/** \brief  Length for Ifx_GTM_BRC_EIRQ_EN_Bits.DEST_ERR_EN */
#define IFX_GTM_BRC_EIRQ_EN_DEST_ERR_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_EIRQ_EN_Bits.DEST_ERR_EN */
#define IFX_GTM_BRC_EIRQ_EN_DEST_ERR_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_EIRQ_EN_Bits.DEST_ERR_EN */
#define IFX_GTM_BRC_EIRQ_EN_DEST_ERR_EN_OFF (0u)

/** \brief  Length for Ifx_GTM_BRC_EIRQ_EN_Bits.DID_EN0 */
#define IFX_GTM_BRC_EIRQ_EN_DID_EN0_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_EIRQ_EN_Bits.DID_EN0 */
#define IFX_GTM_BRC_EIRQ_EN_DID_EN0_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_EIRQ_EN_Bits.DID_EN0 */
#define IFX_GTM_BRC_EIRQ_EN_DID_EN0_OFF (1u)

/** \brief  Length for Ifx_GTM_BRC_EIRQ_EN_Bits.DID_EN10 */
#define IFX_GTM_BRC_EIRQ_EN_DID_EN10_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_EIRQ_EN_Bits.DID_EN10 */
#define IFX_GTM_BRC_EIRQ_EN_DID_EN10_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_EIRQ_EN_Bits.DID_EN10 */
#define IFX_GTM_BRC_EIRQ_EN_DID_EN10_OFF (11u)

/** \brief  Length for Ifx_GTM_BRC_EIRQ_EN_Bits.DID_EN11 */
#define IFX_GTM_BRC_EIRQ_EN_DID_EN11_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_EIRQ_EN_Bits.DID_EN11 */
#define IFX_GTM_BRC_EIRQ_EN_DID_EN11_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_EIRQ_EN_Bits.DID_EN11 */
#define IFX_GTM_BRC_EIRQ_EN_DID_EN11_OFF (12u)

/** \brief  Length for Ifx_GTM_BRC_EIRQ_EN_Bits.DID_EN1 */
#define IFX_GTM_BRC_EIRQ_EN_DID_EN1_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_EIRQ_EN_Bits.DID_EN1 */
#define IFX_GTM_BRC_EIRQ_EN_DID_EN1_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_EIRQ_EN_Bits.DID_EN1 */
#define IFX_GTM_BRC_EIRQ_EN_DID_EN1_OFF (2u)

/** \brief  Length for Ifx_GTM_BRC_EIRQ_EN_Bits.DID_EN2 */
#define IFX_GTM_BRC_EIRQ_EN_DID_EN2_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_EIRQ_EN_Bits.DID_EN2 */
#define IFX_GTM_BRC_EIRQ_EN_DID_EN2_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_EIRQ_EN_Bits.DID_EN2 */
#define IFX_GTM_BRC_EIRQ_EN_DID_EN2_OFF (3u)

/** \brief  Length for Ifx_GTM_BRC_EIRQ_EN_Bits.DID_EN3 */
#define IFX_GTM_BRC_EIRQ_EN_DID_EN3_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_EIRQ_EN_Bits.DID_EN3 */
#define IFX_GTM_BRC_EIRQ_EN_DID_EN3_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_EIRQ_EN_Bits.DID_EN3 */
#define IFX_GTM_BRC_EIRQ_EN_DID_EN3_OFF (4u)

/** \brief  Length for Ifx_GTM_BRC_EIRQ_EN_Bits.DID_EN4 */
#define IFX_GTM_BRC_EIRQ_EN_DID_EN4_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_EIRQ_EN_Bits.DID_EN4 */
#define IFX_GTM_BRC_EIRQ_EN_DID_EN4_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_EIRQ_EN_Bits.DID_EN4 */
#define IFX_GTM_BRC_EIRQ_EN_DID_EN4_OFF (5u)

/** \brief  Length for Ifx_GTM_BRC_EIRQ_EN_Bits.DID_EN5 */
#define IFX_GTM_BRC_EIRQ_EN_DID_EN5_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_EIRQ_EN_Bits.DID_EN5 */
#define IFX_GTM_BRC_EIRQ_EN_DID_EN5_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_EIRQ_EN_Bits.DID_EN5 */
#define IFX_GTM_BRC_EIRQ_EN_DID_EN5_OFF (6u)

/** \brief  Length for Ifx_GTM_BRC_EIRQ_EN_Bits.DID_EN6 */
#define IFX_GTM_BRC_EIRQ_EN_DID_EN6_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_EIRQ_EN_Bits.DID_EN6 */
#define IFX_GTM_BRC_EIRQ_EN_DID_EN6_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_EIRQ_EN_Bits.DID_EN6 */
#define IFX_GTM_BRC_EIRQ_EN_DID_EN6_OFF (7u)

/** \brief  Length for Ifx_GTM_BRC_EIRQ_EN_Bits.DID_EN7 */
#define IFX_GTM_BRC_EIRQ_EN_DID_EN7_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_EIRQ_EN_Bits.DID_EN7 */
#define IFX_GTM_BRC_EIRQ_EN_DID_EN7_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_EIRQ_EN_Bits.DID_EN7 */
#define IFX_GTM_BRC_EIRQ_EN_DID_EN7_OFF (8u)

/** \brief  Length for Ifx_GTM_BRC_EIRQ_EN_Bits.DID_EN8 */
#define IFX_GTM_BRC_EIRQ_EN_DID_EN8_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_EIRQ_EN_Bits.DID_EN8 */
#define IFX_GTM_BRC_EIRQ_EN_DID_EN8_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_EIRQ_EN_Bits.DID_EN8 */
#define IFX_GTM_BRC_EIRQ_EN_DID_EN8_OFF (9u)

/** \brief  Length for Ifx_GTM_BRC_EIRQ_EN_Bits.DID_EN9 */
#define IFX_GTM_BRC_EIRQ_EN_DID_EN9_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_EIRQ_EN_Bits.DID_EN9 */
#define IFX_GTM_BRC_EIRQ_EN_DID_EN9_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_EIRQ_EN_Bits.DID_EN9 */
#define IFX_GTM_BRC_EIRQ_EN_DID_EN9_OFF (10u)

/** \brief  Length for Ifx_GTM_BRC_IRQ_EN_Bits.DEST_ERR_EN */
#define IFX_GTM_BRC_IRQ_EN_DEST_ERR_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_IRQ_EN_Bits.DEST_ERR_EN */
#define IFX_GTM_BRC_IRQ_EN_DEST_ERR_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_IRQ_EN_Bits.DEST_ERR_EN */
#define IFX_GTM_BRC_IRQ_EN_DEST_ERR_EN_OFF (0u)

/** \brief  Length for Ifx_GTM_BRC_IRQ_EN_Bits.DID_EN0 */
#define IFX_GTM_BRC_IRQ_EN_DID_EN0_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_IRQ_EN_Bits.DID_EN0 */
#define IFX_GTM_BRC_IRQ_EN_DID_EN0_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_IRQ_EN_Bits.DID_EN0 */
#define IFX_GTM_BRC_IRQ_EN_DID_EN0_OFF (1u)

/** \brief  Length for Ifx_GTM_BRC_IRQ_EN_Bits.DID_EN10 */
#define IFX_GTM_BRC_IRQ_EN_DID_EN10_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_IRQ_EN_Bits.DID_EN10 */
#define IFX_GTM_BRC_IRQ_EN_DID_EN10_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_IRQ_EN_Bits.DID_EN10 */
#define IFX_GTM_BRC_IRQ_EN_DID_EN10_OFF (11u)

/** \brief  Length for Ifx_GTM_BRC_IRQ_EN_Bits.DID_EN11 */
#define IFX_GTM_BRC_IRQ_EN_DID_EN11_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_IRQ_EN_Bits.DID_EN11 */
#define IFX_GTM_BRC_IRQ_EN_DID_EN11_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_IRQ_EN_Bits.DID_EN11 */
#define IFX_GTM_BRC_IRQ_EN_DID_EN11_OFF (12u)

/** \brief  Length for Ifx_GTM_BRC_IRQ_EN_Bits.DID_EN1 */
#define IFX_GTM_BRC_IRQ_EN_DID_EN1_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_IRQ_EN_Bits.DID_EN1 */
#define IFX_GTM_BRC_IRQ_EN_DID_EN1_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_IRQ_EN_Bits.DID_EN1 */
#define IFX_GTM_BRC_IRQ_EN_DID_EN1_OFF (2u)

/** \brief  Length for Ifx_GTM_BRC_IRQ_EN_Bits.DID_EN2 */
#define IFX_GTM_BRC_IRQ_EN_DID_EN2_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_IRQ_EN_Bits.DID_EN2 */
#define IFX_GTM_BRC_IRQ_EN_DID_EN2_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_IRQ_EN_Bits.DID_EN2 */
#define IFX_GTM_BRC_IRQ_EN_DID_EN2_OFF (3u)

/** \brief  Length for Ifx_GTM_BRC_IRQ_EN_Bits.DID_EN3 */
#define IFX_GTM_BRC_IRQ_EN_DID_EN3_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_IRQ_EN_Bits.DID_EN3 */
#define IFX_GTM_BRC_IRQ_EN_DID_EN3_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_IRQ_EN_Bits.DID_EN3 */
#define IFX_GTM_BRC_IRQ_EN_DID_EN3_OFF (4u)

/** \brief  Length for Ifx_GTM_BRC_IRQ_EN_Bits.DID_EN4 */
#define IFX_GTM_BRC_IRQ_EN_DID_EN4_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_IRQ_EN_Bits.DID_EN4 */
#define IFX_GTM_BRC_IRQ_EN_DID_EN4_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_IRQ_EN_Bits.DID_EN4 */
#define IFX_GTM_BRC_IRQ_EN_DID_EN4_OFF (5u)

/** \brief  Length for Ifx_GTM_BRC_IRQ_EN_Bits.DID_EN5 */
#define IFX_GTM_BRC_IRQ_EN_DID_EN5_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_IRQ_EN_Bits.DID_EN5 */
#define IFX_GTM_BRC_IRQ_EN_DID_EN5_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_IRQ_EN_Bits.DID_EN5 */
#define IFX_GTM_BRC_IRQ_EN_DID_EN5_OFF (6u)

/** \brief  Length for Ifx_GTM_BRC_IRQ_EN_Bits.DID_EN6 */
#define IFX_GTM_BRC_IRQ_EN_DID_EN6_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_IRQ_EN_Bits.DID_EN6 */
#define IFX_GTM_BRC_IRQ_EN_DID_EN6_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_IRQ_EN_Bits.DID_EN6 */
#define IFX_GTM_BRC_IRQ_EN_DID_EN6_OFF (7u)

/** \brief  Length for Ifx_GTM_BRC_IRQ_EN_Bits.DID_EN7 */
#define IFX_GTM_BRC_IRQ_EN_DID_EN7_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_IRQ_EN_Bits.DID_EN7 */
#define IFX_GTM_BRC_IRQ_EN_DID_EN7_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_IRQ_EN_Bits.DID_EN7 */
#define IFX_GTM_BRC_IRQ_EN_DID_EN7_OFF (8u)

/** \brief  Length for Ifx_GTM_BRC_IRQ_EN_Bits.DID_EN8 */
#define IFX_GTM_BRC_IRQ_EN_DID_EN8_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_IRQ_EN_Bits.DID_EN8 */
#define IFX_GTM_BRC_IRQ_EN_DID_EN8_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_IRQ_EN_Bits.DID_EN8 */
#define IFX_GTM_BRC_IRQ_EN_DID_EN8_OFF (9u)

/** \brief  Length for Ifx_GTM_BRC_IRQ_EN_Bits.DID_EN9 */
#define IFX_GTM_BRC_IRQ_EN_DID_EN9_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_IRQ_EN_Bits.DID_EN9 */
#define IFX_GTM_BRC_IRQ_EN_DID_EN9_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_IRQ_EN_Bits.DID_EN9 */
#define IFX_GTM_BRC_IRQ_EN_DID_EN9_OFF (10u)

/** \brief  Length for Ifx_GTM_BRC_IRQ_FORCINT_Bits.TRG_DEST_ERR */
#define IFX_GTM_BRC_IRQ_FORCINT_TRG_DEST_ERR_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_IRQ_FORCINT_Bits.TRG_DEST_ERR */
#define IFX_GTM_BRC_IRQ_FORCINT_TRG_DEST_ERR_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_IRQ_FORCINT_Bits.TRG_DEST_ERR */
#define IFX_GTM_BRC_IRQ_FORCINT_TRG_DEST_ERR_OFF (0u)

/** \brief  Length for Ifx_GTM_BRC_IRQ_FORCINT_Bits.TRG_DID0 */
#define IFX_GTM_BRC_IRQ_FORCINT_TRG_DID0_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_IRQ_FORCINT_Bits.TRG_DID0 */
#define IFX_GTM_BRC_IRQ_FORCINT_TRG_DID0_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_IRQ_FORCINT_Bits.TRG_DID0 */
#define IFX_GTM_BRC_IRQ_FORCINT_TRG_DID0_OFF (1u)

/** \brief  Length for Ifx_GTM_BRC_IRQ_FORCINT_Bits.TRG_DID10 */
#define IFX_GTM_BRC_IRQ_FORCINT_TRG_DID10_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_IRQ_FORCINT_Bits.TRG_DID10 */
#define IFX_GTM_BRC_IRQ_FORCINT_TRG_DID10_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_IRQ_FORCINT_Bits.TRG_DID10 */
#define IFX_GTM_BRC_IRQ_FORCINT_TRG_DID10_OFF (11u)

/** \brief  Length for Ifx_GTM_BRC_IRQ_FORCINT_Bits.TRG_DID11 */
#define IFX_GTM_BRC_IRQ_FORCINT_TRG_DID11_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_IRQ_FORCINT_Bits.TRG_DID11 */
#define IFX_GTM_BRC_IRQ_FORCINT_TRG_DID11_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_IRQ_FORCINT_Bits.TRG_DID11 */
#define IFX_GTM_BRC_IRQ_FORCINT_TRG_DID11_OFF (12u)

/** \brief  Length for Ifx_GTM_BRC_IRQ_FORCINT_Bits.TRG_DID1 */
#define IFX_GTM_BRC_IRQ_FORCINT_TRG_DID1_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_IRQ_FORCINT_Bits.TRG_DID1 */
#define IFX_GTM_BRC_IRQ_FORCINT_TRG_DID1_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_IRQ_FORCINT_Bits.TRG_DID1 */
#define IFX_GTM_BRC_IRQ_FORCINT_TRG_DID1_OFF (2u)

/** \brief  Length for Ifx_GTM_BRC_IRQ_FORCINT_Bits.TRG_DID2 */
#define IFX_GTM_BRC_IRQ_FORCINT_TRG_DID2_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_IRQ_FORCINT_Bits.TRG_DID2 */
#define IFX_GTM_BRC_IRQ_FORCINT_TRG_DID2_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_IRQ_FORCINT_Bits.TRG_DID2 */
#define IFX_GTM_BRC_IRQ_FORCINT_TRG_DID2_OFF (3u)

/** \brief  Length for Ifx_GTM_BRC_IRQ_FORCINT_Bits.TRG_DID3 */
#define IFX_GTM_BRC_IRQ_FORCINT_TRG_DID3_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_IRQ_FORCINT_Bits.TRG_DID3 */
#define IFX_GTM_BRC_IRQ_FORCINT_TRG_DID3_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_IRQ_FORCINT_Bits.TRG_DID3 */
#define IFX_GTM_BRC_IRQ_FORCINT_TRG_DID3_OFF (4u)

/** \brief  Length for Ifx_GTM_BRC_IRQ_FORCINT_Bits.TRG_DID4 */
#define IFX_GTM_BRC_IRQ_FORCINT_TRG_DID4_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_IRQ_FORCINT_Bits.TRG_DID4 */
#define IFX_GTM_BRC_IRQ_FORCINT_TRG_DID4_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_IRQ_FORCINT_Bits.TRG_DID4 */
#define IFX_GTM_BRC_IRQ_FORCINT_TRG_DID4_OFF (5u)

/** \brief  Length for Ifx_GTM_BRC_IRQ_FORCINT_Bits.TRG_DID5 */
#define IFX_GTM_BRC_IRQ_FORCINT_TRG_DID5_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_IRQ_FORCINT_Bits.TRG_DID5 */
#define IFX_GTM_BRC_IRQ_FORCINT_TRG_DID5_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_IRQ_FORCINT_Bits.TRG_DID5 */
#define IFX_GTM_BRC_IRQ_FORCINT_TRG_DID5_OFF (6u)

/** \brief  Length for Ifx_GTM_BRC_IRQ_FORCINT_Bits.TRG_DID6 */
#define IFX_GTM_BRC_IRQ_FORCINT_TRG_DID6_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_IRQ_FORCINT_Bits.TRG_DID6 */
#define IFX_GTM_BRC_IRQ_FORCINT_TRG_DID6_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_IRQ_FORCINT_Bits.TRG_DID6 */
#define IFX_GTM_BRC_IRQ_FORCINT_TRG_DID6_OFF (7u)

/** \brief  Length for Ifx_GTM_BRC_IRQ_FORCINT_Bits.TRG_DID7 */
#define IFX_GTM_BRC_IRQ_FORCINT_TRG_DID7_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_IRQ_FORCINT_Bits.TRG_DID7 */
#define IFX_GTM_BRC_IRQ_FORCINT_TRG_DID7_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_IRQ_FORCINT_Bits.TRG_DID7 */
#define IFX_GTM_BRC_IRQ_FORCINT_TRG_DID7_OFF (8u)

/** \brief  Length for Ifx_GTM_BRC_IRQ_FORCINT_Bits.TRG_DID8 */
#define IFX_GTM_BRC_IRQ_FORCINT_TRG_DID8_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_IRQ_FORCINT_Bits.TRG_DID8 */
#define IFX_GTM_BRC_IRQ_FORCINT_TRG_DID8_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_IRQ_FORCINT_Bits.TRG_DID8 */
#define IFX_GTM_BRC_IRQ_FORCINT_TRG_DID8_OFF (9u)

/** \brief  Length for Ifx_GTM_BRC_IRQ_FORCINT_Bits.TRG_DID9 */
#define IFX_GTM_BRC_IRQ_FORCINT_TRG_DID9_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_IRQ_FORCINT_Bits.TRG_DID9 */
#define IFX_GTM_BRC_IRQ_FORCINT_TRG_DID9_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_IRQ_FORCINT_Bits.TRG_DID9 */
#define IFX_GTM_BRC_IRQ_FORCINT_TRG_DID9_OFF (10u)

/** \brief  Length for Ifx_GTM_BRC_IRQ_MODE_Bits.IRQ_MODE */
#define IFX_GTM_BRC_IRQ_MODE_IRQ_MODE_LEN (2u)

/** \brief  Mask for Ifx_GTM_BRC_IRQ_MODE_Bits.IRQ_MODE */
#define IFX_GTM_BRC_IRQ_MODE_IRQ_MODE_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_BRC_IRQ_MODE_Bits.IRQ_MODE */
#define IFX_GTM_BRC_IRQ_MODE_IRQ_MODE_OFF (0u)

/** \brief  Length for Ifx_GTM_BRC_IRQ_NOTIFY_Bits.DEST_ERR */
#define IFX_GTM_BRC_IRQ_NOTIFY_DEST_ERR_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_IRQ_NOTIFY_Bits.DEST_ERR */
#define IFX_GTM_BRC_IRQ_NOTIFY_DEST_ERR_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_IRQ_NOTIFY_Bits.DEST_ERR */
#define IFX_GTM_BRC_IRQ_NOTIFY_DEST_ERR_OFF (0u)

/** \brief  Length for Ifx_GTM_BRC_IRQ_NOTIFY_Bits.DID0 */
#define IFX_GTM_BRC_IRQ_NOTIFY_DID0_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_IRQ_NOTIFY_Bits.DID0 */
#define IFX_GTM_BRC_IRQ_NOTIFY_DID0_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_IRQ_NOTIFY_Bits.DID0 */
#define IFX_GTM_BRC_IRQ_NOTIFY_DID0_OFF (1u)

/** \brief  Length for Ifx_GTM_BRC_IRQ_NOTIFY_Bits.DID10 */
#define IFX_GTM_BRC_IRQ_NOTIFY_DID10_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_IRQ_NOTIFY_Bits.DID10 */
#define IFX_GTM_BRC_IRQ_NOTIFY_DID10_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_IRQ_NOTIFY_Bits.DID10 */
#define IFX_GTM_BRC_IRQ_NOTIFY_DID10_OFF (11u)

/** \brief  Length for Ifx_GTM_BRC_IRQ_NOTIFY_Bits.DID11 */
#define IFX_GTM_BRC_IRQ_NOTIFY_DID11_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_IRQ_NOTIFY_Bits.DID11 */
#define IFX_GTM_BRC_IRQ_NOTIFY_DID11_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_IRQ_NOTIFY_Bits.DID11 */
#define IFX_GTM_BRC_IRQ_NOTIFY_DID11_OFF (12u)

/** \brief  Length for Ifx_GTM_BRC_IRQ_NOTIFY_Bits.DID1 */
#define IFX_GTM_BRC_IRQ_NOTIFY_DID1_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_IRQ_NOTIFY_Bits.DID1 */
#define IFX_GTM_BRC_IRQ_NOTIFY_DID1_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_IRQ_NOTIFY_Bits.DID1 */
#define IFX_GTM_BRC_IRQ_NOTIFY_DID1_OFF (2u)

/** \brief  Length for Ifx_GTM_BRC_IRQ_NOTIFY_Bits.DID2 */
#define IFX_GTM_BRC_IRQ_NOTIFY_DID2_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_IRQ_NOTIFY_Bits.DID2 */
#define IFX_GTM_BRC_IRQ_NOTIFY_DID2_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_IRQ_NOTIFY_Bits.DID2 */
#define IFX_GTM_BRC_IRQ_NOTIFY_DID2_OFF (3u)

/** \brief  Length for Ifx_GTM_BRC_IRQ_NOTIFY_Bits.DID3 */
#define IFX_GTM_BRC_IRQ_NOTIFY_DID3_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_IRQ_NOTIFY_Bits.DID3 */
#define IFX_GTM_BRC_IRQ_NOTIFY_DID3_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_IRQ_NOTIFY_Bits.DID3 */
#define IFX_GTM_BRC_IRQ_NOTIFY_DID3_OFF (4u)

/** \brief  Length for Ifx_GTM_BRC_IRQ_NOTIFY_Bits.DID4 */
#define IFX_GTM_BRC_IRQ_NOTIFY_DID4_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_IRQ_NOTIFY_Bits.DID4 */
#define IFX_GTM_BRC_IRQ_NOTIFY_DID4_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_IRQ_NOTIFY_Bits.DID4 */
#define IFX_GTM_BRC_IRQ_NOTIFY_DID4_OFF (5u)

/** \brief  Length for Ifx_GTM_BRC_IRQ_NOTIFY_Bits.DID5 */
#define IFX_GTM_BRC_IRQ_NOTIFY_DID5_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_IRQ_NOTIFY_Bits.DID5 */
#define IFX_GTM_BRC_IRQ_NOTIFY_DID5_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_IRQ_NOTIFY_Bits.DID5 */
#define IFX_GTM_BRC_IRQ_NOTIFY_DID5_OFF (6u)

/** \brief  Length for Ifx_GTM_BRC_IRQ_NOTIFY_Bits.DID6 */
#define IFX_GTM_BRC_IRQ_NOTIFY_DID6_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_IRQ_NOTIFY_Bits.DID6 */
#define IFX_GTM_BRC_IRQ_NOTIFY_DID6_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_IRQ_NOTIFY_Bits.DID6 */
#define IFX_GTM_BRC_IRQ_NOTIFY_DID6_OFF (7u)

/** \brief  Length for Ifx_GTM_BRC_IRQ_NOTIFY_Bits.DID7 */
#define IFX_GTM_BRC_IRQ_NOTIFY_DID7_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_IRQ_NOTIFY_Bits.DID7 */
#define IFX_GTM_BRC_IRQ_NOTIFY_DID7_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_IRQ_NOTIFY_Bits.DID7 */
#define IFX_GTM_BRC_IRQ_NOTIFY_DID7_OFF (8u)

/** \brief  Length for Ifx_GTM_BRC_IRQ_NOTIFY_Bits.DID8 */
#define IFX_GTM_BRC_IRQ_NOTIFY_DID8_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_IRQ_NOTIFY_Bits.DID8 */
#define IFX_GTM_BRC_IRQ_NOTIFY_DID8_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_IRQ_NOTIFY_Bits.DID8 */
#define IFX_GTM_BRC_IRQ_NOTIFY_DID8_OFF (9u)

/** \brief  Length for Ifx_GTM_BRC_IRQ_NOTIFY_Bits.DID9 */
#define IFX_GTM_BRC_IRQ_NOTIFY_DID9_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_IRQ_NOTIFY_Bits.DID9 */
#define IFX_GTM_BRC_IRQ_NOTIFY_DID9_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_IRQ_NOTIFY_Bits.DID9 */
#define IFX_GTM_BRC_IRQ_NOTIFY_DID9_OFF (10u)

/** \brief  Length for Ifx_GTM_BRC_RST_Bits.RST */
#define IFX_GTM_BRC_RST_RST_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_RST_Bits.RST */
#define IFX_GTM_BRC_RST_RST_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_RST_Bits.RST */
#define IFX_GTM_BRC_RST_RST_OFF (0u)

/** \brief  Length for Ifx_GTM_BRC_SRC0_ADDR_Bits.ADDR */
#define IFX_GTM_BRC_SRC0_ADDR_ADDR_LEN (9u)

/** \brief  Mask for Ifx_GTM_BRC_SRC0_ADDR_Bits.ADDR */
#define IFX_GTM_BRC_SRC0_ADDR_ADDR_MSK (0x1ffu)

/** \brief  Offset for Ifx_GTM_BRC_SRC0_ADDR_Bits.ADDR */
#define IFX_GTM_BRC_SRC0_ADDR_ADDR_OFF (0u)

/** \brief  Length for Ifx_GTM_BRC_SRC0_ADDR_Bits.BRC_MODE */
#define IFX_GTM_BRC_SRC0_ADDR_BRC_MODE_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC0_ADDR_Bits.BRC_MODE */
#define IFX_GTM_BRC_SRC0_ADDR_BRC_MODE_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC0_ADDR_Bits.BRC_MODE */
#define IFX_GTM_BRC_SRC0_ADDR_BRC_MODE_OFF (12u)

/** \brief  Length for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST0 */
#define IFX_GTM_BRC_SRC0_DEST_EN_DEST0_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST0 */
#define IFX_GTM_BRC_SRC0_DEST_EN_DEST0_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST0 */
#define IFX_GTM_BRC_SRC0_DEST_EN_DEST0_OFF (0u)

/** \brief  Length for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST10 */
#define IFX_GTM_BRC_SRC0_DEST_EN_DEST10_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST10 */
#define IFX_GTM_BRC_SRC0_DEST_EN_DEST10_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST10 */
#define IFX_GTM_BRC_SRC0_DEST_EN_DEST10_OFF (10u)

/** \brief  Length for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST11 */
#define IFX_GTM_BRC_SRC0_DEST_EN_DEST11_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST11 */
#define IFX_GTM_BRC_SRC0_DEST_EN_DEST11_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST11 */
#define IFX_GTM_BRC_SRC0_DEST_EN_DEST11_OFF (11u)

/** \brief  Length for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST12 */
#define IFX_GTM_BRC_SRC0_DEST_EN_DEST12_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST12 */
#define IFX_GTM_BRC_SRC0_DEST_EN_DEST12_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST12 */
#define IFX_GTM_BRC_SRC0_DEST_EN_DEST12_OFF (12u)

/** \brief  Length for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST13 */
#define IFX_GTM_BRC_SRC0_DEST_EN_DEST13_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST13 */
#define IFX_GTM_BRC_SRC0_DEST_EN_DEST13_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST13 */
#define IFX_GTM_BRC_SRC0_DEST_EN_DEST13_OFF (13u)

/** \brief  Length for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST14 */
#define IFX_GTM_BRC_SRC0_DEST_EN_DEST14_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST14 */
#define IFX_GTM_BRC_SRC0_DEST_EN_DEST14_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST14 */
#define IFX_GTM_BRC_SRC0_DEST_EN_DEST14_OFF (14u)

/** \brief  Length for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST15 */
#define IFX_GTM_BRC_SRC0_DEST_EN_DEST15_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST15 */
#define IFX_GTM_BRC_SRC0_DEST_EN_DEST15_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST15 */
#define IFX_GTM_BRC_SRC0_DEST_EN_DEST15_OFF (15u)

/** \brief  Length for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST16 */
#define IFX_GTM_BRC_SRC0_DEST_EN_DEST16_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST16 */
#define IFX_GTM_BRC_SRC0_DEST_EN_DEST16_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST16 */
#define IFX_GTM_BRC_SRC0_DEST_EN_DEST16_OFF (16u)

/** \brief  Length for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST17 */
#define IFX_GTM_BRC_SRC0_DEST_EN_DEST17_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST17 */
#define IFX_GTM_BRC_SRC0_DEST_EN_DEST17_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST17 */
#define IFX_GTM_BRC_SRC0_DEST_EN_DEST17_OFF (17u)

/** \brief  Length for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST18 */
#define IFX_GTM_BRC_SRC0_DEST_EN_DEST18_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST18 */
#define IFX_GTM_BRC_SRC0_DEST_EN_DEST18_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST18 */
#define IFX_GTM_BRC_SRC0_DEST_EN_DEST18_OFF (18u)

/** \brief  Length for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST19 */
#define IFX_GTM_BRC_SRC0_DEST_EN_DEST19_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST19 */
#define IFX_GTM_BRC_SRC0_DEST_EN_DEST19_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST19 */
#define IFX_GTM_BRC_SRC0_DEST_EN_DEST19_OFF (19u)

/** \brief  Length for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST1 */
#define IFX_GTM_BRC_SRC0_DEST_EN_DEST1_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST1 */
#define IFX_GTM_BRC_SRC0_DEST_EN_DEST1_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST1 */
#define IFX_GTM_BRC_SRC0_DEST_EN_DEST1_OFF (1u)

/** \brief  Length for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST20 */
#define IFX_GTM_BRC_SRC0_DEST_EN_DEST20_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST20 */
#define IFX_GTM_BRC_SRC0_DEST_EN_DEST20_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST20 */
#define IFX_GTM_BRC_SRC0_DEST_EN_DEST20_OFF (20u)

/** \brief  Length for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST21 */
#define IFX_GTM_BRC_SRC0_DEST_EN_DEST21_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST21 */
#define IFX_GTM_BRC_SRC0_DEST_EN_DEST21_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST21 */
#define IFX_GTM_BRC_SRC0_DEST_EN_DEST21_OFF (21u)

/** \brief  Length for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST2 */
#define IFX_GTM_BRC_SRC0_DEST_EN_DEST2_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST2 */
#define IFX_GTM_BRC_SRC0_DEST_EN_DEST2_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST2 */
#define IFX_GTM_BRC_SRC0_DEST_EN_DEST2_OFF (2u)

/** \brief  Length for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST3 */
#define IFX_GTM_BRC_SRC0_DEST_EN_DEST3_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST3 */
#define IFX_GTM_BRC_SRC0_DEST_EN_DEST3_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST3 */
#define IFX_GTM_BRC_SRC0_DEST_EN_DEST3_OFF (3u)

/** \brief  Length for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST4 */
#define IFX_GTM_BRC_SRC0_DEST_EN_DEST4_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST4 */
#define IFX_GTM_BRC_SRC0_DEST_EN_DEST4_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST4 */
#define IFX_GTM_BRC_SRC0_DEST_EN_DEST4_OFF (4u)

/** \brief  Length for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST5 */
#define IFX_GTM_BRC_SRC0_DEST_EN_DEST5_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST5 */
#define IFX_GTM_BRC_SRC0_DEST_EN_DEST5_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST5 */
#define IFX_GTM_BRC_SRC0_DEST_EN_DEST5_OFF (5u)

/** \brief  Length for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST6 */
#define IFX_GTM_BRC_SRC0_DEST_EN_DEST6_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST6 */
#define IFX_GTM_BRC_SRC0_DEST_EN_DEST6_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST6 */
#define IFX_GTM_BRC_SRC0_DEST_EN_DEST6_OFF (6u)

/** \brief  Length for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST7 */
#define IFX_GTM_BRC_SRC0_DEST_EN_DEST7_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST7 */
#define IFX_GTM_BRC_SRC0_DEST_EN_DEST7_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST7 */
#define IFX_GTM_BRC_SRC0_DEST_EN_DEST7_OFF (7u)

/** \brief  Length for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST8 */
#define IFX_GTM_BRC_SRC0_DEST_EN_DEST8_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST8 */
#define IFX_GTM_BRC_SRC0_DEST_EN_DEST8_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST8 */
#define IFX_GTM_BRC_SRC0_DEST_EN_DEST8_OFF (8u)

/** \brief  Length for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST9 */
#define IFX_GTM_BRC_SRC0_DEST_EN_DEST9_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST9 */
#define IFX_GTM_BRC_SRC0_DEST_EN_DEST9_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_DEST9 */
#define IFX_GTM_BRC_SRC0_DEST_EN_DEST9_OFF (9u)

/** \brief  Length for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_TRASHBIN */
#define IFX_GTM_BRC_SRC0_DEST_EN_TRASHBIN_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_TRASHBIN */
#define IFX_GTM_BRC_SRC0_DEST_EN_TRASHBIN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC0_DEST_Bits.EN_TRASHBIN */
#define IFX_GTM_BRC_SRC0_DEST_EN_TRASHBIN_OFF (22u)

/** \brief  Length for Ifx_GTM_BRC_SRC10_ADDR_Bits.ADDR */
#define IFX_GTM_BRC_SRC10_ADDR_ADDR_LEN (9u)

/** \brief  Mask for Ifx_GTM_BRC_SRC10_ADDR_Bits.ADDR */
#define IFX_GTM_BRC_SRC10_ADDR_ADDR_MSK (0x1ffu)

/** \brief  Offset for Ifx_GTM_BRC_SRC10_ADDR_Bits.ADDR */
#define IFX_GTM_BRC_SRC10_ADDR_ADDR_OFF (0u)

/** \brief  Length for Ifx_GTM_BRC_SRC10_ADDR_Bits.BRC_MODE */
#define IFX_GTM_BRC_SRC10_ADDR_BRC_MODE_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC10_ADDR_Bits.BRC_MODE */
#define IFX_GTM_BRC_SRC10_ADDR_BRC_MODE_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC10_ADDR_Bits.BRC_MODE */
#define IFX_GTM_BRC_SRC10_ADDR_BRC_MODE_OFF (12u)

/** \brief  Length for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST0 */
#define IFX_GTM_BRC_SRC10_DEST_EN_DEST0_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST0 */
#define IFX_GTM_BRC_SRC10_DEST_EN_DEST0_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST0 */
#define IFX_GTM_BRC_SRC10_DEST_EN_DEST0_OFF (0u)

/** \brief  Length for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST10 */
#define IFX_GTM_BRC_SRC10_DEST_EN_DEST10_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST10 */
#define IFX_GTM_BRC_SRC10_DEST_EN_DEST10_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST10 */
#define IFX_GTM_BRC_SRC10_DEST_EN_DEST10_OFF (10u)

/** \brief  Length for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST11 */
#define IFX_GTM_BRC_SRC10_DEST_EN_DEST11_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST11 */
#define IFX_GTM_BRC_SRC10_DEST_EN_DEST11_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST11 */
#define IFX_GTM_BRC_SRC10_DEST_EN_DEST11_OFF (11u)

/** \brief  Length for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST12 */
#define IFX_GTM_BRC_SRC10_DEST_EN_DEST12_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST12 */
#define IFX_GTM_BRC_SRC10_DEST_EN_DEST12_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST12 */
#define IFX_GTM_BRC_SRC10_DEST_EN_DEST12_OFF (12u)

/** \brief  Length for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST13 */
#define IFX_GTM_BRC_SRC10_DEST_EN_DEST13_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST13 */
#define IFX_GTM_BRC_SRC10_DEST_EN_DEST13_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST13 */
#define IFX_GTM_BRC_SRC10_DEST_EN_DEST13_OFF (13u)

/** \brief  Length for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST14 */
#define IFX_GTM_BRC_SRC10_DEST_EN_DEST14_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST14 */
#define IFX_GTM_BRC_SRC10_DEST_EN_DEST14_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST14 */
#define IFX_GTM_BRC_SRC10_DEST_EN_DEST14_OFF (14u)

/** \brief  Length for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST15 */
#define IFX_GTM_BRC_SRC10_DEST_EN_DEST15_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST15 */
#define IFX_GTM_BRC_SRC10_DEST_EN_DEST15_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST15 */
#define IFX_GTM_BRC_SRC10_DEST_EN_DEST15_OFF (15u)

/** \brief  Length for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST16 */
#define IFX_GTM_BRC_SRC10_DEST_EN_DEST16_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST16 */
#define IFX_GTM_BRC_SRC10_DEST_EN_DEST16_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST16 */
#define IFX_GTM_BRC_SRC10_DEST_EN_DEST16_OFF (16u)

/** \brief  Length for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST17 */
#define IFX_GTM_BRC_SRC10_DEST_EN_DEST17_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST17 */
#define IFX_GTM_BRC_SRC10_DEST_EN_DEST17_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST17 */
#define IFX_GTM_BRC_SRC10_DEST_EN_DEST17_OFF (17u)

/** \brief  Length for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST18 */
#define IFX_GTM_BRC_SRC10_DEST_EN_DEST18_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST18 */
#define IFX_GTM_BRC_SRC10_DEST_EN_DEST18_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST18 */
#define IFX_GTM_BRC_SRC10_DEST_EN_DEST18_OFF (18u)

/** \brief  Length for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST19 */
#define IFX_GTM_BRC_SRC10_DEST_EN_DEST19_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST19 */
#define IFX_GTM_BRC_SRC10_DEST_EN_DEST19_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST19 */
#define IFX_GTM_BRC_SRC10_DEST_EN_DEST19_OFF (19u)

/** \brief  Length for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST1 */
#define IFX_GTM_BRC_SRC10_DEST_EN_DEST1_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST1 */
#define IFX_GTM_BRC_SRC10_DEST_EN_DEST1_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST1 */
#define IFX_GTM_BRC_SRC10_DEST_EN_DEST1_OFF (1u)

/** \brief  Length for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST20 */
#define IFX_GTM_BRC_SRC10_DEST_EN_DEST20_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST20 */
#define IFX_GTM_BRC_SRC10_DEST_EN_DEST20_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST20 */
#define IFX_GTM_BRC_SRC10_DEST_EN_DEST20_OFF (20u)

/** \brief  Length for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST21 */
#define IFX_GTM_BRC_SRC10_DEST_EN_DEST21_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST21 */
#define IFX_GTM_BRC_SRC10_DEST_EN_DEST21_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST21 */
#define IFX_GTM_BRC_SRC10_DEST_EN_DEST21_OFF (21u)

/** \brief  Length for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST2 */
#define IFX_GTM_BRC_SRC10_DEST_EN_DEST2_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST2 */
#define IFX_GTM_BRC_SRC10_DEST_EN_DEST2_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST2 */
#define IFX_GTM_BRC_SRC10_DEST_EN_DEST2_OFF (2u)

/** \brief  Length for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST3 */
#define IFX_GTM_BRC_SRC10_DEST_EN_DEST3_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST3 */
#define IFX_GTM_BRC_SRC10_DEST_EN_DEST3_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST3 */
#define IFX_GTM_BRC_SRC10_DEST_EN_DEST3_OFF (3u)

/** \brief  Length for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST4 */
#define IFX_GTM_BRC_SRC10_DEST_EN_DEST4_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST4 */
#define IFX_GTM_BRC_SRC10_DEST_EN_DEST4_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST4 */
#define IFX_GTM_BRC_SRC10_DEST_EN_DEST4_OFF (4u)

/** \brief  Length for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST5 */
#define IFX_GTM_BRC_SRC10_DEST_EN_DEST5_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST5 */
#define IFX_GTM_BRC_SRC10_DEST_EN_DEST5_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST5 */
#define IFX_GTM_BRC_SRC10_DEST_EN_DEST5_OFF (5u)

/** \brief  Length for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST6 */
#define IFX_GTM_BRC_SRC10_DEST_EN_DEST6_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST6 */
#define IFX_GTM_BRC_SRC10_DEST_EN_DEST6_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST6 */
#define IFX_GTM_BRC_SRC10_DEST_EN_DEST6_OFF (6u)

/** \brief  Length for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST7 */
#define IFX_GTM_BRC_SRC10_DEST_EN_DEST7_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST7 */
#define IFX_GTM_BRC_SRC10_DEST_EN_DEST7_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST7 */
#define IFX_GTM_BRC_SRC10_DEST_EN_DEST7_OFF (7u)

/** \brief  Length for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST8 */
#define IFX_GTM_BRC_SRC10_DEST_EN_DEST8_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST8 */
#define IFX_GTM_BRC_SRC10_DEST_EN_DEST8_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST8 */
#define IFX_GTM_BRC_SRC10_DEST_EN_DEST8_OFF (8u)

/** \brief  Length for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST9 */
#define IFX_GTM_BRC_SRC10_DEST_EN_DEST9_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST9 */
#define IFX_GTM_BRC_SRC10_DEST_EN_DEST9_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_DEST9 */
#define IFX_GTM_BRC_SRC10_DEST_EN_DEST9_OFF (9u)

/** \brief  Length for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_TRASHBIN */
#define IFX_GTM_BRC_SRC10_DEST_EN_TRASHBIN_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_TRASHBIN */
#define IFX_GTM_BRC_SRC10_DEST_EN_TRASHBIN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC10_DEST_Bits.EN_TRASHBIN */
#define IFX_GTM_BRC_SRC10_DEST_EN_TRASHBIN_OFF (22u)

/** \brief  Length for Ifx_GTM_BRC_SRC11_ADDR_Bits.ADDR */
#define IFX_GTM_BRC_SRC11_ADDR_ADDR_LEN (9u)

/** \brief  Mask for Ifx_GTM_BRC_SRC11_ADDR_Bits.ADDR */
#define IFX_GTM_BRC_SRC11_ADDR_ADDR_MSK (0x1ffu)

/** \brief  Offset for Ifx_GTM_BRC_SRC11_ADDR_Bits.ADDR */
#define IFX_GTM_BRC_SRC11_ADDR_ADDR_OFF (0u)

/** \brief  Length for Ifx_GTM_BRC_SRC11_ADDR_Bits.BRC_MODE */
#define IFX_GTM_BRC_SRC11_ADDR_BRC_MODE_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC11_ADDR_Bits.BRC_MODE */
#define IFX_GTM_BRC_SRC11_ADDR_BRC_MODE_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC11_ADDR_Bits.BRC_MODE */
#define IFX_GTM_BRC_SRC11_ADDR_BRC_MODE_OFF (12u)

/** \brief  Length for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST0 */
#define IFX_GTM_BRC_SRC11_DEST_EN_DEST0_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST0 */
#define IFX_GTM_BRC_SRC11_DEST_EN_DEST0_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST0 */
#define IFX_GTM_BRC_SRC11_DEST_EN_DEST0_OFF (0u)

/** \brief  Length for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST10 */
#define IFX_GTM_BRC_SRC11_DEST_EN_DEST10_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST10 */
#define IFX_GTM_BRC_SRC11_DEST_EN_DEST10_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST10 */
#define IFX_GTM_BRC_SRC11_DEST_EN_DEST10_OFF (10u)

/** \brief  Length for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST11 */
#define IFX_GTM_BRC_SRC11_DEST_EN_DEST11_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST11 */
#define IFX_GTM_BRC_SRC11_DEST_EN_DEST11_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST11 */
#define IFX_GTM_BRC_SRC11_DEST_EN_DEST11_OFF (11u)

/** \brief  Length for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST12 */
#define IFX_GTM_BRC_SRC11_DEST_EN_DEST12_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST12 */
#define IFX_GTM_BRC_SRC11_DEST_EN_DEST12_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST12 */
#define IFX_GTM_BRC_SRC11_DEST_EN_DEST12_OFF (12u)

/** \brief  Length for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST13 */
#define IFX_GTM_BRC_SRC11_DEST_EN_DEST13_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST13 */
#define IFX_GTM_BRC_SRC11_DEST_EN_DEST13_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST13 */
#define IFX_GTM_BRC_SRC11_DEST_EN_DEST13_OFF (13u)

/** \brief  Length for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST14 */
#define IFX_GTM_BRC_SRC11_DEST_EN_DEST14_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST14 */
#define IFX_GTM_BRC_SRC11_DEST_EN_DEST14_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST14 */
#define IFX_GTM_BRC_SRC11_DEST_EN_DEST14_OFF (14u)

/** \brief  Length for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST15 */
#define IFX_GTM_BRC_SRC11_DEST_EN_DEST15_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST15 */
#define IFX_GTM_BRC_SRC11_DEST_EN_DEST15_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST15 */
#define IFX_GTM_BRC_SRC11_DEST_EN_DEST15_OFF (15u)

/** \brief  Length for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST16 */
#define IFX_GTM_BRC_SRC11_DEST_EN_DEST16_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST16 */
#define IFX_GTM_BRC_SRC11_DEST_EN_DEST16_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST16 */
#define IFX_GTM_BRC_SRC11_DEST_EN_DEST16_OFF (16u)

/** \brief  Length for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST17 */
#define IFX_GTM_BRC_SRC11_DEST_EN_DEST17_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST17 */
#define IFX_GTM_BRC_SRC11_DEST_EN_DEST17_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST17 */
#define IFX_GTM_BRC_SRC11_DEST_EN_DEST17_OFF (17u)

/** \brief  Length for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST18 */
#define IFX_GTM_BRC_SRC11_DEST_EN_DEST18_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST18 */
#define IFX_GTM_BRC_SRC11_DEST_EN_DEST18_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST18 */
#define IFX_GTM_BRC_SRC11_DEST_EN_DEST18_OFF (18u)

/** \brief  Length for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST19 */
#define IFX_GTM_BRC_SRC11_DEST_EN_DEST19_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST19 */
#define IFX_GTM_BRC_SRC11_DEST_EN_DEST19_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST19 */
#define IFX_GTM_BRC_SRC11_DEST_EN_DEST19_OFF (19u)

/** \brief  Length for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST1 */
#define IFX_GTM_BRC_SRC11_DEST_EN_DEST1_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST1 */
#define IFX_GTM_BRC_SRC11_DEST_EN_DEST1_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST1 */
#define IFX_GTM_BRC_SRC11_DEST_EN_DEST1_OFF (1u)

/** \brief  Length for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST20 */
#define IFX_GTM_BRC_SRC11_DEST_EN_DEST20_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST20 */
#define IFX_GTM_BRC_SRC11_DEST_EN_DEST20_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST20 */
#define IFX_GTM_BRC_SRC11_DEST_EN_DEST20_OFF (20u)

/** \brief  Length for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST21 */
#define IFX_GTM_BRC_SRC11_DEST_EN_DEST21_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST21 */
#define IFX_GTM_BRC_SRC11_DEST_EN_DEST21_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST21 */
#define IFX_GTM_BRC_SRC11_DEST_EN_DEST21_OFF (21u)

/** \brief  Length for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST2 */
#define IFX_GTM_BRC_SRC11_DEST_EN_DEST2_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST2 */
#define IFX_GTM_BRC_SRC11_DEST_EN_DEST2_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST2 */
#define IFX_GTM_BRC_SRC11_DEST_EN_DEST2_OFF (2u)

/** \brief  Length for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST3 */
#define IFX_GTM_BRC_SRC11_DEST_EN_DEST3_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST3 */
#define IFX_GTM_BRC_SRC11_DEST_EN_DEST3_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST3 */
#define IFX_GTM_BRC_SRC11_DEST_EN_DEST3_OFF (3u)

/** \brief  Length for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST4 */
#define IFX_GTM_BRC_SRC11_DEST_EN_DEST4_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST4 */
#define IFX_GTM_BRC_SRC11_DEST_EN_DEST4_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST4 */
#define IFX_GTM_BRC_SRC11_DEST_EN_DEST4_OFF (4u)

/** \brief  Length for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST5 */
#define IFX_GTM_BRC_SRC11_DEST_EN_DEST5_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST5 */
#define IFX_GTM_BRC_SRC11_DEST_EN_DEST5_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST5 */
#define IFX_GTM_BRC_SRC11_DEST_EN_DEST5_OFF (5u)

/** \brief  Length for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST6 */
#define IFX_GTM_BRC_SRC11_DEST_EN_DEST6_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST6 */
#define IFX_GTM_BRC_SRC11_DEST_EN_DEST6_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST6 */
#define IFX_GTM_BRC_SRC11_DEST_EN_DEST6_OFF (6u)

/** \brief  Length for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST7 */
#define IFX_GTM_BRC_SRC11_DEST_EN_DEST7_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST7 */
#define IFX_GTM_BRC_SRC11_DEST_EN_DEST7_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST7 */
#define IFX_GTM_BRC_SRC11_DEST_EN_DEST7_OFF (7u)

/** \brief  Length for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST8 */
#define IFX_GTM_BRC_SRC11_DEST_EN_DEST8_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST8 */
#define IFX_GTM_BRC_SRC11_DEST_EN_DEST8_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST8 */
#define IFX_GTM_BRC_SRC11_DEST_EN_DEST8_OFF (8u)

/** \brief  Length for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST9 */
#define IFX_GTM_BRC_SRC11_DEST_EN_DEST9_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST9 */
#define IFX_GTM_BRC_SRC11_DEST_EN_DEST9_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_DEST9 */
#define IFX_GTM_BRC_SRC11_DEST_EN_DEST9_OFF (9u)

/** \brief  Length for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_TRASHBIN */
#define IFX_GTM_BRC_SRC11_DEST_EN_TRASHBIN_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_TRASHBIN */
#define IFX_GTM_BRC_SRC11_DEST_EN_TRASHBIN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC11_DEST_Bits.EN_TRASHBIN */
#define IFX_GTM_BRC_SRC11_DEST_EN_TRASHBIN_OFF (22u)

/** \brief  Length for Ifx_GTM_BRC_SRC1_ADDR_Bits.ADDR */
#define IFX_GTM_BRC_SRC1_ADDR_ADDR_LEN (9u)

/** \brief  Mask for Ifx_GTM_BRC_SRC1_ADDR_Bits.ADDR */
#define IFX_GTM_BRC_SRC1_ADDR_ADDR_MSK (0x1ffu)

/** \brief  Offset for Ifx_GTM_BRC_SRC1_ADDR_Bits.ADDR */
#define IFX_GTM_BRC_SRC1_ADDR_ADDR_OFF (0u)

/** \brief  Length for Ifx_GTM_BRC_SRC1_ADDR_Bits.BRC_MODE */
#define IFX_GTM_BRC_SRC1_ADDR_BRC_MODE_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC1_ADDR_Bits.BRC_MODE */
#define IFX_GTM_BRC_SRC1_ADDR_BRC_MODE_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC1_ADDR_Bits.BRC_MODE */
#define IFX_GTM_BRC_SRC1_ADDR_BRC_MODE_OFF (12u)

/** \brief  Length for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST0 */
#define IFX_GTM_BRC_SRC1_DEST_EN_DEST0_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST0 */
#define IFX_GTM_BRC_SRC1_DEST_EN_DEST0_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST0 */
#define IFX_GTM_BRC_SRC1_DEST_EN_DEST0_OFF (0u)

/** \brief  Length for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST10 */
#define IFX_GTM_BRC_SRC1_DEST_EN_DEST10_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST10 */
#define IFX_GTM_BRC_SRC1_DEST_EN_DEST10_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST10 */
#define IFX_GTM_BRC_SRC1_DEST_EN_DEST10_OFF (10u)

/** \brief  Length for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST11 */
#define IFX_GTM_BRC_SRC1_DEST_EN_DEST11_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST11 */
#define IFX_GTM_BRC_SRC1_DEST_EN_DEST11_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST11 */
#define IFX_GTM_BRC_SRC1_DEST_EN_DEST11_OFF (11u)

/** \brief  Length for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST12 */
#define IFX_GTM_BRC_SRC1_DEST_EN_DEST12_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST12 */
#define IFX_GTM_BRC_SRC1_DEST_EN_DEST12_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST12 */
#define IFX_GTM_BRC_SRC1_DEST_EN_DEST12_OFF (12u)

/** \brief  Length for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST13 */
#define IFX_GTM_BRC_SRC1_DEST_EN_DEST13_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST13 */
#define IFX_GTM_BRC_SRC1_DEST_EN_DEST13_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST13 */
#define IFX_GTM_BRC_SRC1_DEST_EN_DEST13_OFF (13u)

/** \brief  Length for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST14 */
#define IFX_GTM_BRC_SRC1_DEST_EN_DEST14_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST14 */
#define IFX_GTM_BRC_SRC1_DEST_EN_DEST14_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST14 */
#define IFX_GTM_BRC_SRC1_DEST_EN_DEST14_OFF (14u)

/** \brief  Length for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST15 */
#define IFX_GTM_BRC_SRC1_DEST_EN_DEST15_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST15 */
#define IFX_GTM_BRC_SRC1_DEST_EN_DEST15_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST15 */
#define IFX_GTM_BRC_SRC1_DEST_EN_DEST15_OFF (15u)

/** \brief  Length for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST16 */
#define IFX_GTM_BRC_SRC1_DEST_EN_DEST16_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST16 */
#define IFX_GTM_BRC_SRC1_DEST_EN_DEST16_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST16 */
#define IFX_GTM_BRC_SRC1_DEST_EN_DEST16_OFF (16u)

/** \brief  Length for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST17 */
#define IFX_GTM_BRC_SRC1_DEST_EN_DEST17_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST17 */
#define IFX_GTM_BRC_SRC1_DEST_EN_DEST17_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST17 */
#define IFX_GTM_BRC_SRC1_DEST_EN_DEST17_OFF (17u)

/** \brief  Length for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST18 */
#define IFX_GTM_BRC_SRC1_DEST_EN_DEST18_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST18 */
#define IFX_GTM_BRC_SRC1_DEST_EN_DEST18_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST18 */
#define IFX_GTM_BRC_SRC1_DEST_EN_DEST18_OFF (18u)

/** \brief  Length for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST19 */
#define IFX_GTM_BRC_SRC1_DEST_EN_DEST19_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST19 */
#define IFX_GTM_BRC_SRC1_DEST_EN_DEST19_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST19 */
#define IFX_GTM_BRC_SRC1_DEST_EN_DEST19_OFF (19u)

/** \brief  Length for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST1 */
#define IFX_GTM_BRC_SRC1_DEST_EN_DEST1_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST1 */
#define IFX_GTM_BRC_SRC1_DEST_EN_DEST1_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST1 */
#define IFX_GTM_BRC_SRC1_DEST_EN_DEST1_OFF (1u)

/** \brief  Length for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST20 */
#define IFX_GTM_BRC_SRC1_DEST_EN_DEST20_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST20 */
#define IFX_GTM_BRC_SRC1_DEST_EN_DEST20_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST20 */
#define IFX_GTM_BRC_SRC1_DEST_EN_DEST20_OFF (20u)

/** \brief  Length for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST21 */
#define IFX_GTM_BRC_SRC1_DEST_EN_DEST21_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST21 */
#define IFX_GTM_BRC_SRC1_DEST_EN_DEST21_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST21 */
#define IFX_GTM_BRC_SRC1_DEST_EN_DEST21_OFF (21u)

/** \brief  Length for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST2 */
#define IFX_GTM_BRC_SRC1_DEST_EN_DEST2_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST2 */
#define IFX_GTM_BRC_SRC1_DEST_EN_DEST2_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST2 */
#define IFX_GTM_BRC_SRC1_DEST_EN_DEST2_OFF (2u)

/** \brief  Length for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST3 */
#define IFX_GTM_BRC_SRC1_DEST_EN_DEST3_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST3 */
#define IFX_GTM_BRC_SRC1_DEST_EN_DEST3_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST3 */
#define IFX_GTM_BRC_SRC1_DEST_EN_DEST3_OFF (3u)

/** \brief  Length for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST4 */
#define IFX_GTM_BRC_SRC1_DEST_EN_DEST4_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST4 */
#define IFX_GTM_BRC_SRC1_DEST_EN_DEST4_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST4 */
#define IFX_GTM_BRC_SRC1_DEST_EN_DEST4_OFF (4u)

/** \brief  Length for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST5 */
#define IFX_GTM_BRC_SRC1_DEST_EN_DEST5_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST5 */
#define IFX_GTM_BRC_SRC1_DEST_EN_DEST5_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST5 */
#define IFX_GTM_BRC_SRC1_DEST_EN_DEST5_OFF (5u)

/** \brief  Length for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST6 */
#define IFX_GTM_BRC_SRC1_DEST_EN_DEST6_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST6 */
#define IFX_GTM_BRC_SRC1_DEST_EN_DEST6_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST6 */
#define IFX_GTM_BRC_SRC1_DEST_EN_DEST6_OFF (6u)

/** \brief  Length for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST7 */
#define IFX_GTM_BRC_SRC1_DEST_EN_DEST7_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST7 */
#define IFX_GTM_BRC_SRC1_DEST_EN_DEST7_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST7 */
#define IFX_GTM_BRC_SRC1_DEST_EN_DEST7_OFF (7u)

/** \brief  Length for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST8 */
#define IFX_GTM_BRC_SRC1_DEST_EN_DEST8_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST8 */
#define IFX_GTM_BRC_SRC1_DEST_EN_DEST8_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST8 */
#define IFX_GTM_BRC_SRC1_DEST_EN_DEST8_OFF (8u)

/** \brief  Length for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST9 */
#define IFX_GTM_BRC_SRC1_DEST_EN_DEST9_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST9 */
#define IFX_GTM_BRC_SRC1_DEST_EN_DEST9_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_DEST9 */
#define IFX_GTM_BRC_SRC1_DEST_EN_DEST9_OFF (9u)

/** \brief  Length for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_TRASHBIN */
#define IFX_GTM_BRC_SRC1_DEST_EN_TRASHBIN_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_TRASHBIN */
#define IFX_GTM_BRC_SRC1_DEST_EN_TRASHBIN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC1_DEST_Bits.EN_TRASHBIN */
#define IFX_GTM_BRC_SRC1_DEST_EN_TRASHBIN_OFF (22u)

/** \brief  Length for Ifx_GTM_BRC_SRC2_ADDR_Bits.ADDR */
#define IFX_GTM_BRC_SRC2_ADDR_ADDR_LEN (9u)

/** \brief  Mask for Ifx_GTM_BRC_SRC2_ADDR_Bits.ADDR */
#define IFX_GTM_BRC_SRC2_ADDR_ADDR_MSK (0x1ffu)

/** \brief  Offset for Ifx_GTM_BRC_SRC2_ADDR_Bits.ADDR */
#define IFX_GTM_BRC_SRC2_ADDR_ADDR_OFF (0u)

/** \brief  Length for Ifx_GTM_BRC_SRC2_ADDR_Bits.BRC_MODE */
#define IFX_GTM_BRC_SRC2_ADDR_BRC_MODE_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC2_ADDR_Bits.BRC_MODE */
#define IFX_GTM_BRC_SRC2_ADDR_BRC_MODE_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC2_ADDR_Bits.BRC_MODE */
#define IFX_GTM_BRC_SRC2_ADDR_BRC_MODE_OFF (12u)

/** \brief  Length for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST0 */
#define IFX_GTM_BRC_SRC2_DEST_EN_DEST0_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST0 */
#define IFX_GTM_BRC_SRC2_DEST_EN_DEST0_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST0 */
#define IFX_GTM_BRC_SRC2_DEST_EN_DEST0_OFF (0u)

/** \brief  Length for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST10 */
#define IFX_GTM_BRC_SRC2_DEST_EN_DEST10_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST10 */
#define IFX_GTM_BRC_SRC2_DEST_EN_DEST10_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST10 */
#define IFX_GTM_BRC_SRC2_DEST_EN_DEST10_OFF (10u)

/** \brief  Length for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST11 */
#define IFX_GTM_BRC_SRC2_DEST_EN_DEST11_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST11 */
#define IFX_GTM_BRC_SRC2_DEST_EN_DEST11_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST11 */
#define IFX_GTM_BRC_SRC2_DEST_EN_DEST11_OFF (11u)

/** \brief  Length for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST12 */
#define IFX_GTM_BRC_SRC2_DEST_EN_DEST12_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST12 */
#define IFX_GTM_BRC_SRC2_DEST_EN_DEST12_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST12 */
#define IFX_GTM_BRC_SRC2_DEST_EN_DEST12_OFF (12u)

/** \brief  Length for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST13 */
#define IFX_GTM_BRC_SRC2_DEST_EN_DEST13_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST13 */
#define IFX_GTM_BRC_SRC2_DEST_EN_DEST13_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST13 */
#define IFX_GTM_BRC_SRC2_DEST_EN_DEST13_OFF (13u)

/** \brief  Length for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST14 */
#define IFX_GTM_BRC_SRC2_DEST_EN_DEST14_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST14 */
#define IFX_GTM_BRC_SRC2_DEST_EN_DEST14_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST14 */
#define IFX_GTM_BRC_SRC2_DEST_EN_DEST14_OFF (14u)

/** \brief  Length for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST15 */
#define IFX_GTM_BRC_SRC2_DEST_EN_DEST15_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST15 */
#define IFX_GTM_BRC_SRC2_DEST_EN_DEST15_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST15 */
#define IFX_GTM_BRC_SRC2_DEST_EN_DEST15_OFF (15u)

/** \brief  Length for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST16 */
#define IFX_GTM_BRC_SRC2_DEST_EN_DEST16_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST16 */
#define IFX_GTM_BRC_SRC2_DEST_EN_DEST16_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST16 */
#define IFX_GTM_BRC_SRC2_DEST_EN_DEST16_OFF (16u)

/** \brief  Length for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST17 */
#define IFX_GTM_BRC_SRC2_DEST_EN_DEST17_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST17 */
#define IFX_GTM_BRC_SRC2_DEST_EN_DEST17_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST17 */
#define IFX_GTM_BRC_SRC2_DEST_EN_DEST17_OFF (17u)

/** \brief  Length for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST18 */
#define IFX_GTM_BRC_SRC2_DEST_EN_DEST18_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST18 */
#define IFX_GTM_BRC_SRC2_DEST_EN_DEST18_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST18 */
#define IFX_GTM_BRC_SRC2_DEST_EN_DEST18_OFF (18u)

/** \brief  Length for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST19 */
#define IFX_GTM_BRC_SRC2_DEST_EN_DEST19_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST19 */
#define IFX_GTM_BRC_SRC2_DEST_EN_DEST19_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST19 */
#define IFX_GTM_BRC_SRC2_DEST_EN_DEST19_OFF (19u)

/** \brief  Length for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST1 */
#define IFX_GTM_BRC_SRC2_DEST_EN_DEST1_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST1 */
#define IFX_GTM_BRC_SRC2_DEST_EN_DEST1_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST1 */
#define IFX_GTM_BRC_SRC2_DEST_EN_DEST1_OFF (1u)

/** \brief  Length for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST20 */
#define IFX_GTM_BRC_SRC2_DEST_EN_DEST20_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST20 */
#define IFX_GTM_BRC_SRC2_DEST_EN_DEST20_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST20 */
#define IFX_GTM_BRC_SRC2_DEST_EN_DEST20_OFF (20u)

/** \brief  Length for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST21 */
#define IFX_GTM_BRC_SRC2_DEST_EN_DEST21_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST21 */
#define IFX_GTM_BRC_SRC2_DEST_EN_DEST21_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST21 */
#define IFX_GTM_BRC_SRC2_DEST_EN_DEST21_OFF (21u)

/** \brief  Length for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST2 */
#define IFX_GTM_BRC_SRC2_DEST_EN_DEST2_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST2 */
#define IFX_GTM_BRC_SRC2_DEST_EN_DEST2_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST2 */
#define IFX_GTM_BRC_SRC2_DEST_EN_DEST2_OFF (2u)

/** \brief  Length for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST3 */
#define IFX_GTM_BRC_SRC2_DEST_EN_DEST3_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST3 */
#define IFX_GTM_BRC_SRC2_DEST_EN_DEST3_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST3 */
#define IFX_GTM_BRC_SRC2_DEST_EN_DEST3_OFF (3u)

/** \brief  Length for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST4 */
#define IFX_GTM_BRC_SRC2_DEST_EN_DEST4_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST4 */
#define IFX_GTM_BRC_SRC2_DEST_EN_DEST4_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST4 */
#define IFX_GTM_BRC_SRC2_DEST_EN_DEST4_OFF (4u)

/** \brief  Length for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST5 */
#define IFX_GTM_BRC_SRC2_DEST_EN_DEST5_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST5 */
#define IFX_GTM_BRC_SRC2_DEST_EN_DEST5_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST5 */
#define IFX_GTM_BRC_SRC2_DEST_EN_DEST5_OFF (5u)

/** \brief  Length for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST6 */
#define IFX_GTM_BRC_SRC2_DEST_EN_DEST6_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST6 */
#define IFX_GTM_BRC_SRC2_DEST_EN_DEST6_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST6 */
#define IFX_GTM_BRC_SRC2_DEST_EN_DEST6_OFF (6u)

/** \brief  Length for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST7 */
#define IFX_GTM_BRC_SRC2_DEST_EN_DEST7_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST7 */
#define IFX_GTM_BRC_SRC2_DEST_EN_DEST7_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST7 */
#define IFX_GTM_BRC_SRC2_DEST_EN_DEST7_OFF (7u)

/** \brief  Length for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST8 */
#define IFX_GTM_BRC_SRC2_DEST_EN_DEST8_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST8 */
#define IFX_GTM_BRC_SRC2_DEST_EN_DEST8_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST8 */
#define IFX_GTM_BRC_SRC2_DEST_EN_DEST8_OFF (8u)

/** \brief  Length for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST9 */
#define IFX_GTM_BRC_SRC2_DEST_EN_DEST9_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST9 */
#define IFX_GTM_BRC_SRC2_DEST_EN_DEST9_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_DEST9 */
#define IFX_GTM_BRC_SRC2_DEST_EN_DEST9_OFF (9u)

/** \brief  Length for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_TRASHBIN */
#define IFX_GTM_BRC_SRC2_DEST_EN_TRASHBIN_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_TRASHBIN */
#define IFX_GTM_BRC_SRC2_DEST_EN_TRASHBIN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC2_DEST_Bits.EN_TRASHBIN */
#define IFX_GTM_BRC_SRC2_DEST_EN_TRASHBIN_OFF (22u)

/** \brief  Length for Ifx_GTM_BRC_SRC3_ADDR_Bits.ADDR */
#define IFX_GTM_BRC_SRC3_ADDR_ADDR_LEN (9u)

/** \brief  Mask for Ifx_GTM_BRC_SRC3_ADDR_Bits.ADDR */
#define IFX_GTM_BRC_SRC3_ADDR_ADDR_MSK (0x1ffu)

/** \brief  Offset for Ifx_GTM_BRC_SRC3_ADDR_Bits.ADDR */
#define IFX_GTM_BRC_SRC3_ADDR_ADDR_OFF (0u)

/** \brief  Length for Ifx_GTM_BRC_SRC3_ADDR_Bits.BRC_MODE */
#define IFX_GTM_BRC_SRC3_ADDR_BRC_MODE_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC3_ADDR_Bits.BRC_MODE */
#define IFX_GTM_BRC_SRC3_ADDR_BRC_MODE_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC3_ADDR_Bits.BRC_MODE */
#define IFX_GTM_BRC_SRC3_ADDR_BRC_MODE_OFF (12u)

/** \brief  Length for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST0 */
#define IFX_GTM_BRC_SRC3_DEST_EN_DEST0_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST0 */
#define IFX_GTM_BRC_SRC3_DEST_EN_DEST0_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST0 */
#define IFX_GTM_BRC_SRC3_DEST_EN_DEST0_OFF (0u)

/** \brief  Length for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST10 */
#define IFX_GTM_BRC_SRC3_DEST_EN_DEST10_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST10 */
#define IFX_GTM_BRC_SRC3_DEST_EN_DEST10_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST10 */
#define IFX_GTM_BRC_SRC3_DEST_EN_DEST10_OFF (10u)

/** \brief  Length for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST11 */
#define IFX_GTM_BRC_SRC3_DEST_EN_DEST11_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST11 */
#define IFX_GTM_BRC_SRC3_DEST_EN_DEST11_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST11 */
#define IFX_GTM_BRC_SRC3_DEST_EN_DEST11_OFF (11u)

/** \brief  Length for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST12 */
#define IFX_GTM_BRC_SRC3_DEST_EN_DEST12_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST12 */
#define IFX_GTM_BRC_SRC3_DEST_EN_DEST12_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST12 */
#define IFX_GTM_BRC_SRC3_DEST_EN_DEST12_OFF (12u)

/** \brief  Length for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST13 */
#define IFX_GTM_BRC_SRC3_DEST_EN_DEST13_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST13 */
#define IFX_GTM_BRC_SRC3_DEST_EN_DEST13_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST13 */
#define IFX_GTM_BRC_SRC3_DEST_EN_DEST13_OFF (13u)

/** \brief  Length for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST14 */
#define IFX_GTM_BRC_SRC3_DEST_EN_DEST14_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST14 */
#define IFX_GTM_BRC_SRC3_DEST_EN_DEST14_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST14 */
#define IFX_GTM_BRC_SRC3_DEST_EN_DEST14_OFF (14u)

/** \brief  Length for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST15 */
#define IFX_GTM_BRC_SRC3_DEST_EN_DEST15_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST15 */
#define IFX_GTM_BRC_SRC3_DEST_EN_DEST15_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST15 */
#define IFX_GTM_BRC_SRC3_DEST_EN_DEST15_OFF (15u)

/** \brief  Length for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST16 */
#define IFX_GTM_BRC_SRC3_DEST_EN_DEST16_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST16 */
#define IFX_GTM_BRC_SRC3_DEST_EN_DEST16_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST16 */
#define IFX_GTM_BRC_SRC3_DEST_EN_DEST16_OFF (16u)

/** \brief  Length for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST17 */
#define IFX_GTM_BRC_SRC3_DEST_EN_DEST17_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST17 */
#define IFX_GTM_BRC_SRC3_DEST_EN_DEST17_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST17 */
#define IFX_GTM_BRC_SRC3_DEST_EN_DEST17_OFF (17u)

/** \brief  Length for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST18 */
#define IFX_GTM_BRC_SRC3_DEST_EN_DEST18_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST18 */
#define IFX_GTM_BRC_SRC3_DEST_EN_DEST18_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST18 */
#define IFX_GTM_BRC_SRC3_DEST_EN_DEST18_OFF (18u)

/** \brief  Length for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST19 */
#define IFX_GTM_BRC_SRC3_DEST_EN_DEST19_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST19 */
#define IFX_GTM_BRC_SRC3_DEST_EN_DEST19_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST19 */
#define IFX_GTM_BRC_SRC3_DEST_EN_DEST19_OFF (19u)

/** \brief  Length for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST1 */
#define IFX_GTM_BRC_SRC3_DEST_EN_DEST1_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST1 */
#define IFX_GTM_BRC_SRC3_DEST_EN_DEST1_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST1 */
#define IFX_GTM_BRC_SRC3_DEST_EN_DEST1_OFF (1u)

/** \brief  Length for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST20 */
#define IFX_GTM_BRC_SRC3_DEST_EN_DEST20_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST20 */
#define IFX_GTM_BRC_SRC3_DEST_EN_DEST20_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST20 */
#define IFX_GTM_BRC_SRC3_DEST_EN_DEST20_OFF (20u)

/** \brief  Length for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST21 */
#define IFX_GTM_BRC_SRC3_DEST_EN_DEST21_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST21 */
#define IFX_GTM_BRC_SRC3_DEST_EN_DEST21_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST21 */
#define IFX_GTM_BRC_SRC3_DEST_EN_DEST21_OFF (21u)

/** \brief  Length for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST2 */
#define IFX_GTM_BRC_SRC3_DEST_EN_DEST2_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST2 */
#define IFX_GTM_BRC_SRC3_DEST_EN_DEST2_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST2 */
#define IFX_GTM_BRC_SRC3_DEST_EN_DEST2_OFF (2u)

/** \brief  Length for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST3 */
#define IFX_GTM_BRC_SRC3_DEST_EN_DEST3_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST3 */
#define IFX_GTM_BRC_SRC3_DEST_EN_DEST3_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST3 */
#define IFX_GTM_BRC_SRC3_DEST_EN_DEST3_OFF (3u)

/** \brief  Length for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST4 */
#define IFX_GTM_BRC_SRC3_DEST_EN_DEST4_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST4 */
#define IFX_GTM_BRC_SRC3_DEST_EN_DEST4_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST4 */
#define IFX_GTM_BRC_SRC3_DEST_EN_DEST4_OFF (4u)

/** \brief  Length for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST5 */
#define IFX_GTM_BRC_SRC3_DEST_EN_DEST5_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST5 */
#define IFX_GTM_BRC_SRC3_DEST_EN_DEST5_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST5 */
#define IFX_GTM_BRC_SRC3_DEST_EN_DEST5_OFF (5u)

/** \brief  Length for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST6 */
#define IFX_GTM_BRC_SRC3_DEST_EN_DEST6_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST6 */
#define IFX_GTM_BRC_SRC3_DEST_EN_DEST6_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST6 */
#define IFX_GTM_BRC_SRC3_DEST_EN_DEST6_OFF (6u)

/** \brief  Length for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST7 */
#define IFX_GTM_BRC_SRC3_DEST_EN_DEST7_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST7 */
#define IFX_GTM_BRC_SRC3_DEST_EN_DEST7_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST7 */
#define IFX_GTM_BRC_SRC3_DEST_EN_DEST7_OFF (7u)

/** \brief  Length for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST8 */
#define IFX_GTM_BRC_SRC3_DEST_EN_DEST8_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST8 */
#define IFX_GTM_BRC_SRC3_DEST_EN_DEST8_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST8 */
#define IFX_GTM_BRC_SRC3_DEST_EN_DEST8_OFF (8u)

/** \brief  Length for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST9 */
#define IFX_GTM_BRC_SRC3_DEST_EN_DEST9_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST9 */
#define IFX_GTM_BRC_SRC3_DEST_EN_DEST9_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_DEST9 */
#define IFX_GTM_BRC_SRC3_DEST_EN_DEST9_OFF (9u)

/** \brief  Length for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_TRASHBIN */
#define IFX_GTM_BRC_SRC3_DEST_EN_TRASHBIN_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_TRASHBIN */
#define IFX_GTM_BRC_SRC3_DEST_EN_TRASHBIN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC3_DEST_Bits.EN_TRASHBIN */
#define IFX_GTM_BRC_SRC3_DEST_EN_TRASHBIN_OFF (22u)

/** \brief  Length for Ifx_GTM_BRC_SRC4_ADDR_Bits.ADDR */
#define IFX_GTM_BRC_SRC4_ADDR_ADDR_LEN (9u)

/** \brief  Mask for Ifx_GTM_BRC_SRC4_ADDR_Bits.ADDR */
#define IFX_GTM_BRC_SRC4_ADDR_ADDR_MSK (0x1ffu)

/** \brief  Offset for Ifx_GTM_BRC_SRC4_ADDR_Bits.ADDR */
#define IFX_GTM_BRC_SRC4_ADDR_ADDR_OFF (0u)

/** \brief  Length for Ifx_GTM_BRC_SRC4_ADDR_Bits.BRC_MODE */
#define IFX_GTM_BRC_SRC4_ADDR_BRC_MODE_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC4_ADDR_Bits.BRC_MODE */
#define IFX_GTM_BRC_SRC4_ADDR_BRC_MODE_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC4_ADDR_Bits.BRC_MODE */
#define IFX_GTM_BRC_SRC4_ADDR_BRC_MODE_OFF (12u)

/** \brief  Length for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST0 */
#define IFX_GTM_BRC_SRC4_DEST_EN_DEST0_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST0 */
#define IFX_GTM_BRC_SRC4_DEST_EN_DEST0_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST0 */
#define IFX_GTM_BRC_SRC4_DEST_EN_DEST0_OFF (0u)

/** \brief  Length for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST10 */
#define IFX_GTM_BRC_SRC4_DEST_EN_DEST10_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST10 */
#define IFX_GTM_BRC_SRC4_DEST_EN_DEST10_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST10 */
#define IFX_GTM_BRC_SRC4_DEST_EN_DEST10_OFF (10u)

/** \brief  Length for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST11 */
#define IFX_GTM_BRC_SRC4_DEST_EN_DEST11_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST11 */
#define IFX_GTM_BRC_SRC4_DEST_EN_DEST11_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST11 */
#define IFX_GTM_BRC_SRC4_DEST_EN_DEST11_OFF (11u)

/** \brief  Length for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST12 */
#define IFX_GTM_BRC_SRC4_DEST_EN_DEST12_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST12 */
#define IFX_GTM_BRC_SRC4_DEST_EN_DEST12_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST12 */
#define IFX_GTM_BRC_SRC4_DEST_EN_DEST12_OFF (12u)

/** \brief  Length for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST13 */
#define IFX_GTM_BRC_SRC4_DEST_EN_DEST13_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST13 */
#define IFX_GTM_BRC_SRC4_DEST_EN_DEST13_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST13 */
#define IFX_GTM_BRC_SRC4_DEST_EN_DEST13_OFF (13u)

/** \brief  Length for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST14 */
#define IFX_GTM_BRC_SRC4_DEST_EN_DEST14_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST14 */
#define IFX_GTM_BRC_SRC4_DEST_EN_DEST14_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST14 */
#define IFX_GTM_BRC_SRC4_DEST_EN_DEST14_OFF (14u)

/** \brief  Length for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST15 */
#define IFX_GTM_BRC_SRC4_DEST_EN_DEST15_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST15 */
#define IFX_GTM_BRC_SRC4_DEST_EN_DEST15_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST15 */
#define IFX_GTM_BRC_SRC4_DEST_EN_DEST15_OFF (15u)

/** \brief  Length for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST16 */
#define IFX_GTM_BRC_SRC4_DEST_EN_DEST16_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST16 */
#define IFX_GTM_BRC_SRC4_DEST_EN_DEST16_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST16 */
#define IFX_GTM_BRC_SRC4_DEST_EN_DEST16_OFF (16u)

/** \brief  Length for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST17 */
#define IFX_GTM_BRC_SRC4_DEST_EN_DEST17_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST17 */
#define IFX_GTM_BRC_SRC4_DEST_EN_DEST17_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST17 */
#define IFX_GTM_BRC_SRC4_DEST_EN_DEST17_OFF (17u)

/** \brief  Length for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST18 */
#define IFX_GTM_BRC_SRC4_DEST_EN_DEST18_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST18 */
#define IFX_GTM_BRC_SRC4_DEST_EN_DEST18_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST18 */
#define IFX_GTM_BRC_SRC4_DEST_EN_DEST18_OFF (18u)

/** \brief  Length for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST19 */
#define IFX_GTM_BRC_SRC4_DEST_EN_DEST19_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST19 */
#define IFX_GTM_BRC_SRC4_DEST_EN_DEST19_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST19 */
#define IFX_GTM_BRC_SRC4_DEST_EN_DEST19_OFF (19u)

/** \brief  Length for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST1 */
#define IFX_GTM_BRC_SRC4_DEST_EN_DEST1_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST1 */
#define IFX_GTM_BRC_SRC4_DEST_EN_DEST1_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST1 */
#define IFX_GTM_BRC_SRC4_DEST_EN_DEST1_OFF (1u)

/** \brief  Length for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST20 */
#define IFX_GTM_BRC_SRC4_DEST_EN_DEST20_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST20 */
#define IFX_GTM_BRC_SRC4_DEST_EN_DEST20_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST20 */
#define IFX_GTM_BRC_SRC4_DEST_EN_DEST20_OFF (20u)

/** \brief  Length for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST21 */
#define IFX_GTM_BRC_SRC4_DEST_EN_DEST21_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST21 */
#define IFX_GTM_BRC_SRC4_DEST_EN_DEST21_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST21 */
#define IFX_GTM_BRC_SRC4_DEST_EN_DEST21_OFF (21u)

/** \brief  Length for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST2 */
#define IFX_GTM_BRC_SRC4_DEST_EN_DEST2_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST2 */
#define IFX_GTM_BRC_SRC4_DEST_EN_DEST2_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST2 */
#define IFX_GTM_BRC_SRC4_DEST_EN_DEST2_OFF (2u)

/** \brief  Length for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST3 */
#define IFX_GTM_BRC_SRC4_DEST_EN_DEST3_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST3 */
#define IFX_GTM_BRC_SRC4_DEST_EN_DEST3_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST3 */
#define IFX_GTM_BRC_SRC4_DEST_EN_DEST3_OFF (3u)

/** \brief  Length for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST4 */
#define IFX_GTM_BRC_SRC4_DEST_EN_DEST4_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST4 */
#define IFX_GTM_BRC_SRC4_DEST_EN_DEST4_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST4 */
#define IFX_GTM_BRC_SRC4_DEST_EN_DEST4_OFF (4u)

/** \brief  Length for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST5 */
#define IFX_GTM_BRC_SRC4_DEST_EN_DEST5_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST5 */
#define IFX_GTM_BRC_SRC4_DEST_EN_DEST5_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST5 */
#define IFX_GTM_BRC_SRC4_DEST_EN_DEST5_OFF (5u)

/** \brief  Length for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST6 */
#define IFX_GTM_BRC_SRC4_DEST_EN_DEST6_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST6 */
#define IFX_GTM_BRC_SRC4_DEST_EN_DEST6_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST6 */
#define IFX_GTM_BRC_SRC4_DEST_EN_DEST6_OFF (6u)

/** \brief  Length for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST7 */
#define IFX_GTM_BRC_SRC4_DEST_EN_DEST7_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST7 */
#define IFX_GTM_BRC_SRC4_DEST_EN_DEST7_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST7 */
#define IFX_GTM_BRC_SRC4_DEST_EN_DEST7_OFF (7u)

/** \brief  Length for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST8 */
#define IFX_GTM_BRC_SRC4_DEST_EN_DEST8_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST8 */
#define IFX_GTM_BRC_SRC4_DEST_EN_DEST8_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST8 */
#define IFX_GTM_BRC_SRC4_DEST_EN_DEST8_OFF (8u)

/** \brief  Length for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST9 */
#define IFX_GTM_BRC_SRC4_DEST_EN_DEST9_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST9 */
#define IFX_GTM_BRC_SRC4_DEST_EN_DEST9_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_DEST9 */
#define IFX_GTM_BRC_SRC4_DEST_EN_DEST9_OFF (9u)

/** \brief  Length for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_TRASHBIN */
#define IFX_GTM_BRC_SRC4_DEST_EN_TRASHBIN_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_TRASHBIN */
#define IFX_GTM_BRC_SRC4_DEST_EN_TRASHBIN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC4_DEST_Bits.EN_TRASHBIN */
#define IFX_GTM_BRC_SRC4_DEST_EN_TRASHBIN_OFF (22u)

/** \brief  Length for Ifx_GTM_BRC_SRC5_ADDR_Bits.ADDR */
#define IFX_GTM_BRC_SRC5_ADDR_ADDR_LEN (9u)

/** \brief  Mask for Ifx_GTM_BRC_SRC5_ADDR_Bits.ADDR */
#define IFX_GTM_BRC_SRC5_ADDR_ADDR_MSK (0x1ffu)

/** \brief  Offset for Ifx_GTM_BRC_SRC5_ADDR_Bits.ADDR */
#define IFX_GTM_BRC_SRC5_ADDR_ADDR_OFF (0u)

/** \brief  Length for Ifx_GTM_BRC_SRC5_ADDR_Bits.BRC_MODE */
#define IFX_GTM_BRC_SRC5_ADDR_BRC_MODE_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC5_ADDR_Bits.BRC_MODE */
#define IFX_GTM_BRC_SRC5_ADDR_BRC_MODE_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC5_ADDR_Bits.BRC_MODE */
#define IFX_GTM_BRC_SRC5_ADDR_BRC_MODE_OFF (12u)

/** \brief  Length for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST0 */
#define IFX_GTM_BRC_SRC5_DEST_EN_DEST0_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST0 */
#define IFX_GTM_BRC_SRC5_DEST_EN_DEST0_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST0 */
#define IFX_GTM_BRC_SRC5_DEST_EN_DEST0_OFF (0u)

/** \brief  Length for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST10 */
#define IFX_GTM_BRC_SRC5_DEST_EN_DEST10_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST10 */
#define IFX_GTM_BRC_SRC5_DEST_EN_DEST10_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST10 */
#define IFX_GTM_BRC_SRC5_DEST_EN_DEST10_OFF (10u)

/** \brief  Length for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST11 */
#define IFX_GTM_BRC_SRC5_DEST_EN_DEST11_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST11 */
#define IFX_GTM_BRC_SRC5_DEST_EN_DEST11_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST11 */
#define IFX_GTM_BRC_SRC5_DEST_EN_DEST11_OFF (11u)

/** \brief  Length for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST12 */
#define IFX_GTM_BRC_SRC5_DEST_EN_DEST12_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST12 */
#define IFX_GTM_BRC_SRC5_DEST_EN_DEST12_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST12 */
#define IFX_GTM_BRC_SRC5_DEST_EN_DEST12_OFF (12u)

/** \brief  Length for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST13 */
#define IFX_GTM_BRC_SRC5_DEST_EN_DEST13_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST13 */
#define IFX_GTM_BRC_SRC5_DEST_EN_DEST13_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST13 */
#define IFX_GTM_BRC_SRC5_DEST_EN_DEST13_OFF (13u)

/** \brief  Length for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST14 */
#define IFX_GTM_BRC_SRC5_DEST_EN_DEST14_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST14 */
#define IFX_GTM_BRC_SRC5_DEST_EN_DEST14_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST14 */
#define IFX_GTM_BRC_SRC5_DEST_EN_DEST14_OFF (14u)

/** \brief  Length for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST15 */
#define IFX_GTM_BRC_SRC5_DEST_EN_DEST15_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST15 */
#define IFX_GTM_BRC_SRC5_DEST_EN_DEST15_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST15 */
#define IFX_GTM_BRC_SRC5_DEST_EN_DEST15_OFF (15u)

/** \brief  Length for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST16 */
#define IFX_GTM_BRC_SRC5_DEST_EN_DEST16_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST16 */
#define IFX_GTM_BRC_SRC5_DEST_EN_DEST16_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST16 */
#define IFX_GTM_BRC_SRC5_DEST_EN_DEST16_OFF (16u)

/** \brief  Length for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST17 */
#define IFX_GTM_BRC_SRC5_DEST_EN_DEST17_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST17 */
#define IFX_GTM_BRC_SRC5_DEST_EN_DEST17_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST17 */
#define IFX_GTM_BRC_SRC5_DEST_EN_DEST17_OFF (17u)

/** \brief  Length for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST18 */
#define IFX_GTM_BRC_SRC5_DEST_EN_DEST18_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST18 */
#define IFX_GTM_BRC_SRC5_DEST_EN_DEST18_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST18 */
#define IFX_GTM_BRC_SRC5_DEST_EN_DEST18_OFF (18u)

/** \brief  Length for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST19 */
#define IFX_GTM_BRC_SRC5_DEST_EN_DEST19_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST19 */
#define IFX_GTM_BRC_SRC5_DEST_EN_DEST19_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST19 */
#define IFX_GTM_BRC_SRC5_DEST_EN_DEST19_OFF (19u)

/** \brief  Length for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST1 */
#define IFX_GTM_BRC_SRC5_DEST_EN_DEST1_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST1 */
#define IFX_GTM_BRC_SRC5_DEST_EN_DEST1_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST1 */
#define IFX_GTM_BRC_SRC5_DEST_EN_DEST1_OFF (1u)

/** \brief  Length for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST20 */
#define IFX_GTM_BRC_SRC5_DEST_EN_DEST20_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST20 */
#define IFX_GTM_BRC_SRC5_DEST_EN_DEST20_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST20 */
#define IFX_GTM_BRC_SRC5_DEST_EN_DEST20_OFF (20u)

/** \brief  Length for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST21 */
#define IFX_GTM_BRC_SRC5_DEST_EN_DEST21_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST21 */
#define IFX_GTM_BRC_SRC5_DEST_EN_DEST21_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST21 */
#define IFX_GTM_BRC_SRC5_DEST_EN_DEST21_OFF (21u)

/** \brief  Length for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST2 */
#define IFX_GTM_BRC_SRC5_DEST_EN_DEST2_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST2 */
#define IFX_GTM_BRC_SRC5_DEST_EN_DEST2_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST2 */
#define IFX_GTM_BRC_SRC5_DEST_EN_DEST2_OFF (2u)

/** \brief  Length for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST3 */
#define IFX_GTM_BRC_SRC5_DEST_EN_DEST3_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST3 */
#define IFX_GTM_BRC_SRC5_DEST_EN_DEST3_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST3 */
#define IFX_GTM_BRC_SRC5_DEST_EN_DEST3_OFF (3u)

/** \brief  Length for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST4 */
#define IFX_GTM_BRC_SRC5_DEST_EN_DEST4_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST4 */
#define IFX_GTM_BRC_SRC5_DEST_EN_DEST4_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST4 */
#define IFX_GTM_BRC_SRC5_DEST_EN_DEST4_OFF (4u)

/** \brief  Length for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST5 */
#define IFX_GTM_BRC_SRC5_DEST_EN_DEST5_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST5 */
#define IFX_GTM_BRC_SRC5_DEST_EN_DEST5_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST5 */
#define IFX_GTM_BRC_SRC5_DEST_EN_DEST5_OFF (5u)

/** \brief  Length for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST6 */
#define IFX_GTM_BRC_SRC5_DEST_EN_DEST6_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST6 */
#define IFX_GTM_BRC_SRC5_DEST_EN_DEST6_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST6 */
#define IFX_GTM_BRC_SRC5_DEST_EN_DEST6_OFF (6u)

/** \brief  Length for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST7 */
#define IFX_GTM_BRC_SRC5_DEST_EN_DEST7_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST7 */
#define IFX_GTM_BRC_SRC5_DEST_EN_DEST7_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST7 */
#define IFX_GTM_BRC_SRC5_DEST_EN_DEST7_OFF (7u)

/** \brief  Length for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST8 */
#define IFX_GTM_BRC_SRC5_DEST_EN_DEST8_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST8 */
#define IFX_GTM_BRC_SRC5_DEST_EN_DEST8_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST8 */
#define IFX_GTM_BRC_SRC5_DEST_EN_DEST8_OFF (8u)

/** \brief  Length for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST9 */
#define IFX_GTM_BRC_SRC5_DEST_EN_DEST9_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST9 */
#define IFX_GTM_BRC_SRC5_DEST_EN_DEST9_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_DEST9 */
#define IFX_GTM_BRC_SRC5_DEST_EN_DEST9_OFF (9u)

/** \brief  Length for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_TRASHBIN */
#define IFX_GTM_BRC_SRC5_DEST_EN_TRASHBIN_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_TRASHBIN */
#define IFX_GTM_BRC_SRC5_DEST_EN_TRASHBIN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC5_DEST_Bits.EN_TRASHBIN */
#define IFX_GTM_BRC_SRC5_DEST_EN_TRASHBIN_OFF (22u)

/** \brief  Length for Ifx_GTM_BRC_SRC6_ADDR_Bits.ADDR */
#define IFX_GTM_BRC_SRC6_ADDR_ADDR_LEN (9u)

/** \brief  Mask for Ifx_GTM_BRC_SRC6_ADDR_Bits.ADDR */
#define IFX_GTM_BRC_SRC6_ADDR_ADDR_MSK (0x1ffu)

/** \brief  Offset for Ifx_GTM_BRC_SRC6_ADDR_Bits.ADDR */
#define IFX_GTM_BRC_SRC6_ADDR_ADDR_OFF (0u)

/** \brief  Length for Ifx_GTM_BRC_SRC6_ADDR_Bits.BRC_MODE */
#define IFX_GTM_BRC_SRC6_ADDR_BRC_MODE_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC6_ADDR_Bits.BRC_MODE */
#define IFX_GTM_BRC_SRC6_ADDR_BRC_MODE_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC6_ADDR_Bits.BRC_MODE */
#define IFX_GTM_BRC_SRC6_ADDR_BRC_MODE_OFF (12u)

/** \brief  Length for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST0 */
#define IFX_GTM_BRC_SRC6_DEST_EN_DEST0_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST0 */
#define IFX_GTM_BRC_SRC6_DEST_EN_DEST0_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST0 */
#define IFX_GTM_BRC_SRC6_DEST_EN_DEST0_OFF (0u)

/** \brief  Length for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST10 */
#define IFX_GTM_BRC_SRC6_DEST_EN_DEST10_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST10 */
#define IFX_GTM_BRC_SRC6_DEST_EN_DEST10_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST10 */
#define IFX_GTM_BRC_SRC6_DEST_EN_DEST10_OFF (10u)

/** \brief  Length for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST11 */
#define IFX_GTM_BRC_SRC6_DEST_EN_DEST11_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST11 */
#define IFX_GTM_BRC_SRC6_DEST_EN_DEST11_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST11 */
#define IFX_GTM_BRC_SRC6_DEST_EN_DEST11_OFF (11u)

/** \brief  Length for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST12 */
#define IFX_GTM_BRC_SRC6_DEST_EN_DEST12_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST12 */
#define IFX_GTM_BRC_SRC6_DEST_EN_DEST12_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST12 */
#define IFX_GTM_BRC_SRC6_DEST_EN_DEST12_OFF (12u)

/** \brief  Length for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST13 */
#define IFX_GTM_BRC_SRC6_DEST_EN_DEST13_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST13 */
#define IFX_GTM_BRC_SRC6_DEST_EN_DEST13_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST13 */
#define IFX_GTM_BRC_SRC6_DEST_EN_DEST13_OFF (13u)

/** \brief  Length for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST14 */
#define IFX_GTM_BRC_SRC6_DEST_EN_DEST14_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST14 */
#define IFX_GTM_BRC_SRC6_DEST_EN_DEST14_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST14 */
#define IFX_GTM_BRC_SRC6_DEST_EN_DEST14_OFF (14u)

/** \brief  Length for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST15 */
#define IFX_GTM_BRC_SRC6_DEST_EN_DEST15_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST15 */
#define IFX_GTM_BRC_SRC6_DEST_EN_DEST15_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST15 */
#define IFX_GTM_BRC_SRC6_DEST_EN_DEST15_OFF (15u)

/** \brief  Length for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST16 */
#define IFX_GTM_BRC_SRC6_DEST_EN_DEST16_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST16 */
#define IFX_GTM_BRC_SRC6_DEST_EN_DEST16_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST16 */
#define IFX_GTM_BRC_SRC6_DEST_EN_DEST16_OFF (16u)

/** \brief  Length for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST17 */
#define IFX_GTM_BRC_SRC6_DEST_EN_DEST17_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST17 */
#define IFX_GTM_BRC_SRC6_DEST_EN_DEST17_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST17 */
#define IFX_GTM_BRC_SRC6_DEST_EN_DEST17_OFF (17u)

/** \brief  Length for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST18 */
#define IFX_GTM_BRC_SRC6_DEST_EN_DEST18_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST18 */
#define IFX_GTM_BRC_SRC6_DEST_EN_DEST18_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST18 */
#define IFX_GTM_BRC_SRC6_DEST_EN_DEST18_OFF (18u)

/** \brief  Length for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST19 */
#define IFX_GTM_BRC_SRC6_DEST_EN_DEST19_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST19 */
#define IFX_GTM_BRC_SRC6_DEST_EN_DEST19_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST19 */
#define IFX_GTM_BRC_SRC6_DEST_EN_DEST19_OFF (19u)

/** \brief  Length for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST1 */
#define IFX_GTM_BRC_SRC6_DEST_EN_DEST1_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST1 */
#define IFX_GTM_BRC_SRC6_DEST_EN_DEST1_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST1 */
#define IFX_GTM_BRC_SRC6_DEST_EN_DEST1_OFF (1u)

/** \brief  Length for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST20 */
#define IFX_GTM_BRC_SRC6_DEST_EN_DEST20_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST20 */
#define IFX_GTM_BRC_SRC6_DEST_EN_DEST20_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST20 */
#define IFX_GTM_BRC_SRC6_DEST_EN_DEST20_OFF (20u)

/** \brief  Length for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST21 */
#define IFX_GTM_BRC_SRC6_DEST_EN_DEST21_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST21 */
#define IFX_GTM_BRC_SRC6_DEST_EN_DEST21_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST21 */
#define IFX_GTM_BRC_SRC6_DEST_EN_DEST21_OFF (21u)

/** \brief  Length for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST2 */
#define IFX_GTM_BRC_SRC6_DEST_EN_DEST2_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST2 */
#define IFX_GTM_BRC_SRC6_DEST_EN_DEST2_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST2 */
#define IFX_GTM_BRC_SRC6_DEST_EN_DEST2_OFF (2u)

/** \brief  Length for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST3 */
#define IFX_GTM_BRC_SRC6_DEST_EN_DEST3_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST3 */
#define IFX_GTM_BRC_SRC6_DEST_EN_DEST3_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST3 */
#define IFX_GTM_BRC_SRC6_DEST_EN_DEST3_OFF (3u)

/** \brief  Length for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST4 */
#define IFX_GTM_BRC_SRC6_DEST_EN_DEST4_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST4 */
#define IFX_GTM_BRC_SRC6_DEST_EN_DEST4_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST4 */
#define IFX_GTM_BRC_SRC6_DEST_EN_DEST4_OFF (4u)

/** \brief  Length for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST5 */
#define IFX_GTM_BRC_SRC6_DEST_EN_DEST5_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST5 */
#define IFX_GTM_BRC_SRC6_DEST_EN_DEST5_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST5 */
#define IFX_GTM_BRC_SRC6_DEST_EN_DEST5_OFF (5u)

/** \brief  Length for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST6 */
#define IFX_GTM_BRC_SRC6_DEST_EN_DEST6_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST6 */
#define IFX_GTM_BRC_SRC6_DEST_EN_DEST6_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST6 */
#define IFX_GTM_BRC_SRC6_DEST_EN_DEST6_OFF (6u)

/** \brief  Length for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST7 */
#define IFX_GTM_BRC_SRC6_DEST_EN_DEST7_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST7 */
#define IFX_GTM_BRC_SRC6_DEST_EN_DEST7_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST7 */
#define IFX_GTM_BRC_SRC6_DEST_EN_DEST7_OFF (7u)

/** \brief  Length for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST8 */
#define IFX_GTM_BRC_SRC6_DEST_EN_DEST8_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST8 */
#define IFX_GTM_BRC_SRC6_DEST_EN_DEST8_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST8 */
#define IFX_GTM_BRC_SRC6_DEST_EN_DEST8_OFF (8u)

/** \brief  Length for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST9 */
#define IFX_GTM_BRC_SRC6_DEST_EN_DEST9_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST9 */
#define IFX_GTM_BRC_SRC6_DEST_EN_DEST9_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_DEST9 */
#define IFX_GTM_BRC_SRC6_DEST_EN_DEST9_OFF (9u)

/** \brief  Length for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_TRASHBIN */
#define IFX_GTM_BRC_SRC6_DEST_EN_TRASHBIN_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_TRASHBIN */
#define IFX_GTM_BRC_SRC6_DEST_EN_TRASHBIN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC6_DEST_Bits.EN_TRASHBIN */
#define IFX_GTM_BRC_SRC6_DEST_EN_TRASHBIN_OFF (22u)

/** \brief  Length for Ifx_GTM_BRC_SRC7_ADDR_Bits.ADDR */
#define IFX_GTM_BRC_SRC7_ADDR_ADDR_LEN (9u)

/** \brief  Mask for Ifx_GTM_BRC_SRC7_ADDR_Bits.ADDR */
#define IFX_GTM_BRC_SRC7_ADDR_ADDR_MSK (0x1ffu)

/** \brief  Offset for Ifx_GTM_BRC_SRC7_ADDR_Bits.ADDR */
#define IFX_GTM_BRC_SRC7_ADDR_ADDR_OFF (0u)

/** \brief  Length for Ifx_GTM_BRC_SRC7_ADDR_Bits.BRC_MODE */
#define IFX_GTM_BRC_SRC7_ADDR_BRC_MODE_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC7_ADDR_Bits.BRC_MODE */
#define IFX_GTM_BRC_SRC7_ADDR_BRC_MODE_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC7_ADDR_Bits.BRC_MODE */
#define IFX_GTM_BRC_SRC7_ADDR_BRC_MODE_OFF (12u)

/** \brief  Length for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST0 */
#define IFX_GTM_BRC_SRC7_DEST_EN_DEST0_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST0 */
#define IFX_GTM_BRC_SRC7_DEST_EN_DEST0_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST0 */
#define IFX_GTM_BRC_SRC7_DEST_EN_DEST0_OFF (0u)

/** \brief  Length for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST10 */
#define IFX_GTM_BRC_SRC7_DEST_EN_DEST10_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST10 */
#define IFX_GTM_BRC_SRC7_DEST_EN_DEST10_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST10 */
#define IFX_GTM_BRC_SRC7_DEST_EN_DEST10_OFF (10u)

/** \brief  Length for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST11 */
#define IFX_GTM_BRC_SRC7_DEST_EN_DEST11_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST11 */
#define IFX_GTM_BRC_SRC7_DEST_EN_DEST11_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST11 */
#define IFX_GTM_BRC_SRC7_DEST_EN_DEST11_OFF (11u)

/** \brief  Length for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST12 */
#define IFX_GTM_BRC_SRC7_DEST_EN_DEST12_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST12 */
#define IFX_GTM_BRC_SRC7_DEST_EN_DEST12_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST12 */
#define IFX_GTM_BRC_SRC7_DEST_EN_DEST12_OFF (12u)

/** \brief  Length for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST13 */
#define IFX_GTM_BRC_SRC7_DEST_EN_DEST13_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST13 */
#define IFX_GTM_BRC_SRC7_DEST_EN_DEST13_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST13 */
#define IFX_GTM_BRC_SRC7_DEST_EN_DEST13_OFF (13u)

/** \brief  Length for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST14 */
#define IFX_GTM_BRC_SRC7_DEST_EN_DEST14_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST14 */
#define IFX_GTM_BRC_SRC7_DEST_EN_DEST14_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST14 */
#define IFX_GTM_BRC_SRC7_DEST_EN_DEST14_OFF (14u)

/** \brief  Length for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST15 */
#define IFX_GTM_BRC_SRC7_DEST_EN_DEST15_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST15 */
#define IFX_GTM_BRC_SRC7_DEST_EN_DEST15_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST15 */
#define IFX_GTM_BRC_SRC7_DEST_EN_DEST15_OFF (15u)

/** \brief  Length for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST16 */
#define IFX_GTM_BRC_SRC7_DEST_EN_DEST16_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST16 */
#define IFX_GTM_BRC_SRC7_DEST_EN_DEST16_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST16 */
#define IFX_GTM_BRC_SRC7_DEST_EN_DEST16_OFF (16u)

/** \brief  Length for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST17 */
#define IFX_GTM_BRC_SRC7_DEST_EN_DEST17_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST17 */
#define IFX_GTM_BRC_SRC7_DEST_EN_DEST17_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST17 */
#define IFX_GTM_BRC_SRC7_DEST_EN_DEST17_OFF (17u)

/** \brief  Length for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST18 */
#define IFX_GTM_BRC_SRC7_DEST_EN_DEST18_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST18 */
#define IFX_GTM_BRC_SRC7_DEST_EN_DEST18_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST18 */
#define IFX_GTM_BRC_SRC7_DEST_EN_DEST18_OFF (18u)

/** \brief  Length for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST19 */
#define IFX_GTM_BRC_SRC7_DEST_EN_DEST19_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST19 */
#define IFX_GTM_BRC_SRC7_DEST_EN_DEST19_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST19 */
#define IFX_GTM_BRC_SRC7_DEST_EN_DEST19_OFF (19u)

/** \brief  Length for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST1 */
#define IFX_GTM_BRC_SRC7_DEST_EN_DEST1_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST1 */
#define IFX_GTM_BRC_SRC7_DEST_EN_DEST1_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST1 */
#define IFX_GTM_BRC_SRC7_DEST_EN_DEST1_OFF (1u)

/** \brief  Length for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST20 */
#define IFX_GTM_BRC_SRC7_DEST_EN_DEST20_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST20 */
#define IFX_GTM_BRC_SRC7_DEST_EN_DEST20_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST20 */
#define IFX_GTM_BRC_SRC7_DEST_EN_DEST20_OFF (20u)

/** \brief  Length for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST21 */
#define IFX_GTM_BRC_SRC7_DEST_EN_DEST21_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST21 */
#define IFX_GTM_BRC_SRC7_DEST_EN_DEST21_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST21 */
#define IFX_GTM_BRC_SRC7_DEST_EN_DEST21_OFF (21u)

/** \brief  Length for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST2 */
#define IFX_GTM_BRC_SRC7_DEST_EN_DEST2_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST2 */
#define IFX_GTM_BRC_SRC7_DEST_EN_DEST2_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST2 */
#define IFX_GTM_BRC_SRC7_DEST_EN_DEST2_OFF (2u)

/** \brief  Length for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST3 */
#define IFX_GTM_BRC_SRC7_DEST_EN_DEST3_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST3 */
#define IFX_GTM_BRC_SRC7_DEST_EN_DEST3_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST3 */
#define IFX_GTM_BRC_SRC7_DEST_EN_DEST3_OFF (3u)

/** \brief  Length for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST4 */
#define IFX_GTM_BRC_SRC7_DEST_EN_DEST4_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST4 */
#define IFX_GTM_BRC_SRC7_DEST_EN_DEST4_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST4 */
#define IFX_GTM_BRC_SRC7_DEST_EN_DEST4_OFF (4u)

/** \brief  Length for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST5 */
#define IFX_GTM_BRC_SRC7_DEST_EN_DEST5_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST5 */
#define IFX_GTM_BRC_SRC7_DEST_EN_DEST5_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST5 */
#define IFX_GTM_BRC_SRC7_DEST_EN_DEST5_OFF (5u)

/** \brief  Length for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST6 */
#define IFX_GTM_BRC_SRC7_DEST_EN_DEST6_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST6 */
#define IFX_GTM_BRC_SRC7_DEST_EN_DEST6_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST6 */
#define IFX_GTM_BRC_SRC7_DEST_EN_DEST6_OFF (6u)

/** \brief  Length for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST7 */
#define IFX_GTM_BRC_SRC7_DEST_EN_DEST7_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST7 */
#define IFX_GTM_BRC_SRC7_DEST_EN_DEST7_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST7 */
#define IFX_GTM_BRC_SRC7_DEST_EN_DEST7_OFF (7u)

/** \brief  Length for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST8 */
#define IFX_GTM_BRC_SRC7_DEST_EN_DEST8_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST8 */
#define IFX_GTM_BRC_SRC7_DEST_EN_DEST8_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST8 */
#define IFX_GTM_BRC_SRC7_DEST_EN_DEST8_OFF (8u)

/** \brief  Length for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST9 */
#define IFX_GTM_BRC_SRC7_DEST_EN_DEST9_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST9 */
#define IFX_GTM_BRC_SRC7_DEST_EN_DEST9_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_DEST9 */
#define IFX_GTM_BRC_SRC7_DEST_EN_DEST9_OFF (9u)

/** \brief  Length for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_TRASHBIN */
#define IFX_GTM_BRC_SRC7_DEST_EN_TRASHBIN_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_TRASHBIN */
#define IFX_GTM_BRC_SRC7_DEST_EN_TRASHBIN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC7_DEST_Bits.EN_TRASHBIN */
#define IFX_GTM_BRC_SRC7_DEST_EN_TRASHBIN_OFF (22u)

/** \brief  Length for Ifx_GTM_BRC_SRC8_ADDR_Bits.ADDR */
#define IFX_GTM_BRC_SRC8_ADDR_ADDR_LEN (9u)

/** \brief  Mask for Ifx_GTM_BRC_SRC8_ADDR_Bits.ADDR */
#define IFX_GTM_BRC_SRC8_ADDR_ADDR_MSK (0x1ffu)

/** \brief  Offset for Ifx_GTM_BRC_SRC8_ADDR_Bits.ADDR */
#define IFX_GTM_BRC_SRC8_ADDR_ADDR_OFF (0u)

/** \brief  Length for Ifx_GTM_BRC_SRC8_ADDR_Bits.BRC_MODE */
#define IFX_GTM_BRC_SRC8_ADDR_BRC_MODE_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC8_ADDR_Bits.BRC_MODE */
#define IFX_GTM_BRC_SRC8_ADDR_BRC_MODE_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC8_ADDR_Bits.BRC_MODE */
#define IFX_GTM_BRC_SRC8_ADDR_BRC_MODE_OFF (12u)

/** \brief  Length for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST0 */
#define IFX_GTM_BRC_SRC8_DEST_EN_DEST0_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST0 */
#define IFX_GTM_BRC_SRC8_DEST_EN_DEST0_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST0 */
#define IFX_GTM_BRC_SRC8_DEST_EN_DEST0_OFF (0u)

/** \brief  Length for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST10 */
#define IFX_GTM_BRC_SRC8_DEST_EN_DEST10_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST10 */
#define IFX_GTM_BRC_SRC8_DEST_EN_DEST10_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST10 */
#define IFX_GTM_BRC_SRC8_DEST_EN_DEST10_OFF (10u)

/** \brief  Length for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST11 */
#define IFX_GTM_BRC_SRC8_DEST_EN_DEST11_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST11 */
#define IFX_GTM_BRC_SRC8_DEST_EN_DEST11_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST11 */
#define IFX_GTM_BRC_SRC8_DEST_EN_DEST11_OFF (11u)

/** \brief  Length for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST12 */
#define IFX_GTM_BRC_SRC8_DEST_EN_DEST12_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST12 */
#define IFX_GTM_BRC_SRC8_DEST_EN_DEST12_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST12 */
#define IFX_GTM_BRC_SRC8_DEST_EN_DEST12_OFF (12u)

/** \brief  Length for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST13 */
#define IFX_GTM_BRC_SRC8_DEST_EN_DEST13_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST13 */
#define IFX_GTM_BRC_SRC8_DEST_EN_DEST13_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST13 */
#define IFX_GTM_BRC_SRC8_DEST_EN_DEST13_OFF (13u)

/** \brief  Length for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST14 */
#define IFX_GTM_BRC_SRC8_DEST_EN_DEST14_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST14 */
#define IFX_GTM_BRC_SRC8_DEST_EN_DEST14_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST14 */
#define IFX_GTM_BRC_SRC8_DEST_EN_DEST14_OFF (14u)

/** \brief  Length for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST15 */
#define IFX_GTM_BRC_SRC8_DEST_EN_DEST15_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST15 */
#define IFX_GTM_BRC_SRC8_DEST_EN_DEST15_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST15 */
#define IFX_GTM_BRC_SRC8_DEST_EN_DEST15_OFF (15u)

/** \brief  Length for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST16 */
#define IFX_GTM_BRC_SRC8_DEST_EN_DEST16_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST16 */
#define IFX_GTM_BRC_SRC8_DEST_EN_DEST16_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST16 */
#define IFX_GTM_BRC_SRC8_DEST_EN_DEST16_OFF (16u)

/** \brief  Length for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST17 */
#define IFX_GTM_BRC_SRC8_DEST_EN_DEST17_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST17 */
#define IFX_GTM_BRC_SRC8_DEST_EN_DEST17_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST17 */
#define IFX_GTM_BRC_SRC8_DEST_EN_DEST17_OFF (17u)

/** \brief  Length for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST18 */
#define IFX_GTM_BRC_SRC8_DEST_EN_DEST18_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST18 */
#define IFX_GTM_BRC_SRC8_DEST_EN_DEST18_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST18 */
#define IFX_GTM_BRC_SRC8_DEST_EN_DEST18_OFF (18u)

/** \brief  Length for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST19 */
#define IFX_GTM_BRC_SRC8_DEST_EN_DEST19_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST19 */
#define IFX_GTM_BRC_SRC8_DEST_EN_DEST19_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST19 */
#define IFX_GTM_BRC_SRC8_DEST_EN_DEST19_OFF (19u)

/** \brief  Length for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST1 */
#define IFX_GTM_BRC_SRC8_DEST_EN_DEST1_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST1 */
#define IFX_GTM_BRC_SRC8_DEST_EN_DEST1_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST1 */
#define IFX_GTM_BRC_SRC8_DEST_EN_DEST1_OFF (1u)

/** \brief  Length for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST20 */
#define IFX_GTM_BRC_SRC8_DEST_EN_DEST20_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST20 */
#define IFX_GTM_BRC_SRC8_DEST_EN_DEST20_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST20 */
#define IFX_GTM_BRC_SRC8_DEST_EN_DEST20_OFF (20u)

/** \brief  Length for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST21 */
#define IFX_GTM_BRC_SRC8_DEST_EN_DEST21_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST21 */
#define IFX_GTM_BRC_SRC8_DEST_EN_DEST21_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST21 */
#define IFX_GTM_BRC_SRC8_DEST_EN_DEST21_OFF (21u)

/** \brief  Length for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST2 */
#define IFX_GTM_BRC_SRC8_DEST_EN_DEST2_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST2 */
#define IFX_GTM_BRC_SRC8_DEST_EN_DEST2_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST2 */
#define IFX_GTM_BRC_SRC8_DEST_EN_DEST2_OFF (2u)

/** \brief  Length for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST3 */
#define IFX_GTM_BRC_SRC8_DEST_EN_DEST3_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST3 */
#define IFX_GTM_BRC_SRC8_DEST_EN_DEST3_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST3 */
#define IFX_GTM_BRC_SRC8_DEST_EN_DEST3_OFF (3u)

/** \brief  Length for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST4 */
#define IFX_GTM_BRC_SRC8_DEST_EN_DEST4_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST4 */
#define IFX_GTM_BRC_SRC8_DEST_EN_DEST4_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST4 */
#define IFX_GTM_BRC_SRC8_DEST_EN_DEST4_OFF (4u)

/** \brief  Length for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST5 */
#define IFX_GTM_BRC_SRC8_DEST_EN_DEST5_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST5 */
#define IFX_GTM_BRC_SRC8_DEST_EN_DEST5_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST5 */
#define IFX_GTM_BRC_SRC8_DEST_EN_DEST5_OFF (5u)

/** \brief  Length for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST6 */
#define IFX_GTM_BRC_SRC8_DEST_EN_DEST6_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST6 */
#define IFX_GTM_BRC_SRC8_DEST_EN_DEST6_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST6 */
#define IFX_GTM_BRC_SRC8_DEST_EN_DEST6_OFF (6u)

/** \brief  Length for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST7 */
#define IFX_GTM_BRC_SRC8_DEST_EN_DEST7_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST7 */
#define IFX_GTM_BRC_SRC8_DEST_EN_DEST7_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST7 */
#define IFX_GTM_BRC_SRC8_DEST_EN_DEST7_OFF (7u)

/** \brief  Length for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST8 */
#define IFX_GTM_BRC_SRC8_DEST_EN_DEST8_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST8 */
#define IFX_GTM_BRC_SRC8_DEST_EN_DEST8_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST8 */
#define IFX_GTM_BRC_SRC8_DEST_EN_DEST8_OFF (8u)

/** \brief  Length for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST9 */
#define IFX_GTM_BRC_SRC8_DEST_EN_DEST9_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST9 */
#define IFX_GTM_BRC_SRC8_DEST_EN_DEST9_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_DEST9 */
#define IFX_GTM_BRC_SRC8_DEST_EN_DEST9_OFF (9u)

/** \brief  Length for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_TRASHBIN */
#define IFX_GTM_BRC_SRC8_DEST_EN_TRASHBIN_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_TRASHBIN */
#define IFX_GTM_BRC_SRC8_DEST_EN_TRASHBIN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC8_DEST_Bits.EN_TRASHBIN */
#define IFX_GTM_BRC_SRC8_DEST_EN_TRASHBIN_OFF (22u)

/** \brief  Length for Ifx_GTM_BRC_SRC9_ADDR_Bits.ADDR */
#define IFX_GTM_BRC_SRC9_ADDR_ADDR_LEN (9u)

/** \brief  Mask for Ifx_GTM_BRC_SRC9_ADDR_Bits.ADDR */
#define IFX_GTM_BRC_SRC9_ADDR_ADDR_MSK (0x1ffu)

/** \brief  Offset for Ifx_GTM_BRC_SRC9_ADDR_Bits.ADDR */
#define IFX_GTM_BRC_SRC9_ADDR_ADDR_OFF (0u)

/** \brief  Length for Ifx_GTM_BRC_SRC9_ADDR_Bits.BRC_MODE */
#define IFX_GTM_BRC_SRC9_ADDR_BRC_MODE_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC9_ADDR_Bits.BRC_MODE */
#define IFX_GTM_BRC_SRC9_ADDR_BRC_MODE_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC9_ADDR_Bits.BRC_MODE */
#define IFX_GTM_BRC_SRC9_ADDR_BRC_MODE_OFF (12u)

/** \brief  Length for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST0 */
#define IFX_GTM_BRC_SRC9_DEST_EN_DEST0_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST0 */
#define IFX_GTM_BRC_SRC9_DEST_EN_DEST0_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST0 */
#define IFX_GTM_BRC_SRC9_DEST_EN_DEST0_OFF (0u)

/** \brief  Length for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST10 */
#define IFX_GTM_BRC_SRC9_DEST_EN_DEST10_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST10 */
#define IFX_GTM_BRC_SRC9_DEST_EN_DEST10_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST10 */
#define IFX_GTM_BRC_SRC9_DEST_EN_DEST10_OFF (10u)

/** \brief  Length for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST11 */
#define IFX_GTM_BRC_SRC9_DEST_EN_DEST11_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST11 */
#define IFX_GTM_BRC_SRC9_DEST_EN_DEST11_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST11 */
#define IFX_GTM_BRC_SRC9_DEST_EN_DEST11_OFF (11u)

/** \brief  Length for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST12 */
#define IFX_GTM_BRC_SRC9_DEST_EN_DEST12_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST12 */
#define IFX_GTM_BRC_SRC9_DEST_EN_DEST12_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST12 */
#define IFX_GTM_BRC_SRC9_DEST_EN_DEST12_OFF (12u)

/** \brief  Length for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST13 */
#define IFX_GTM_BRC_SRC9_DEST_EN_DEST13_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST13 */
#define IFX_GTM_BRC_SRC9_DEST_EN_DEST13_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST13 */
#define IFX_GTM_BRC_SRC9_DEST_EN_DEST13_OFF (13u)

/** \brief  Length for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST14 */
#define IFX_GTM_BRC_SRC9_DEST_EN_DEST14_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST14 */
#define IFX_GTM_BRC_SRC9_DEST_EN_DEST14_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST14 */
#define IFX_GTM_BRC_SRC9_DEST_EN_DEST14_OFF (14u)

/** \brief  Length for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST15 */
#define IFX_GTM_BRC_SRC9_DEST_EN_DEST15_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST15 */
#define IFX_GTM_BRC_SRC9_DEST_EN_DEST15_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST15 */
#define IFX_GTM_BRC_SRC9_DEST_EN_DEST15_OFF (15u)

/** \brief  Length for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST16 */
#define IFX_GTM_BRC_SRC9_DEST_EN_DEST16_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST16 */
#define IFX_GTM_BRC_SRC9_DEST_EN_DEST16_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST16 */
#define IFX_GTM_BRC_SRC9_DEST_EN_DEST16_OFF (16u)

/** \brief  Length for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST17 */
#define IFX_GTM_BRC_SRC9_DEST_EN_DEST17_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST17 */
#define IFX_GTM_BRC_SRC9_DEST_EN_DEST17_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST17 */
#define IFX_GTM_BRC_SRC9_DEST_EN_DEST17_OFF (17u)

/** \brief  Length for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST18 */
#define IFX_GTM_BRC_SRC9_DEST_EN_DEST18_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST18 */
#define IFX_GTM_BRC_SRC9_DEST_EN_DEST18_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST18 */
#define IFX_GTM_BRC_SRC9_DEST_EN_DEST18_OFF (18u)

/** \brief  Length for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST19 */
#define IFX_GTM_BRC_SRC9_DEST_EN_DEST19_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST19 */
#define IFX_GTM_BRC_SRC9_DEST_EN_DEST19_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST19 */
#define IFX_GTM_BRC_SRC9_DEST_EN_DEST19_OFF (19u)

/** \brief  Length for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST1 */
#define IFX_GTM_BRC_SRC9_DEST_EN_DEST1_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST1 */
#define IFX_GTM_BRC_SRC9_DEST_EN_DEST1_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST1 */
#define IFX_GTM_BRC_SRC9_DEST_EN_DEST1_OFF (1u)

/** \brief  Length for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST20 */
#define IFX_GTM_BRC_SRC9_DEST_EN_DEST20_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST20 */
#define IFX_GTM_BRC_SRC9_DEST_EN_DEST20_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST20 */
#define IFX_GTM_BRC_SRC9_DEST_EN_DEST20_OFF (20u)

/** \brief  Length for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST21 */
#define IFX_GTM_BRC_SRC9_DEST_EN_DEST21_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST21 */
#define IFX_GTM_BRC_SRC9_DEST_EN_DEST21_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST21 */
#define IFX_GTM_BRC_SRC9_DEST_EN_DEST21_OFF (21u)

/** \brief  Length for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST2 */
#define IFX_GTM_BRC_SRC9_DEST_EN_DEST2_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST2 */
#define IFX_GTM_BRC_SRC9_DEST_EN_DEST2_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST2 */
#define IFX_GTM_BRC_SRC9_DEST_EN_DEST2_OFF (2u)

/** \brief  Length for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST3 */
#define IFX_GTM_BRC_SRC9_DEST_EN_DEST3_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST3 */
#define IFX_GTM_BRC_SRC9_DEST_EN_DEST3_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST3 */
#define IFX_GTM_BRC_SRC9_DEST_EN_DEST3_OFF (3u)

/** \brief  Length for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST4 */
#define IFX_GTM_BRC_SRC9_DEST_EN_DEST4_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST4 */
#define IFX_GTM_BRC_SRC9_DEST_EN_DEST4_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST4 */
#define IFX_GTM_BRC_SRC9_DEST_EN_DEST4_OFF (4u)

/** \brief  Length for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST5 */
#define IFX_GTM_BRC_SRC9_DEST_EN_DEST5_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST5 */
#define IFX_GTM_BRC_SRC9_DEST_EN_DEST5_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST5 */
#define IFX_GTM_BRC_SRC9_DEST_EN_DEST5_OFF (5u)

/** \brief  Length for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST6 */
#define IFX_GTM_BRC_SRC9_DEST_EN_DEST6_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST6 */
#define IFX_GTM_BRC_SRC9_DEST_EN_DEST6_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST6 */
#define IFX_GTM_BRC_SRC9_DEST_EN_DEST6_OFF (6u)

/** \brief  Length for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST7 */
#define IFX_GTM_BRC_SRC9_DEST_EN_DEST7_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST7 */
#define IFX_GTM_BRC_SRC9_DEST_EN_DEST7_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST7 */
#define IFX_GTM_BRC_SRC9_DEST_EN_DEST7_OFF (7u)

/** \brief  Length for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST8 */
#define IFX_GTM_BRC_SRC9_DEST_EN_DEST8_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST8 */
#define IFX_GTM_BRC_SRC9_DEST_EN_DEST8_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST8 */
#define IFX_GTM_BRC_SRC9_DEST_EN_DEST8_OFF (8u)

/** \brief  Length for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST9 */
#define IFX_GTM_BRC_SRC9_DEST_EN_DEST9_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST9 */
#define IFX_GTM_BRC_SRC9_DEST_EN_DEST9_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_DEST9 */
#define IFX_GTM_BRC_SRC9_DEST_EN_DEST9_OFF (9u)

/** \brief  Length for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_TRASHBIN */
#define IFX_GTM_BRC_SRC9_DEST_EN_TRASHBIN_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_TRASHBIN */
#define IFX_GTM_BRC_SRC9_DEST_EN_TRASHBIN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRC_SRC9_DEST_Bits.EN_TRASHBIN */
#define IFX_GTM_BRC_SRC9_DEST_EN_TRASHBIN_OFF (22u)

/** \brief  Length for Ifx_GTM_BRIDGE_MODE_Bits.BRG_MODE */
#define IFX_GTM_BRIDGE_MODE_BRG_MODE_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRIDGE_MODE_Bits.BRG_MODE */
#define IFX_GTM_BRIDGE_MODE_BRG_MODE_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRIDGE_MODE_Bits.BRG_MODE */
#define IFX_GTM_BRIDGE_MODE_BRG_MODE_OFF (0u)

/** \brief  Length for Ifx_GTM_BRIDGE_MODE_Bits.BRG_RST */
#define IFX_GTM_BRIDGE_MODE_BRG_RST_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRIDGE_MODE_Bits.BRG_RST */
#define IFX_GTM_BRIDGE_MODE_BRG_RST_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRIDGE_MODE_Bits.BRG_RST */
#define IFX_GTM_BRIDGE_MODE_BRG_RST_OFF (16u)

/** \brief  Length for Ifx_GTM_BRIDGE_MODE_Bits.BUFF_DPT */
#define IFX_GTM_BRIDGE_MODE_BUFF_DPT_LEN (8u)

/** \brief  Mask for Ifx_GTM_BRIDGE_MODE_Bits.BUFF_DPT */
#define IFX_GTM_BRIDGE_MODE_BUFF_DPT_MSK (0xffu)

/** \brief  Offset for Ifx_GTM_BRIDGE_MODE_Bits.BUFF_DPT */
#define IFX_GTM_BRIDGE_MODE_BUFF_DPT_OFF (24u)

/** \brief  Length for Ifx_GTM_BRIDGE_MODE_Bits.BUFF_OVL */
#define IFX_GTM_BRIDGE_MODE_BUFF_OVL_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRIDGE_MODE_Bits.BUFF_OVL */
#define IFX_GTM_BRIDGE_MODE_BUFF_OVL_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRIDGE_MODE_Bits.BUFF_OVL */
#define IFX_GTM_BRIDGE_MODE_BUFF_OVL_OFF (9u)

/** \brief  Length for Ifx_GTM_BRIDGE_MODE_Bits.MODE_UP_PGR */
#define IFX_GTM_BRIDGE_MODE_MODE_UP_PGR_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRIDGE_MODE_Bits.MODE_UP_PGR */
#define IFX_GTM_BRIDGE_MODE_MODE_UP_PGR_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRIDGE_MODE_Bits.MODE_UP_PGR */
#define IFX_GTM_BRIDGE_MODE_MODE_UP_PGR_OFF (8u)

/** \brief  Length for Ifx_GTM_BRIDGE_MODE_Bits.MSK_WR_RSP */
#define IFX_GTM_BRIDGE_MODE_MSK_WR_RSP_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRIDGE_MODE_Bits.MSK_WR_RSP */
#define IFX_GTM_BRIDGE_MODE_MSK_WR_RSP_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRIDGE_MODE_Bits.MSK_WR_RSP */
#define IFX_GTM_BRIDGE_MODE_MSK_WR_RSP_OFF (1u)

/** \brief  Length for Ifx_GTM_BRIDGE_MODE_Bits.SYNC_INPUT_REG */
#define IFX_GTM_BRIDGE_MODE_SYNC_INPUT_REG_LEN (1u)

/** \brief  Mask for Ifx_GTM_BRIDGE_MODE_Bits.SYNC_INPUT_REG */
#define IFX_GTM_BRIDGE_MODE_SYNC_INPUT_REG_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_BRIDGE_MODE_Bits.SYNC_INPUT_REG */
#define IFX_GTM_BRIDGE_MODE_SYNC_INPUT_REG_OFF (12u)

/** \brief  Length for Ifx_GTM_BRIDGE_PTR1_Bits.ABT_TRAN_PGR */
#define IFX_GTM_BRIDGE_PTR1_ABT_TRAN_PGR_LEN (5u)

/** \brief  Mask for Ifx_GTM_BRIDGE_PTR1_Bits.ABT_TRAN_PGR */
#define IFX_GTM_BRIDGE_PTR1_ABT_TRAN_PGR_MSK (0x1fu)

/** \brief  Offset for Ifx_GTM_BRIDGE_PTR1_Bits.ABT_TRAN_PGR */
#define IFX_GTM_BRIDGE_PTR1_ABT_TRAN_PGR_OFF (15u)

/** \brief  Length for Ifx_GTM_BRIDGE_PTR1_Bits.FBC */
#define IFX_GTM_BRIDGE_PTR1_FBC_LEN (6u)

/** \brief  Mask for Ifx_GTM_BRIDGE_PTR1_Bits.FBC */
#define IFX_GTM_BRIDGE_PTR1_FBC_MSK (0x3fu)

/** \brief  Offset for Ifx_GTM_BRIDGE_PTR1_Bits.FBC */
#define IFX_GTM_BRIDGE_PTR1_FBC_OFF (20u)

/** \brief  Length for Ifx_GTM_BRIDGE_PTR1_Bits.FIRST_RSP_PTR */
#define IFX_GTM_BRIDGE_PTR1_FIRST_RSP_PTR_LEN (5u)

/** \brief  Mask for Ifx_GTM_BRIDGE_PTR1_Bits.FIRST_RSP_PTR */
#define IFX_GTM_BRIDGE_PTR1_FIRST_RSP_PTR_MSK (0x1fu)

/** \brief  Offset for Ifx_GTM_BRIDGE_PTR1_Bits.FIRST_RSP_PTR */
#define IFX_GTM_BRIDGE_PTR1_FIRST_RSP_PTR_OFF (5u)

/** \brief  Length for Ifx_GTM_BRIDGE_PTR1_Bits.NEW_TRAN_PTR */
#define IFX_GTM_BRIDGE_PTR1_NEW_TRAN_PTR_LEN (5u)

/** \brief  Mask for Ifx_GTM_BRIDGE_PTR1_Bits.NEW_TRAN_PTR */
#define IFX_GTM_BRIDGE_PTR1_NEW_TRAN_PTR_MSK (0x1fu)

/** \brief  Offset for Ifx_GTM_BRIDGE_PTR1_Bits.NEW_TRAN_PTR */
#define IFX_GTM_BRIDGE_PTR1_NEW_TRAN_PTR_OFF (0u)

/** \brief  Length for Ifx_GTM_BRIDGE_PTR1_Bits.RSP_TRAN_RDY */
#define IFX_GTM_BRIDGE_PTR1_RSP_TRAN_RDY_LEN (6u)

/** \brief  Mask for Ifx_GTM_BRIDGE_PTR1_Bits.RSP_TRAN_RDY */
#define IFX_GTM_BRIDGE_PTR1_RSP_TRAN_RDY_MSK (0x3fu)

/** \brief  Offset for Ifx_GTM_BRIDGE_PTR1_Bits.RSP_TRAN_RDY */
#define IFX_GTM_BRIDGE_PTR1_RSP_TRAN_RDY_OFF (26u)

/** \brief  Length for Ifx_GTM_BRIDGE_PTR1_Bits.TRAN_IN_PGR */
#define IFX_GTM_BRIDGE_PTR1_TRAN_IN_PGR_LEN (5u)

/** \brief  Mask for Ifx_GTM_BRIDGE_PTR1_Bits.TRAN_IN_PGR */
#define IFX_GTM_BRIDGE_PTR1_TRAN_IN_PGR_MSK (0x1fu)

/** \brief  Offset for Ifx_GTM_BRIDGE_PTR1_Bits.TRAN_IN_PGR */
#define IFX_GTM_BRIDGE_PTR1_TRAN_IN_PGR_OFF (10u)

/** \brief  Length for Ifx_GTM_BRIDGE_PTR2_Bits.TRAN_IN_PGR2 */
#define IFX_GTM_BRIDGE_PTR2_TRAN_IN_PGR2_LEN (5u)

/** \brief  Mask for Ifx_GTM_BRIDGE_PTR2_Bits.TRAN_IN_PGR2 */
#define IFX_GTM_BRIDGE_PTR2_TRAN_IN_PGR2_MSK (0x1fu)

/** \brief  Offset for Ifx_GTM_BRIDGE_PTR2_Bits.TRAN_IN_PGR2 */
#define IFX_GTM_BRIDGE_PTR2_TRAN_IN_PGR2_OFF (0u)

/** \brief  Length for Ifx_GTM_CLC_Bits.DISR */
#define IFX_GTM_CLC_DISR_LEN (1u)

/** \brief  Mask for Ifx_GTM_CLC_Bits.DISR */
#define IFX_GTM_CLC_DISR_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CLC_Bits.DISR */
#define IFX_GTM_CLC_DISR_OFF (0u)

/** \brief  Length for Ifx_GTM_CLC_Bits.DISS */
#define IFX_GTM_CLC_DISS_LEN (1u)

/** \brief  Mask for Ifx_GTM_CLC_Bits.DISS */
#define IFX_GTM_CLC_DISS_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CLC_Bits.DISS */
#define IFX_GTM_CLC_DISS_OFF (1u)

/** \brief  Length for Ifx_GTM_CLC_Bits.EDIS */
#define IFX_GTM_CLC_EDIS_LEN (1u)

/** \brief  Mask for Ifx_GTM_CLC_Bits.EDIS */
#define IFX_GTM_CLC_EDIS_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CLC_Bits.EDIS */
#define IFX_GTM_CLC_EDIS_OFF (3u)

/** \brief  Length for Ifx_GTM_CMP_EIRQ_EN_Bits.ABWC0_EN_EIRQ */
#define IFX_GTM_CMP_EIRQ_EN_ABWC0_EN_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_EIRQ_EN_Bits.ABWC0_EN_EIRQ */
#define IFX_GTM_CMP_EIRQ_EN_ABWC0_EN_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_EIRQ_EN_Bits.ABWC0_EN_EIRQ */
#define IFX_GTM_CMP_EIRQ_EN_ABWC0_EN_EIRQ_OFF (0u)

/** \brief  Length for Ifx_GTM_CMP_EIRQ_EN_Bits.ABWC10_EN_EIRQ */
#define IFX_GTM_CMP_EIRQ_EN_ABWC10_EN_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_EIRQ_EN_Bits.ABWC10_EN_EIRQ */
#define IFX_GTM_CMP_EIRQ_EN_ABWC10_EN_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_EIRQ_EN_Bits.ABWC10_EN_EIRQ */
#define IFX_GTM_CMP_EIRQ_EN_ABWC10_EN_EIRQ_OFF (10u)

/** \brief  Length for Ifx_GTM_CMP_EIRQ_EN_Bits.ABWC11_EN_EIRQ */
#define IFX_GTM_CMP_EIRQ_EN_ABWC11_EN_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_EIRQ_EN_Bits.ABWC11_EN_EIRQ */
#define IFX_GTM_CMP_EIRQ_EN_ABWC11_EN_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_EIRQ_EN_Bits.ABWC11_EN_EIRQ */
#define IFX_GTM_CMP_EIRQ_EN_ABWC11_EN_EIRQ_OFF (11u)

/** \brief  Length for Ifx_GTM_CMP_EIRQ_EN_Bits.ABWC1_EN_EIRQ */
#define IFX_GTM_CMP_EIRQ_EN_ABWC1_EN_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_EIRQ_EN_Bits.ABWC1_EN_EIRQ */
#define IFX_GTM_CMP_EIRQ_EN_ABWC1_EN_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_EIRQ_EN_Bits.ABWC1_EN_EIRQ */
#define IFX_GTM_CMP_EIRQ_EN_ABWC1_EN_EIRQ_OFF (1u)

/** \brief  Length for Ifx_GTM_CMP_EIRQ_EN_Bits.ABWC2_EN_EIRQ */
#define IFX_GTM_CMP_EIRQ_EN_ABWC2_EN_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_EIRQ_EN_Bits.ABWC2_EN_EIRQ */
#define IFX_GTM_CMP_EIRQ_EN_ABWC2_EN_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_EIRQ_EN_Bits.ABWC2_EN_EIRQ */
#define IFX_GTM_CMP_EIRQ_EN_ABWC2_EN_EIRQ_OFF (2u)

/** \brief  Length for Ifx_GTM_CMP_EIRQ_EN_Bits.ABWC3_EN_EIRQ */
#define IFX_GTM_CMP_EIRQ_EN_ABWC3_EN_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_EIRQ_EN_Bits.ABWC3_EN_EIRQ */
#define IFX_GTM_CMP_EIRQ_EN_ABWC3_EN_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_EIRQ_EN_Bits.ABWC3_EN_EIRQ */
#define IFX_GTM_CMP_EIRQ_EN_ABWC3_EN_EIRQ_OFF (3u)

/** \brief  Length for Ifx_GTM_CMP_EIRQ_EN_Bits.ABWC4_EN_EIRQ */
#define IFX_GTM_CMP_EIRQ_EN_ABWC4_EN_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_EIRQ_EN_Bits.ABWC4_EN_EIRQ */
#define IFX_GTM_CMP_EIRQ_EN_ABWC4_EN_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_EIRQ_EN_Bits.ABWC4_EN_EIRQ */
#define IFX_GTM_CMP_EIRQ_EN_ABWC4_EN_EIRQ_OFF (4u)

/** \brief  Length for Ifx_GTM_CMP_EIRQ_EN_Bits.ABWC5_EN_EIRQ */
#define IFX_GTM_CMP_EIRQ_EN_ABWC5_EN_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_EIRQ_EN_Bits.ABWC5_EN_EIRQ */
#define IFX_GTM_CMP_EIRQ_EN_ABWC5_EN_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_EIRQ_EN_Bits.ABWC5_EN_EIRQ */
#define IFX_GTM_CMP_EIRQ_EN_ABWC5_EN_EIRQ_OFF (5u)

/** \brief  Length for Ifx_GTM_CMP_EIRQ_EN_Bits.ABWC6_EN_EIRQ */
#define IFX_GTM_CMP_EIRQ_EN_ABWC6_EN_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_EIRQ_EN_Bits.ABWC6_EN_EIRQ */
#define IFX_GTM_CMP_EIRQ_EN_ABWC6_EN_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_EIRQ_EN_Bits.ABWC6_EN_EIRQ */
#define IFX_GTM_CMP_EIRQ_EN_ABWC6_EN_EIRQ_OFF (6u)

/** \brief  Length for Ifx_GTM_CMP_EIRQ_EN_Bits.ABWC7_EN_EIRQ */
#define IFX_GTM_CMP_EIRQ_EN_ABWC7_EN_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_EIRQ_EN_Bits.ABWC7_EN_EIRQ */
#define IFX_GTM_CMP_EIRQ_EN_ABWC7_EN_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_EIRQ_EN_Bits.ABWC7_EN_EIRQ */
#define IFX_GTM_CMP_EIRQ_EN_ABWC7_EN_EIRQ_OFF (7u)

/** \brief  Length for Ifx_GTM_CMP_EIRQ_EN_Bits.ABWC8_EN_EIRQ */
#define IFX_GTM_CMP_EIRQ_EN_ABWC8_EN_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_EIRQ_EN_Bits.ABWC8_EN_EIRQ */
#define IFX_GTM_CMP_EIRQ_EN_ABWC8_EN_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_EIRQ_EN_Bits.ABWC8_EN_EIRQ */
#define IFX_GTM_CMP_EIRQ_EN_ABWC8_EN_EIRQ_OFF (8u)

/** \brief  Length for Ifx_GTM_CMP_EIRQ_EN_Bits.ABWC9_EN_EIRQ */
#define IFX_GTM_CMP_EIRQ_EN_ABWC9_EN_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_EIRQ_EN_Bits.ABWC9_EN_EIRQ */
#define IFX_GTM_CMP_EIRQ_EN_ABWC9_EN_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_EIRQ_EN_Bits.ABWC9_EN_EIRQ */
#define IFX_GTM_CMP_EIRQ_EN_ABWC9_EN_EIRQ_OFF (9u)

/** \brief  Length for Ifx_GTM_CMP_EIRQ_EN_Bits.TBWC0_EN_EIRQ */
#define IFX_GTM_CMP_EIRQ_EN_TBWC0_EN_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_EIRQ_EN_Bits.TBWC0_EN_EIRQ */
#define IFX_GTM_CMP_EIRQ_EN_TBWC0_EN_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_EIRQ_EN_Bits.TBWC0_EN_EIRQ */
#define IFX_GTM_CMP_EIRQ_EN_TBWC0_EN_EIRQ_OFF (12u)

/** \brief  Length for Ifx_GTM_CMP_EIRQ_EN_Bits.TBWC10_EN_EIRQ */
#define IFX_GTM_CMP_EIRQ_EN_TBWC10_EN_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_EIRQ_EN_Bits.TBWC10_EN_EIRQ */
#define IFX_GTM_CMP_EIRQ_EN_TBWC10_EN_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_EIRQ_EN_Bits.TBWC10_EN_EIRQ */
#define IFX_GTM_CMP_EIRQ_EN_TBWC10_EN_EIRQ_OFF (22u)

/** \brief  Length for Ifx_GTM_CMP_EIRQ_EN_Bits.TBWC11_EN_EIRQ */
#define IFX_GTM_CMP_EIRQ_EN_TBWC11_EN_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_EIRQ_EN_Bits.TBWC11_EN_EIRQ */
#define IFX_GTM_CMP_EIRQ_EN_TBWC11_EN_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_EIRQ_EN_Bits.TBWC11_EN_EIRQ */
#define IFX_GTM_CMP_EIRQ_EN_TBWC11_EN_EIRQ_OFF (23u)

/** \brief  Length for Ifx_GTM_CMP_EIRQ_EN_Bits.TBWC1_EN_EIRQ */
#define IFX_GTM_CMP_EIRQ_EN_TBWC1_EN_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_EIRQ_EN_Bits.TBWC1_EN_EIRQ */
#define IFX_GTM_CMP_EIRQ_EN_TBWC1_EN_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_EIRQ_EN_Bits.TBWC1_EN_EIRQ */
#define IFX_GTM_CMP_EIRQ_EN_TBWC1_EN_EIRQ_OFF (13u)

/** \brief  Length for Ifx_GTM_CMP_EIRQ_EN_Bits.TBWC2_EN_EIRQ */
#define IFX_GTM_CMP_EIRQ_EN_TBWC2_EN_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_EIRQ_EN_Bits.TBWC2_EN_EIRQ */
#define IFX_GTM_CMP_EIRQ_EN_TBWC2_EN_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_EIRQ_EN_Bits.TBWC2_EN_EIRQ */
#define IFX_GTM_CMP_EIRQ_EN_TBWC2_EN_EIRQ_OFF (14u)

/** \brief  Length for Ifx_GTM_CMP_EIRQ_EN_Bits.TBWC3_EN_EIRQ */
#define IFX_GTM_CMP_EIRQ_EN_TBWC3_EN_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_EIRQ_EN_Bits.TBWC3_EN_EIRQ */
#define IFX_GTM_CMP_EIRQ_EN_TBWC3_EN_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_EIRQ_EN_Bits.TBWC3_EN_EIRQ */
#define IFX_GTM_CMP_EIRQ_EN_TBWC3_EN_EIRQ_OFF (15u)

/** \brief  Length for Ifx_GTM_CMP_EIRQ_EN_Bits.TBWC4_EN_EIRQ */
#define IFX_GTM_CMP_EIRQ_EN_TBWC4_EN_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_EIRQ_EN_Bits.TBWC4_EN_EIRQ */
#define IFX_GTM_CMP_EIRQ_EN_TBWC4_EN_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_EIRQ_EN_Bits.TBWC4_EN_EIRQ */
#define IFX_GTM_CMP_EIRQ_EN_TBWC4_EN_EIRQ_OFF (16u)

/** \brief  Length for Ifx_GTM_CMP_EIRQ_EN_Bits.TBWC5_EN_EIRQ */
#define IFX_GTM_CMP_EIRQ_EN_TBWC5_EN_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_EIRQ_EN_Bits.TBWC5_EN_EIRQ */
#define IFX_GTM_CMP_EIRQ_EN_TBWC5_EN_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_EIRQ_EN_Bits.TBWC5_EN_EIRQ */
#define IFX_GTM_CMP_EIRQ_EN_TBWC5_EN_EIRQ_OFF (17u)

/** \brief  Length for Ifx_GTM_CMP_EIRQ_EN_Bits.TBWC6_EN_EIRQ */
#define IFX_GTM_CMP_EIRQ_EN_TBWC6_EN_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_EIRQ_EN_Bits.TBWC6_EN_EIRQ */
#define IFX_GTM_CMP_EIRQ_EN_TBWC6_EN_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_EIRQ_EN_Bits.TBWC6_EN_EIRQ */
#define IFX_GTM_CMP_EIRQ_EN_TBWC6_EN_EIRQ_OFF (18u)

/** \brief  Length for Ifx_GTM_CMP_EIRQ_EN_Bits.TBWC7_EN_EIRQ */
#define IFX_GTM_CMP_EIRQ_EN_TBWC7_EN_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_EIRQ_EN_Bits.TBWC7_EN_EIRQ */
#define IFX_GTM_CMP_EIRQ_EN_TBWC7_EN_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_EIRQ_EN_Bits.TBWC7_EN_EIRQ */
#define IFX_GTM_CMP_EIRQ_EN_TBWC7_EN_EIRQ_OFF (19u)

/** \brief  Length for Ifx_GTM_CMP_EIRQ_EN_Bits.TBWC8_EN_EIRQ */
#define IFX_GTM_CMP_EIRQ_EN_TBWC8_EN_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_EIRQ_EN_Bits.TBWC8_EN_EIRQ */
#define IFX_GTM_CMP_EIRQ_EN_TBWC8_EN_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_EIRQ_EN_Bits.TBWC8_EN_EIRQ */
#define IFX_GTM_CMP_EIRQ_EN_TBWC8_EN_EIRQ_OFF (20u)

/** \brief  Length for Ifx_GTM_CMP_EIRQ_EN_Bits.TBWC9_EN_EIRQ */
#define IFX_GTM_CMP_EIRQ_EN_TBWC9_EN_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_EIRQ_EN_Bits.TBWC9_EN_EIRQ */
#define IFX_GTM_CMP_EIRQ_EN_TBWC9_EN_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_EIRQ_EN_Bits.TBWC9_EN_EIRQ */
#define IFX_GTM_CMP_EIRQ_EN_TBWC9_EN_EIRQ_OFF (21u)

/** \brief  Length for Ifx_GTM_CMP_EN_Bits.ABWC0_EN */
#define IFX_GTM_CMP_EN_ABWC0_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_EN_Bits.ABWC0_EN */
#define IFX_GTM_CMP_EN_ABWC0_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_EN_Bits.ABWC0_EN */
#define IFX_GTM_CMP_EN_ABWC0_EN_OFF (0u)

/** \brief  Length for Ifx_GTM_CMP_EN_Bits.ABWC10_EN */
#define IFX_GTM_CMP_EN_ABWC10_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_EN_Bits.ABWC10_EN */
#define IFX_GTM_CMP_EN_ABWC10_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_EN_Bits.ABWC10_EN */
#define IFX_GTM_CMP_EN_ABWC10_EN_OFF (10u)

/** \brief  Length for Ifx_GTM_CMP_EN_Bits.ABWC11_EN */
#define IFX_GTM_CMP_EN_ABWC11_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_EN_Bits.ABWC11_EN */
#define IFX_GTM_CMP_EN_ABWC11_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_EN_Bits.ABWC11_EN */
#define IFX_GTM_CMP_EN_ABWC11_EN_OFF (11u)

/** \brief  Length for Ifx_GTM_CMP_EN_Bits.ABWC1_EN */
#define IFX_GTM_CMP_EN_ABWC1_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_EN_Bits.ABWC1_EN */
#define IFX_GTM_CMP_EN_ABWC1_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_EN_Bits.ABWC1_EN */
#define IFX_GTM_CMP_EN_ABWC1_EN_OFF (1u)

/** \brief  Length for Ifx_GTM_CMP_EN_Bits.ABWC2_EN */
#define IFX_GTM_CMP_EN_ABWC2_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_EN_Bits.ABWC2_EN */
#define IFX_GTM_CMP_EN_ABWC2_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_EN_Bits.ABWC2_EN */
#define IFX_GTM_CMP_EN_ABWC2_EN_OFF (2u)

/** \brief  Length for Ifx_GTM_CMP_EN_Bits.ABWC3_EN */
#define IFX_GTM_CMP_EN_ABWC3_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_EN_Bits.ABWC3_EN */
#define IFX_GTM_CMP_EN_ABWC3_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_EN_Bits.ABWC3_EN */
#define IFX_GTM_CMP_EN_ABWC3_EN_OFF (3u)

/** \brief  Length for Ifx_GTM_CMP_EN_Bits.ABWC4_EN */
#define IFX_GTM_CMP_EN_ABWC4_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_EN_Bits.ABWC4_EN */
#define IFX_GTM_CMP_EN_ABWC4_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_EN_Bits.ABWC4_EN */
#define IFX_GTM_CMP_EN_ABWC4_EN_OFF (4u)

/** \brief  Length for Ifx_GTM_CMP_EN_Bits.ABWC5_EN */
#define IFX_GTM_CMP_EN_ABWC5_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_EN_Bits.ABWC5_EN */
#define IFX_GTM_CMP_EN_ABWC5_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_EN_Bits.ABWC5_EN */
#define IFX_GTM_CMP_EN_ABWC5_EN_OFF (5u)

/** \brief  Length for Ifx_GTM_CMP_EN_Bits.ABWC6_EN */
#define IFX_GTM_CMP_EN_ABWC6_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_EN_Bits.ABWC6_EN */
#define IFX_GTM_CMP_EN_ABWC6_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_EN_Bits.ABWC6_EN */
#define IFX_GTM_CMP_EN_ABWC6_EN_OFF (6u)

/** \brief  Length for Ifx_GTM_CMP_EN_Bits.ABWC7_EN */
#define IFX_GTM_CMP_EN_ABWC7_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_EN_Bits.ABWC7_EN */
#define IFX_GTM_CMP_EN_ABWC7_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_EN_Bits.ABWC7_EN */
#define IFX_GTM_CMP_EN_ABWC7_EN_OFF (7u)

/** \brief  Length for Ifx_GTM_CMP_EN_Bits.ABWC8_EN */
#define IFX_GTM_CMP_EN_ABWC8_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_EN_Bits.ABWC8_EN */
#define IFX_GTM_CMP_EN_ABWC8_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_EN_Bits.ABWC8_EN */
#define IFX_GTM_CMP_EN_ABWC8_EN_OFF (8u)

/** \brief  Length for Ifx_GTM_CMP_EN_Bits.ABWC9_EN */
#define IFX_GTM_CMP_EN_ABWC9_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_EN_Bits.ABWC9_EN */
#define IFX_GTM_CMP_EN_ABWC9_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_EN_Bits.ABWC9_EN */
#define IFX_GTM_CMP_EN_ABWC9_EN_OFF (9u)

/** \brief  Length for Ifx_GTM_CMP_EN_Bits.TBWC0_EN */
#define IFX_GTM_CMP_EN_TBWC0_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_EN_Bits.TBWC0_EN */
#define IFX_GTM_CMP_EN_TBWC0_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_EN_Bits.TBWC0_EN */
#define IFX_GTM_CMP_EN_TBWC0_EN_OFF (12u)

/** \brief  Length for Ifx_GTM_CMP_EN_Bits.TBWC10_EN */
#define IFX_GTM_CMP_EN_TBWC10_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_EN_Bits.TBWC10_EN */
#define IFX_GTM_CMP_EN_TBWC10_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_EN_Bits.TBWC10_EN */
#define IFX_GTM_CMP_EN_TBWC10_EN_OFF (22u)

/** \brief  Length for Ifx_GTM_CMP_EN_Bits.TBWC11_EN */
#define IFX_GTM_CMP_EN_TBWC11_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_EN_Bits.TBWC11_EN */
#define IFX_GTM_CMP_EN_TBWC11_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_EN_Bits.TBWC11_EN */
#define IFX_GTM_CMP_EN_TBWC11_EN_OFF (23u)

/** \brief  Length for Ifx_GTM_CMP_EN_Bits.TBWC1_EN */
#define IFX_GTM_CMP_EN_TBWC1_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_EN_Bits.TBWC1_EN */
#define IFX_GTM_CMP_EN_TBWC1_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_EN_Bits.TBWC1_EN */
#define IFX_GTM_CMP_EN_TBWC1_EN_OFF (13u)

/** \brief  Length for Ifx_GTM_CMP_EN_Bits.TBWC2_EN */
#define IFX_GTM_CMP_EN_TBWC2_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_EN_Bits.TBWC2_EN */
#define IFX_GTM_CMP_EN_TBWC2_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_EN_Bits.TBWC2_EN */
#define IFX_GTM_CMP_EN_TBWC2_EN_OFF (14u)

/** \brief  Length for Ifx_GTM_CMP_EN_Bits.TBWC3_EN */
#define IFX_GTM_CMP_EN_TBWC3_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_EN_Bits.TBWC3_EN */
#define IFX_GTM_CMP_EN_TBWC3_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_EN_Bits.TBWC3_EN */
#define IFX_GTM_CMP_EN_TBWC3_EN_OFF (15u)

/** \brief  Length for Ifx_GTM_CMP_EN_Bits.TBWC4_EN */
#define IFX_GTM_CMP_EN_TBWC4_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_EN_Bits.TBWC4_EN */
#define IFX_GTM_CMP_EN_TBWC4_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_EN_Bits.TBWC4_EN */
#define IFX_GTM_CMP_EN_TBWC4_EN_OFF (16u)

/** \brief  Length for Ifx_GTM_CMP_EN_Bits.TBWC5_EN */
#define IFX_GTM_CMP_EN_TBWC5_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_EN_Bits.TBWC5_EN */
#define IFX_GTM_CMP_EN_TBWC5_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_EN_Bits.TBWC5_EN */
#define IFX_GTM_CMP_EN_TBWC5_EN_OFF (17u)

/** \brief  Length for Ifx_GTM_CMP_EN_Bits.TBWC6_EN */
#define IFX_GTM_CMP_EN_TBWC6_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_EN_Bits.TBWC6_EN */
#define IFX_GTM_CMP_EN_TBWC6_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_EN_Bits.TBWC6_EN */
#define IFX_GTM_CMP_EN_TBWC6_EN_OFF (18u)

/** \brief  Length for Ifx_GTM_CMP_EN_Bits.TBWC7_EN */
#define IFX_GTM_CMP_EN_TBWC7_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_EN_Bits.TBWC7_EN */
#define IFX_GTM_CMP_EN_TBWC7_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_EN_Bits.TBWC7_EN */
#define IFX_GTM_CMP_EN_TBWC7_EN_OFF (19u)

/** \brief  Length for Ifx_GTM_CMP_EN_Bits.TBWC8_EN */
#define IFX_GTM_CMP_EN_TBWC8_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_EN_Bits.TBWC8_EN */
#define IFX_GTM_CMP_EN_TBWC8_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_EN_Bits.TBWC8_EN */
#define IFX_GTM_CMP_EN_TBWC8_EN_OFF (20u)

/** \brief  Length for Ifx_GTM_CMP_EN_Bits.TBWC9_EN */
#define IFX_GTM_CMP_EN_TBWC9_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_EN_Bits.TBWC9_EN */
#define IFX_GTM_CMP_EN_TBWC9_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_EN_Bits.TBWC9_EN */
#define IFX_GTM_CMP_EN_TBWC9_EN_OFF (21u)

/** \brief  Length for Ifx_GTM_CMP_IRQ_EN_Bits.ABWC0_EN_IRQ */
#define IFX_GTM_CMP_IRQ_EN_ABWC0_EN_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_IRQ_EN_Bits.ABWC0_EN_IRQ */
#define IFX_GTM_CMP_IRQ_EN_ABWC0_EN_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_IRQ_EN_Bits.ABWC0_EN_IRQ */
#define IFX_GTM_CMP_IRQ_EN_ABWC0_EN_IRQ_OFF (0u)

/** \brief  Length for Ifx_GTM_CMP_IRQ_EN_Bits.ABWC10_EN_IRQ */
#define IFX_GTM_CMP_IRQ_EN_ABWC10_EN_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_IRQ_EN_Bits.ABWC10_EN_IRQ */
#define IFX_GTM_CMP_IRQ_EN_ABWC10_EN_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_IRQ_EN_Bits.ABWC10_EN_IRQ */
#define IFX_GTM_CMP_IRQ_EN_ABWC10_EN_IRQ_OFF (10u)

/** \brief  Length for Ifx_GTM_CMP_IRQ_EN_Bits.ABWC11_EN_IRQ */
#define IFX_GTM_CMP_IRQ_EN_ABWC11_EN_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_IRQ_EN_Bits.ABWC11_EN_IRQ */
#define IFX_GTM_CMP_IRQ_EN_ABWC11_EN_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_IRQ_EN_Bits.ABWC11_EN_IRQ */
#define IFX_GTM_CMP_IRQ_EN_ABWC11_EN_IRQ_OFF (11u)

/** \brief  Length for Ifx_GTM_CMP_IRQ_EN_Bits.ABWC1_EN_IRQ */
#define IFX_GTM_CMP_IRQ_EN_ABWC1_EN_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_IRQ_EN_Bits.ABWC1_EN_IRQ */
#define IFX_GTM_CMP_IRQ_EN_ABWC1_EN_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_IRQ_EN_Bits.ABWC1_EN_IRQ */
#define IFX_GTM_CMP_IRQ_EN_ABWC1_EN_IRQ_OFF (1u)

/** \brief  Length for Ifx_GTM_CMP_IRQ_EN_Bits.ABWC2_EN_IRQ */
#define IFX_GTM_CMP_IRQ_EN_ABWC2_EN_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_IRQ_EN_Bits.ABWC2_EN_IRQ */
#define IFX_GTM_CMP_IRQ_EN_ABWC2_EN_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_IRQ_EN_Bits.ABWC2_EN_IRQ */
#define IFX_GTM_CMP_IRQ_EN_ABWC2_EN_IRQ_OFF (2u)

/** \brief  Length for Ifx_GTM_CMP_IRQ_EN_Bits.ABWC3_EN_IRQ */
#define IFX_GTM_CMP_IRQ_EN_ABWC3_EN_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_IRQ_EN_Bits.ABWC3_EN_IRQ */
#define IFX_GTM_CMP_IRQ_EN_ABWC3_EN_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_IRQ_EN_Bits.ABWC3_EN_IRQ */
#define IFX_GTM_CMP_IRQ_EN_ABWC3_EN_IRQ_OFF (3u)

/** \brief  Length for Ifx_GTM_CMP_IRQ_EN_Bits.ABWC4_EN_IRQ */
#define IFX_GTM_CMP_IRQ_EN_ABWC4_EN_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_IRQ_EN_Bits.ABWC4_EN_IRQ */
#define IFX_GTM_CMP_IRQ_EN_ABWC4_EN_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_IRQ_EN_Bits.ABWC4_EN_IRQ */
#define IFX_GTM_CMP_IRQ_EN_ABWC4_EN_IRQ_OFF (4u)

/** \brief  Length for Ifx_GTM_CMP_IRQ_EN_Bits.ABWC5_EN_IRQ */
#define IFX_GTM_CMP_IRQ_EN_ABWC5_EN_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_IRQ_EN_Bits.ABWC5_EN_IRQ */
#define IFX_GTM_CMP_IRQ_EN_ABWC5_EN_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_IRQ_EN_Bits.ABWC5_EN_IRQ */
#define IFX_GTM_CMP_IRQ_EN_ABWC5_EN_IRQ_OFF (5u)

/** \brief  Length for Ifx_GTM_CMP_IRQ_EN_Bits.ABWC6_EN_IRQ */
#define IFX_GTM_CMP_IRQ_EN_ABWC6_EN_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_IRQ_EN_Bits.ABWC6_EN_IRQ */
#define IFX_GTM_CMP_IRQ_EN_ABWC6_EN_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_IRQ_EN_Bits.ABWC6_EN_IRQ */
#define IFX_GTM_CMP_IRQ_EN_ABWC6_EN_IRQ_OFF (6u)

/** \brief  Length for Ifx_GTM_CMP_IRQ_EN_Bits.ABWC7_EN_IRQ */
#define IFX_GTM_CMP_IRQ_EN_ABWC7_EN_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_IRQ_EN_Bits.ABWC7_EN_IRQ */
#define IFX_GTM_CMP_IRQ_EN_ABWC7_EN_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_IRQ_EN_Bits.ABWC7_EN_IRQ */
#define IFX_GTM_CMP_IRQ_EN_ABWC7_EN_IRQ_OFF (7u)

/** \brief  Length for Ifx_GTM_CMP_IRQ_EN_Bits.ABWC8_EN_IRQ */
#define IFX_GTM_CMP_IRQ_EN_ABWC8_EN_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_IRQ_EN_Bits.ABWC8_EN_IRQ */
#define IFX_GTM_CMP_IRQ_EN_ABWC8_EN_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_IRQ_EN_Bits.ABWC8_EN_IRQ */
#define IFX_GTM_CMP_IRQ_EN_ABWC8_EN_IRQ_OFF (8u)

/** \brief  Length for Ifx_GTM_CMP_IRQ_EN_Bits.ABWC9_EN_IRQ */
#define IFX_GTM_CMP_IRQ_EN_ABWC9_EN_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_IRQ_EN_Bits.ABWC9_EN_IRQ */
#define IFX_GTM_CMP_IRQ_EN_ABWC9_EN_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_IRQ_EN_Bits.ABWC9_EN_IRQ */
#define IFX_GTM_CMP_IRQ_EN_ABWC9_EN_IRQ_OFF (9u)

/** \brief  Length for Ifx_GTM_CMP_IRQ_EN_Bits.TBWC0_EN_IRQ */
#define IFX_GTM_CMP_IRQ_EN_TBWC0_EN_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_IRQ_EN_Bits.TBWC0_EN_IRQ */
#define IFX_GTM_CMP_IRQ_EN_TBWC0_EN_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_IRQ_EN_Bits.TBWC0_EN_IRQ */
#define IFX_GTM_CMP_IRQ_EN_TBWC0_EN_IRQ_OFF (12u)

/** \brief  Length for Ifx_GTM_CMP_IRQ_EN_Bits.TBWC10_EN_IRQ */
#define IFX_GTM_CMP_IRQ_EN_TBWC10_EN_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_IRQ_EN_Bits.TBWC10_EN_IRQ */
#define IFX_GTM_CMP_IRQ_EN_TBWC10_EN_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_IRQ_EN_Bits.TBWC10_EN_IRQ */
#define IFX_GTM_CMP_IRQ_EN_TBWC10_EN_IRQ_OFF (22u)

/** \brief  Length for Ifx_GTM_CMP_IRQ_EN_Bits.TBWC11_EN_IRQ */
#define IFX_GTM_CMP_IRQ_EN_TBWC11_EN_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_IRQ_EN_Bits.TBWC11_EN_IRQ */
#define IFX_GTM_CMP_IRQ_EN_TBWC11_EN_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_IRQ_EN_Bits.TBWC11_EN_IRQ */
#define IFX_GTM_CMP_IRQ_EN_TBWC11_EN_IRQ_OFF (23u)

/** \brief  Length for Ifx_GTM_CMP_IRQ_EN_Bits.TBWC1_EN_IRQ */
#define IFX_GTM_CMP_IRQ_EN_TBWC1_EN_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_IRQ_EN_Bits.TBWC1_EN_IRQ */
#define IFX_GTM_CMP_IRQ_EN_TBWC1_EN_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_IRQ_EN_Bits.TBWC1_EN_IRQ */
#define IFX_GTM_CMP_IRQ_EN_TBWC1_EN_IRQ_OFF (13u)

/** \brief  Length for Ifx_GTM_CMP_IRQ_EN_Bits.TBWC2_EN_IRQ */
#define IFX_GTM_CMP_IRQ_EN_TBWC2_EN_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_IRQ_EN_Bits.TBWC2_EN_IRQ */
#define IFX_GTM_CMP_IRQ_EN_TBWC2_EN_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_IRQ_EN_Bits.TBWC2_EN_IRQ */
#define IFX_GTM_CMP_IRQ_EN_TBWC2_EN_IRQ_OFF (14u)

/** \brief  Length for Ifx_GTM_CMP_IRQ_EN_Bits.TBWC3_EN_IRQ */
#define IFX_GTM_CMP_IRQ_EN_TBWC3_EN_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_IRQ_EN_Bits.TBWC3_EN_IRQ */
#define IFX_GTM_CMP_IRQ_EN_TBWC3_EN_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_IRQ_EN_Bits.TBWC3_EN_IRQ */
#define IFX_GTM_CMP_IRQ_EN_TBWC3_EN_IRQ_OFF (15u)

/** \brief  Length for Ifx_GTM_CMP_IRQ_EN_Bits.TBWC4_EN_IRQ */
#define IFX_GTM_CMP_IRQ_EN_TBWC4_EN_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_IRQ_EN_Bits.TBWC4_EN_IRQ */
#define IFX_GTM_CMP_IRQ_EN_TBWC4_EN_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_IRQ_EN_Bits.TBWC4_EN_IRQ */
#define IFX_GTM_CMP_IRQ_EN_TBWC4_EN_IRQ_OFF (16u)

/** \brief  Length for Ifx_GTM_CMP_IRQ_EN_Bits.TBWC5_EN_IRQ */
#define IFX_GTM_CMP_IRQ_EN_TBWC5_EN_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_IRQ_EN_Bits.TBWC5_EN_IRQ */
#define IFX_GTM_CMP_IRQ_EN_TBWC5_EN_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_IRQ_EN_Bits.TBWC5_EN_IRQ */
#define IFX_GTM_CMP_IRQ_EN_TBWC5_EN_IRQ_OFF (17u)

/** \brief  Length for Ifx_GTM_CMP_IRQ_EN_Bits.TBWC6_EN_IRQ */
#define IFX_GTM_CMP_IRQ_EN_TBWC6_EN_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_IRQ_EN_Bits.TBWC6_EN_IRQ */
#define IFX_GTM_CMP_IRQ_EN_TBWC6_EN_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_IRQ_EN_Bits.TBWC6_EN_IRQ */
#define IFX_GTM_CMP_IRQ_EN_TBWC6_EN_IRQ_OFF (18u)

/** \brief  Length for Ifx_GTM_CMP_IRQ_EN_Bits.TBWC7_EN_IRQ */
#define IFX_GTM_CMP_IRQ_EN_TBWC7_EN_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_IRQ_EN_Bits.TBWC7_EN_IRQ */
#define IFX_GTM_CMP_IRQ_EN_TBWC7_EN_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_IRQ_EN_Bits.TBWC7_EN_IRQ */
#define IFX_GTM_CMP_IRQ_EN_TBWC7_EN_IRQ_OFF (19u)

/** \brief  Length for Ifx_GTM_CMP_IRQ_EN_Bits.TBWC8_EN_IRQ */
#define IFX_GTM_CMP_IRQ_EN_TBWC8_EN_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_IRQ_EN_Bits.TBWC8_EN_IRQ */
#define IFX_GTM_CMP_IRQ_EN_TBWC8_EN_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_IRQ_EN_Bits.TBWC8_EN_IRQ */
#define IFX_GTM_CMP_IRQ_EN_TBWC8_EN_IRQ_OFF (20u)

/** \brief  Length for Ifx_GTM_CMP_IRQ_EN_Bits.TBWC9_EN_IRQ */
#define IFX_GTM_CMP_IRQ_EN_TBWC9_EN_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_IRQ_EN_Bits.TBWC9_EN_IRQ */
#define IFX_GTM_CMP_IRQ_EN_TBWC9_EN_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_IRQ_EN_Bits.TBWC9_EN_IRQ */
#define IFX_GTM_CMP_IRQ_EN_TBWC9_EN_IRQ_OFF (21u)

/** \brief  Length for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_ABWC0 */
#define IFX_GTM_CMP_IRQ_FORCINT_TRG_ABWC0_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_ABWC0 */
#define IFX_GTM_CMP_IRQ_FORCINT_TRG_ABWC0_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_ABWC0 */
#define IFX_GTM_CMP_IRQ_FORCINT_TRG_ABWC0_OFF (0u)

/** \brief  Length for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_ABWC10 */
#define IFX_GTM_CMP_IRQ_FORCINT_TRG_ABWC10_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_ABWC10 */
#define IFX_GTM_CMP_IRQ_FORCINT_TRG_ABWC10_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_ABWC10 */
#define IFX_GTM_CMP_IRQ_FORCINT_TRG_ABWC10_OFF (10u)

/** \brief  Length for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_ABWC11 */
#define IFX_GTM_CMP_IRQ_FORCINT_TRG_ABWC11_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_ABWC11 */
#define IFX_GTM_CMP_IRQ_FORCINT_TRG_ABWC11_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_ABWC11 */
#define IFX_GTM_CMP_IRQ_FORCINT_TRG_ABWC11_OFF (11u)

/** \brief  Length for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_ABWC1 */
#define IFX_GTM_CMP_IRQ_FORCINT_TRG_ABWC1_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_ABWC1 */
#define IFX_GTM_CMP_IRQ_FORCINT_TRG_ABWC1_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_ABWC1 */
#define IFX_GTM_CMP_IRQ_FORCINT_TRG_ABWC1_OFF (1u)

/** \brief  Length for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_ABWC2 */
#define IFX_GTM_CMP_IRQ_FORCINT_TRG_ABWC2_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_ABWC2 */
#define IFX_GTM_CMP_IRQ_FORCINT_TRG_ABWC2_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_ABWC2 */
#define IFX_GTM_CMP_IRQ_FORCINT_TRG_ABWC2_OFF (2u)

/** \brief  Length for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_ABWC3 */
#define IFX_GTM_CMP_IRQ_FORCINT_TRG_ABWC3_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_ABWC3 */
#define IFX_GTM_CMP_IRQ_FORCINT_TRG_ABWC3_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_ABWC3 */
#define IFX_GTM_CMP_IRQ_FORCINT_TRG_ABWC3_OFF (3u)

/** \brief  Length for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_ABWC4 */
#define IFX_GTM_CMP_IRQ_FORCINT_TRG_ABWC4_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_ABWC4 */
#define IFX_GTM_CMP_IRQ_FORCINT_TRG_ABWC4_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_ABWC4 */
#define IFX_GTM_CMP_IRQ_FORCINT_TRG_ABWC4_OFF (4u)

/** \brief  Length for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_ABWC5 */
#define IFX_GTM_CMP_IRQ_FORCINT_TRG_ABWC5_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_ABWC5 */
#define IFX_GTM_CMP_IRQ_FORCINT_TRG_ABWC5_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_ABWC5 */
#define IFX_GTM_CMP_IRQ_FORCINT_TRG_ABWC5_OFF (5u)

/** \brief  Length for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_ABWC6 */
#define IFX_GTM_CMP_IRQ_FORCINT_TRG_ABWC6_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_ABWC6 */
#define IFX_GTM_CMP_IRQ_FORCINT_TRG_ABWC6_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_ABWC6 */
#define IFX_GTM_CMP_IRQ_FORCINT_TRG_ABWC6_OFF (6u)

/** \brief  Length for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_ABWC7 */
#define IFX_GTM_CMP_IRQ_FORCINT_TRG_ABWC7_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_ABWC7 */
#define IFX_GTM_CMP_IRQ_FORCINT_TRG_ABWC7_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_ABWC7 */
#define IFX_GTM_CMP_IRQ_FORCINT_TRG_ABWC7_OFF (7u)

/** \brief  Length for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_ABWC8 */
#define IFX_GTM_CMP_IRQ_FORCINT_TRG_ABWC8_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_ABWC8 */
#define IFX_GTM_CMP_IRQ_FORCINT_TRG_ABWC8_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_ABWC8 */
#define IFX_GTM_CMP_IRQ_FORCINT_TRG_ABWC8_OFF (8u)

/** \brief  Length for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_ABWC9 */
#define IFX_GTM_CMP_IRQ_FORCINT_TRG_ABWC9_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_ABWC9 */
#define IFX_GTM_CMP_IRQ_FORCINT_TRG_ABWC9_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_ABWC9 */
#define IFX_GTM_CMP_IRQ_FORCINT_TRG_ABWC9_OFF (9u)

/** \brief  Length for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_TBWC0 */
#define IFX_GTM_CMP_IRQ_FORCINT_TRG_TBWC0_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_TBWC0 */
#define IFX_GTM_CMP_IRQ_FORCINT_TRG_TBWC0_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_TBWC0 */
#define IFX_GTM_CMP_IRQ_FORCINT_TRG_TBWC0_OFF (12u)

/** \brief  Length for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_TBWC10 */
#define IFX_GTM_CMP_IRQ_FORCINT_TRG_TBWC10_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_TBWC10 */
#define IFX_GTM_CMP_IRQ_FORCINT_TRG_TBWC10_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_TBWC10 */
#define IFX_GTM_CMP_IRQ_FORCINT_TRG_TBWC10_OFF (22u)

/** \brief  Length for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_TBWC11 */
#define IFX_GTM_CMP_IRQ_FORCINT_TRG_TBWC11_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_TBWC11 */
#define IFX_GTM_CMP_IRQ_FORCINT_TRG_TBWC11_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_TBWC11 */
#define IFX_GTM_CMP_IRQ_FORCINT_TRG_TBWC11_OFF (23u)

/** \brief  Length for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_TBWC1 */
#define IFX_GTM_CMP_IRQ_FORCINT_TRG_TBWC1_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_TBWC1 */
#define IFX_GTM_CMP_IRQ_FORCINT_TRG_TBWC1_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_TBWC1 */
#define IFX_GTM_CMP_IRQ_FORCINT_TRG_TBWC1_OFF (13u)

/** \brief  Length for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_TBWC2 */
#define IFX_GTM_CMP_IRQ_FORCINT_TRG_TBWC2_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_TBWC2 */
#define IFX_GTM_CMP_IRQ_FORCINT_TRG_TBWC2_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_TBWC2 */
#define IFX_GTM_CMP_IRQ_FORCINT_TRG_TBWC2_OFF (14u)

/** \brief  Length for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_TBWC3 */
#define IFX_GTM_CMP_IRQ_FORCINT_TRG_TBWC3_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_TBWC3 */
#define IFX_GTM_CMP_IRQ_FORCINT_TRG_TBWC3_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_TBWC3 */
#define IFX_GTM_CMP_IRQ_FORCINT_TRG_TBWC3_OFF (15u)

/** \brief  Length for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_TBWC4 */
#define IFX_GTM_CMP_IRQ_FORCINT_TRG_TBWC4_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_TBWC4 */
#define IFX_GTM_CMP_IRQ_FORCINT_TRG_TBWC4_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_TBWC4 */
#define IFX_GTM_CMP_IRQ_FORCINT_TRG_TBWC4_OFF (16u)

/** \brief  Length for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_TBWC5 */
#define IFX_GTM_CMP_IRQ_FORCINT_TRG_TBWC5_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_TBWC5 */
#define IFX_GTM_CMP_IRQ_FORCINT_TRG_TBWC5_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_TBWC5 */
#define IFX_GTM_CMP_IRQ_FORCINT_TRG_TBWC5_OFF (17u)

/** \brief  Length for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_TBWC6 */
#define IFX_GTM_CMP_IRQ_FORCINT_TRG_TBWC6_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_TBWC6 */
#define IFX_GTM_CMP_IRQ_FORCINT_TRG_TBWC6_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_TBWC6 */
#define IFX_GTM_CMP_IRQ_FORCINT_TRG_TBWC6_OFF (18u)

/** \brief  Length for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_TBWC7 */
#define IFX_GTM_CMP_IRQ_FORCINT_TRG_TBWC7_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_TBWC7 */
#define IFX_GTM_CMP_IRQ_FORCINT_TRG_TBWC7_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_TBWC7 */
#define IFX_GTM_CMP_IRQ_FORCINT_TRG_TBWC7_OFF (19u)

/** \brief  Length for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_TBWC8 */
#define IFX_GTM_CMP_IRQ_FORCINT_TRG_TBWC8_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_TBWC8 */
#define IFX_GTM_CMP_IRQ_FORCINT_TRG_TBWC8_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_TBWC8 */
#define IFX_GTM_CMP_IRQ_FORCINT_TRG_TBWC8_OFF (20u)

/** \brief  Length for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_TBWC9 */
#define IFX_GTM_CMP_IRQ_FORCINT_TRG_TBWC9_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_TBWC9 */
#define IFX_GTM_CMP_IRQ_FORCINT_TRG_TBWC9_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_IRQ_FORCINT_Bits.TRG_TBWC9 */
#define IFX_GTM_CMP_IRQ_FORCINT_TRG_TBWC9_OFF (21u)

/** \brief  Length for Ifx_GTM_CMP_IRQ_MODE_Bits.IRQ_MODE */
#define IFX_GTM_CMP_IRQ_MODE_IRQ_MODE_LEN (2u)

/** \brief  Mask for Ifx_GTM_CMP_IRQ_MODE_Bits.IRQ_MODE */
#define IFX_GTM_CMP_IRQ_MODE_IRQ_MODE_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_CMP_IRQ_MODE_Bits.IRQ_MODE */
#define IFX_GTM_CMP_IRQ_MODE_IRQ_MODE_OFF (0u)

/** \brief  Length for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.ABWC0 */
#define IFX_GTM_CMP_IRQ_NOTIFY_ABWC0_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.ABWC0 */
#define IFX_GTM_CMP_IRQ_NOTIFY_ABWC0_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.ABWC0 */
#define IFX_GTM_CMP_IRQ_NOTIFY_ABWC0_OFF (0u)

/** \brief  Length for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.ABWC10 */
#define IFX_GTM_CMP_IRQ_NOTIFY_ABWC10_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.ABWC10 */
#define IFX_GTM_CMP_IRQ_NOTIFY_ABWC10_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.ABWC10 */
#define IFX_GTM_CMP_IRQ_NOTIFY_ABWC10_OFF (10u)

/** \brief  Length for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.ABWC11 */
#define IFX_GTM_CMP_IRQ_NOTIFY_ABWC11_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.ABWC11 */
#define IFX_GTM_CMP_IRQ_NOTIFY_ABWC11_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.ABWC11 */
#define IFX_GTM_CMP_IRQ_NOTIFY_ABWC11_OFF (11u)

/** \brief  Length for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.ABWC1 */
#define IFX_GTM_CMP_IRQ_NOTIFY_ABWC1_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.ABWC1 */
#define IFX_GTM_CMP_IRQ_NOTIFY_ABWC1_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.ABWC1 */
#define IFX_GTM_CMP_IRQ_NOTIFY_ABWC1_OFF (1u)

/** \brief  Length for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.ABWC2 */
#define IFX_GTM_CMP_IRQ_NOTIFY_ABWC2_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.ABWC2 */
#define IFX_GTM_CMP_IRQ_NOTIFY_ABWC2_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.ABWC2 */
#define IFX_GTM_CMP_IRQ_NOTIFY_ABWC2_OFF (2u)

/** \brief  Length for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.ABWC3 */
#define IFX_GTM_CMP_IRQ_NOTIFY_ABWC3_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.ABWC3 */
#define IFX_GTM_CMP_IRQ_NOTIFY_ABWC3_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.ABWC3 */
#define IFX_GTM_CMP_IRQ_NOTIFY_ABWC3_OFF (3u)

/** \brief  Length for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.ABWC4 */
#define IFX_GTM_CMP_IRQ_NOTIFY_ABWC4_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.ABWC4 */
#define IFX_GTM_CMP_IRQ_NOTIFY_ABWC4_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.ABWC4 */
#define IFX_GTM_CMP_IRQ_NOTIFY_ABWC4_OFF (4u)

/** \brief  Length for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.ABWC5 */
#define IFX_GTM_CMP_IRQ_NOTIFY_ABWC5_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.ABWC5 */
#define IFX_GTM_CMP_IRQ_NOTIFY_ABWC5_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.ABWC5 */
#define IFX_GTM_CMP_IRQ_NOTIFY_ABWC5_OFF (5u)

/** \brief  Length for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.ABWC6 */
#define IFX_GTM_CMP_IRQ_NOTIFY_ABWC6_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.ABWC6 */
#define IFX_GTM_CMP_IRQ_NOTIFY_ABWC6_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.ABWC6 */
#define IFX_GTM_CMP_IRQ_NOTIFY_ABWC6_OFF (6u)

/** \brief  Length for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.ABWC7 */
#define IFX_GTM_CMP_IRQ_NOTIFY_ABWC7_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.ABWC7 */
#define IFX_GTM_CMP_IRQ_NOTIFY_ABWC7_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.ABWC7 */
#define IFX_GTM_CMP_IRQ_NOTIFY_ABWC7_OFF (7u)

/** \brief  Length for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.ABWC8 */
#define IFX_GTM_CMP_IRQ_NOTIFY_ABWC8_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.ABWC8 */
#define IFX_GTM_CMP_IRQ_NOTIFY_ABWC8_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.ABWC8 */
#define IFX_GTM_CMP_IRQ_NOTIFY_ABWC8_OFF (8u)

/** \brief  Length for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.ABWC9 */
#define IFX_GTM_CMP_IRQ_NOTIFY_ABWC9_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.ABWC9 */
#define IFX_GTM_CMP_IRQ_NOTIFY_ABWC9_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.ABWC9 */
#define IFX_GTM_CMP_IRQ_NOTIFY_ABWC9_OFF (9u)

/** \brief  Length for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.TBWC0 */
#define IFX_GTM_CMP_IRQ_NOTIFY_TBWC0_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.TBWC0 */
#define IFX_GTM_CMP_IRQ_NOTIFY_TBWC0_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.TBWC0 */
#define IFX_GTM_CMP_IRQ_NOTIFY_TBWC0_OFF (12u)

/** \brief  Length for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.TBWC10 */
#define IFX_GTM_CMP_IRQ_NOTIFY_TBWC10_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.TBWC10 */
#define IFX_GTM_CMP_IRQ_NOTIFY_TBWC10_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.TBWC10 */
#define IFX_GTM_CMP_IRQ_NOTIFY_TBWC10_OFF (22u)

/** \brief  Length for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.TBWC11 */
#define IFX_GTM_CMP_IRQ_NOTIFY_TBWC11_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.TBWC11 */
#define IFX_GTM_CMP_IRQ_NOTIFY_TBWC11_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.TBWC11 */
#define IFX_GTM_CMP_IRQ_NOTIFY_TBWC11_OFF (23u)

/** \brief  Length for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.TBWC1 */
#define IFX_GTM_CMP_IRQ_NOTIFY_TBWC1_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.TBWC1 */
#define IFX_GTM_CMP_IRQ_NOTIFY_TBWC1_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.TBWC1 */
#define IFX_GTM_CMP_IRQ_NOTIFY_TBWC1_OFF (13u)

/** \brief  Length for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.TBWC2 */
#define IFX_GTM_CMP_IRQ_NOTIFY_TBWC2_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.TBWC2 */
#define IFX_GTM_CMP_IRQ_NOTIFY_TBWC2_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.TBWC2 */
#define IFX_GTM_CMP_IRQ_NOTIFY_TBWC2_OFF (14u)

/** \brief  Length for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.TBWC3 */
#define IFX_GTM_CMP_IRQ_NOTIFY_TBWC3_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.TBWC3 */
#define IFX_GTM_CMP_IRQ_NOTIFY_TBWC3_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.TBWC3 */
#define IFX_GTM_CMP_IRQ_NOTIFY_TBWC3_OFF (15u)

/** \brief  Length for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.TBWC4 */
#define IFX_GTM_CMP_IRQ_NOTIFY_TBWC4_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.TBWC4 */
#define IFX_GTM_CMP_IRQ_NOTIFY_TBWC4_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.TBWC4 */
#define IFX_GTM_CMP_IRQ_NOTIFY_TBWC4_OFF (16u)

/** \brief  Length for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.TBWC5 */
#define IFX_GTM_CMP_IRQ_NOTIFY_TBWC5_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.TBWC5 */
#define IFX_GTM_CMP_IRQ_NOTIFY_TBWC5_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.TBWC5 */
#define IFX_GTM_CMP_IRQ_NOTIFY_TBWC5_OFF (17u)

/** \brief  Length for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.TBWC6 */
#define IFX_GTM_CMP_IRQ_NOTIFY_TBWC6_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.TBWC6 */
#define IFX_GTM_CMP_IRQ_NOTIFY_TBWC6_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.TBWC6 */
#define IFX_GTM_CMP_IRQ_NOTIFY_TBWC6_OFF (18u)

/** \brief  Length for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.TBWC7 */
#define IFX_GTM_CMP_IRQ_NOTIFY_TBWC7_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.TBWC7 */
#define IFX_GTM_CMP_IRQ_NOTIFY_TBWC7_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.TBWC7 */
#define IFX_GTM_CMP_IRQ_NOTIFY_TBWC7_OFF (19u)

/** \brief  Length for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.TBWC8 */
#define IFX_GTM_CMP_IRQ_NOTIFY_TBWC8_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.TBWC8 */
#define IFX_GTM_CMP_IRQ_NOTIFY_TBWC8_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.TBWC8 */
#define IFX_GTM_CMP_IRQ_NOTIFY_TBWC8_OFF (20u)

/** \brief  Length for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.TBWC9 */
#define IFX_GTM_CMP_IRQ_NOTIFY_TBWC9_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.TBWC9 */
#define IFX_GTM_CMP_IRQ_NOTIFY_TBWC9_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMP_IRQ_NOTIFY_Bits.TBWC9 */
#define IFX_GTM_CMP_IRQ_NOTIFY_TBWC9_OFF (21u)

/** \brief  Length for Ifx_GTM_CMU_CLK0_5_CTRL_Bits.CLK_CNT */
#define IFX_GTM_CMU_CLK0_5_CTRL_CLK_CNT_LEN (24u)

/** \brief  Mask for Ifx_GTM_CMU_CLK0_5_CTRL_Bits.CLK_CNT */
#define IFX_GTM_CMU_CLK0_5_CTRL_CLK_CNT_MSK (0xffffffu)

/** \brief  Offset for Ifx_GTM_CMU_CLK0_5_CTRL_Bits.CLK_CNT */
#define IFX_GTM_CMU_CLK0_5_CTRL_CLK_CNT_OFF (0u)

/** \brief  Length for Ifx_GTM_CMU_CLK_6_CTRL_Bits.CLK6_SEL */
#define IFX_GTM_CMU_CLK_6_CTRL_CLK6_SEL_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMU_CLK_6_CTRL_Bits.CLK6_SEL */
#define IFX_GTM_CMU_CLK_6_CTRL_CLK6_SEL_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMU_CLK_6_CTRL_Bits.CLK6_SEL */
#define IFX_GTM_CMU_CLK_6_CTRL_CLK6_SEL_OFF (24u)

/** \brief  Length for Ifx_GTM_CMU_CLK_6_CTRL_Bits.CLK_CNT */
#define IFX_GTM_CMU_CLK_6_CTRL_CLK_CNT_LEN (24u)

/** \brief  Mask for Ifx_GTM_CMU_CLK_6_CTRL_Bits.CLK_CNT */
#define IFX_GTM_CMU_CLK_6_CTRL_CLK_CNT_MSK (0xffffffu)

/** \brief  Offset for Ifx_GTM_CMU_CLK_6_CTRL_Bits.CLK_CNT */
#define IFX_GTM_CMU_CLK_6_CTRL_CLK_CNT_OFF (0u)

/** \brief  Length for Ifx_GTM_CMU_CLK_7_CTRL_Bits.CLK7_SEL */
#define IFX_GTM_CMU_CLK_7_CTRL_CLK7_SEL_LEN (1u)

/** \brief  Mask for Ifx_GTM_CMU_CLK_7_CTRL_Bits.CLK7_SEL */
#define IFX_GTM_CMU_CLK_7_CTRL_CLK7_SEL_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CMU_CLK_7_CTRL_Bits.CLK7_SEL */
#define IFX_GTM_CMU_CLK_7_CTRL_CLK7_SEL_OFF (24u)

/** \brief  Length for Ifx_GTM_CMU_CLK_7_CTRL_Bits.CLK_CNT */
#define IFX_GTM_CMU_CLK_7_CTRL_CLK_CNT_LEN (24u)

/** \brief  Mask for Ifx_GTM_CMU_CLK_7_CTRL_Bits.CLK_CNT */
#define IFX_GTM_CMU_CLK_7_CTRL_CLK_CNT_MSK (0xffffffu)

/** \brief  Offset for Ifx_GTM_CMU_CLK_7_CTRL_Bits.CLK_CNT */
#define IFX_GTM_CMU_CLK_7_CTRL_CLK_CNT_OFF (0u)

/** \brief  Length for Ifx_GTM_CMU_CLK_EN_Bits.EN_CLK0 */
#define IFX_GTM_CMU_CLK_EN_EN_CLK0_LEN (2u)

/** \brief  Mask for Ifx_GTM_CMU_CLK_EN_Bits.EN_CLK0 */
#define IFX_GTM_CMU_CLK_EN_EN_CLK0_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_CMU_CLK_EN_Bits.EN_CLK0 */
#define IFX_GTM_CMU_CLK_EN_EN_CLK0_OFF (0u)

/** \brief  Length for Ifx_GTM_CMU_CLK_EN_Bits.EN_CLK1 */
#define IFX_GTM_CMU_CLK_EN_EN_CLK1_LEN (2u)

/** \brief  Mask for Ifx_GTM_CMU_CLK_EN_Bits.EN_CLK1 */
#define IFX_GTM_CMU_CLK_EN_EN_CLK1_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_CMU_CLK_EN_Bits.EN_CLK1 */
#define IFX_GTM_CMU_CLK_EN_EN_CLK1_OFF (2u)

/** \brief  Length for Ifx_GTM_CMU_CLK_EN_Bits.EN_CLK2 */
#define IFX_GTM_CMU_CLK_EN_EN_CLK2_LEN (2u)

/** \brief  Mask for Ifx_GTM_CMU_CLK_EN_Bits.EN_CLK2 */
#define IFX_GTM_CMU_CLK_EN_EN_CLK2_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_CMU_CLK_EN_Bits.EN_CLK2 */
#define IFX_GTM_CMU_CLK_EN_EN_CLK2_OFF (4u)

/** \brief  Length for Ifx_GTM_CMU_CLK_EN_Bits.EN_CLK3 */
#define IFX_GTM_CMU_CLK_EN_EN_CLK3_LEN (2u)

/** \brief  Mask for Ifx_GTM_CMU_CLK_EN_Bits.EN_CLK3 */
#define IFX_GTM_CMU_CLK_EN_EN_CLK3_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_CMU_CLK_EN_Bits.EN_CLK3 */
#define IFX_GTM_CMU_CLK_EN_EN_CLK3_OFF (6u)

/** \brief  Length for Ifx_GTM_CMU_CLK_EN_Bits.EN_CLK4 */
#define IFX_GTM_CMU_CLK_EN_EN_CLK4_LEN (2u)

/** \brief  Mask for Ifx_GTM_CMU_CLK_EN_Bits.EN_CLK4 */
#define IFX_GTM_CMU_CLK_EN_EN_CLK4_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_CMU_CLK_EN_Bits.EN_CLK4 */
#define IFX_GTM_CMU_CLK_EN_EN_CLK4_OFF (8u)

/** \brief  Length for Ifx_GTM_CMU_CLK_EN_Bits.EN_CLK5 */
#define IFX_GTM_CMU_CLK_EN_EN_CLK5_LEN (2u)

/** \brief  Mask for Ifx_GTM_CMU_CLK_EN_Bits.EN_CLK5 */
#define IFX_GTM_CMU_CLK_EN_EN_CLK5_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_CMU_CLK_EN_Bits.EN_CLK5 */
#define IFX_GTM_CMU_CLK_EN_EN_CLK5_OFF (10u)

/** \brief  Length for Ifx_GTM_CMU_CLK_EN_Bits.EN_CLK6 */
#define IFX_GTM_CMU_CLK_EN_EN_CLK6_LEN (2u)

/** \brief  Mask for Ifx_GTM_CMU_CLK_EN_Bits.EN_CLK6 */
#define IFX_GTM_CMU_CLK_EN_EN_CLK6_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_CMU_CLK_EN_Bits.EN_CLK6 */
#define IFX_GTM_CMU_CLK_EN_EN_CLK6_OFF (12u)

/** \brief  Length for Ifx_GTM_CMU_CLK_EN_Bits.EN_CLK7 */
#define IFX_GTM_CMU_CLK_EN_EN_CLK7_LEN (2u)

/** \brief  Mask for Ifx_GTM_CMU_CLK_EN_Bits.EN_CLK7 */
#define IFX_GTM_CMU_CLK_EN_EN_CLK7_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_CMU_CLK_EN_Bits.EN_CLK7 */
#define IFX_GTM_CMU_CLK_EN_EN_CLK7_OFF (14u)

/** \brief  Length for Ifx_GTM_CMU_CLK_EN_Bits.EN_ECLK0 */
#define IFX_GTM_CMU_CLK_EN_EN_ECLK0_LEN (2u)

/** \brief  Mask for Ifx_GTM_CMU_CLK_EN_Bits.EN_ECLK0 */
#define IFX_GTM_CMU_CLK_EN_EN_ECLK0_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_CMU_CLK_EN_Bits.EN_ECLK0 */
#define IFX_GTM_CMU_CLK_EN_EN_ECLK0_OFF (16u)

/** \brief  Length for Ifx_GTM_CMU_CLK_EN_Bits.EN_ECLK1 */
#define IFX_GTM_CMU_CLK_EN_EN_ECLK1_LEN (2u)

/** \brief  Mask for Ifx_GTM_CMU_CLK_EN_Bits.EN_ECLK1 */
#define IFX_GTM_CMU_CLK_EN_EN_ECLK1_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_CMU_CLK_EN_Bits.EN_ECLK1 */
#define IFX_GTM_CMU_CLK_EN_EN_ECLK1_OFF (18u)

/** \brief  Length for Ifx_GTM_CMU_CLK_EN_Bits.EN_ECLK2 */
#define IFX_GTM_CMU_CLK_EN_EN_ECLK2_LEN (2u)

/** \brief  Mask for Ifx_GTM_CMU_CLK_EN_Bits.EN_ECLK2 */
#define IFX_GTM_CMU_CLK_EN_EN_ECLK2_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_CMU_CLK_EN_Bits.EN_ECLK2 */
#define IFX_GTM_CMU_CLK_EN_EN_ECLK2_OFF (20u)

/** \brief  Length for Ifx_GTM_CMU_CLK_EN_Bits.EN_FXCLK */
#define IFX_GTM_CMU_CLK_EN_EN_FXCLK_LEN (2u)

/** \brief  Mask for Ifx_GTM_CMU_CLK_EN_Bits.EN_FXCLK */
#define IFX_GTM_CMU_CLK_EN_EN_FXCLK_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_CMU_CLK_EN_Bits.EN_FXCLK */
#define IFX_GTM_CMU_CLK_EN_EN_FXCLK_OFF (22u)

/** \brief  Length for Ifx_GTM_CMU_ECLK_DEN_Bits.ECLK_DEN */
#define IFX_GTM_CMU_ECLK_DEN_ECLK_DEN_LEN (24u)

/** \brief  Mask for Ifx_GTM_CMU_ECLK_DEN_Bits.ECLK_DEN */
#define IFX_GTM_CMU_ECLK_DEN_ECLK_DEN_MSK (0xffffffu)

/** \brief  Offset for Ifx_GTM_CMU_ECLK_DEN_Bits.ECLK_DEN */
#define IFX_GTM_CMU_ECLK_DEN_ECLK_DEN_OFF (0u)

/** \brief  Length for Ifx_GTM_CMU_ECLK_NUM_Bits.ECLK_NUM */
#define IFX_GTM_CMU_ECLK_NUM_ECLK_NUM_LEN (24u)

/** \brief  Mask for Ifx_GTM_CMU_ECLK_NUM_Bits.ECLK_NUM */
#define IFX_GTM_CMU_ECLK_NUM_ECLK_NUM_MSK (0xffffffu)

/** \brief  Offset for Ifx_GTM_CMU_ECLK_NUM_Bits.ECLK_NUM */
#define IFX_GTM_CMU_ECLK_NUM_ECLK_NUM_OFF (0u)

/** \brief  Length for Ifx_GTM_CMU_FXCLK_CTRL_Bits.FXCLK_SEL */
#define IFX_GTM_CMU_FXCLK_CTRL_FXCLK_SEL_LEN (4u)

/** \brief  Mask for Ifx_GTM_CMU_FXCLK_CTRL_Bits.FXCLK_SEL */
#define IFX_GTM_CMU_FXCLK_CTRL_FXCLK_SEL_MSK (0xfu)

/** \brief  Offset for Ifx_GTM_CMU_FXCLK_CTRL_Bits.FXCLK_SEL */
#define IFX_GTM_CMU_FXCLK_CTRL_FXCLK_SEL_OFF (0u)

/** \brief  Length for Ifx_GTM_CMU_GCLK_DEN_Bits.GCLK_DEN */
#define IFX_GTM_CMU_GCLK_DEN_GCLK_DEN_LEN (24u)

/** \brief  Mask for Ifx_GTM_CMU_GCLK_DEN_Bits.GCLK_DEN */
#define IFX_GTM_CMU_GCLK_DEN_GCLK_DEN_MSK (0xffffffu)

/** \brief  Offset for Ifx_GTM_CMU_GCLK_DEN_Bits.GCLK_DEN */
#define IFX_GTM_CMU_GCLK_DEN_GCLK_DEN_OFF (0u)

/** \brief  Length for Ifx_GTM_CMU_GCLK_NUM_Bits.GCLK_NUM */
#define IFX_GTM_CMU_GCLK_NUM_GCLK_NUM_LEN (24u)

/** \brief  Mask for Ifx_GTM_CMU_GCLK_NUM_Bits.GCLK_NUM */
#define IFX_GTM_CMU_GCLK_NUM_GCLK_NUM_MSK (0xffffffu)

/** \brief  Offset for Ifx_GTM_CMU_GCLK_NUM_Bits.GCLK_NUM */
#define IFX_GTM_CMU_GCLK_NUM_GCLK_NUM_OFF (0u)

/** \brief  Length for Ifx_GTM_CTRL_Bits.RF_PROT */
#define IFX_GTM_CTRL_RF_PROT_LEN (1u)

/** \brief  Mask for Ifx_GTM_CTRL_Bits.RF_PROT */
#define IFX_GTM_CTRL_RF_PROT_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CTRL_Bits.RF_PROT */
#define IFX_GTM_CTRL_RF_PROT_OFF (0u)

/** \brief  Length for Ifx_GTM_CTRL_Bits.TO_MODE */
#define IFX_GTM_CTRL_TO_MODE_LEN (1u)

/** \brief  Mask for Ifx_GTM_CTRL_Bits.TO_MODE */
#define IFX_GTM_CTRL_TO_MODE_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_CTRL_Bits.TO_MODE */
#define IFX_GTM_CTRL_TO_MODE_OFF (1u)

/** \brief  Length for Ifx_GTM_CTRL_Bits.TO_VAL */
#define IFX_GTM_CTRL_TO_VAL_LEN (5u)

/** \brief  Mask for Ifx_GTM_CTRL_Bits.TO_VAL */
#define IFX_GTM_CTRL_TO_VAL_MSK (0x1fu)

/** \brief  Offset for Ifx_GTM_CTRL_Bits.TO_VAL */
#define IFX_GTM_CTRL_TO_VAL_OFF (4u)

/** \brief  Length for Ifx_GTM_DATAIN_Bits.DATA */
#define IFX_GTM_DATAIN_DATA_LEN (32u)

/** \brief  Mask for Ifx_GTM_DATAIN_Bits.DATA */
#define IFX_GTM_DATAIN_DATA_MSK (0xffffffffu)

/** \brief  Offset for Ifx_GTM_DATAIN_Bits.DATA */
#define IFX_GTM_DATAIN_DATA_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_ACB_Bits.ACB_0 */
#define IFX_GTM_DPLL_ACB_ACB_0_LEN (5u)

/** \brief  Mask for Ifx_GTM_DPLL_ACB_Bits.ACB_0 */
#define IFX_GTM_DPLL_ACB_ACB_0_MSK (0x1fu)

/** \brief  Offset for Ifx_GTM_DPLL_ACB_Bits.ACB_0 */
#define IFX_GTM_DPLL_ACB_ACB_0_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_ACB_Bits.ACB_1 */
#define IFX_GTM_DPLL_ACB_ACB_1_LEN (5u)

/** \brief  Mask for Ifx_GTM_DPLL_ACB_Bits.ACB_1 */
#define IFX_GTM_DPLL_ACB_ACB_1_MSK (0x1fu)

/** \brief  Offset for Ifx_GTM_DPLL_ACB_Bits.ACB_1 */
#define IFX_GTM_DPLL_ACB_ACB_1_OFF (8u)

/** \brief  Length for Ifx_GTM_DPLL_ACB_Bits.ACB_2 */
#define IFX_GTM_DPLL_ACB_ACB_2_LEN (5u)

/** \brief  Mask for Ifx_GTM_DPLL_ACB_Bits.ACB_2 */
#define IFX_GTM_DPLL_ACB_ACB_2_MSK (0x1fu)

/** \brief  Offset for Ifx_GTM_DPLL_ACB_Bits.ACB_2 */
#define IFX_GTM_DPLL_ACB_ACB_2_OFF (16u)

/** \brief  Length for Ifx_GTM_DPLL_ACB_Bits.ACB_3 */
#define IFX_GTM_DPLL_ACB_ACB_3_LEN (5u)

/** \brief  Mask for Ifx_GTM_DPLL_ACB_Bits.ACB_3 */
#define IFX_GTM_DPLL_ACB_ACB_3_MSK (0x1fu)

/** \brief  Offset for Ifx_GTM_DPLL_ACB_Bits.ACB_3 */
#define IFX_GTM_DPLL_ACB_ACB_3_OFF (24u)

/** \brief  Length for Ifx_GTM_DPLL_ACT_STA_Bits.ACT_Ni */
#define IFX_GTM_DPLL_ACT_STA_ACT_NI_LEN (24u)

/** \brief  Mask for Ifx_GTM_DPLL_ACT_STA_Bits.ACT_Ni */
#define IFX_GTM_DPLL_ACT_STA_ACT_NI_MSK (0xffffffu)

/** \brief  Offset for Ifx_GTM_DPLL_ACT_STA_Bits.ACT_Ni */
#define IFX_GTM_DPLL_ACT_STA_ACT_NI_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_ADD_IN_CAL1_Bits.ADD_IN_CAL_1 */
#define IFX_GTM_DPLL_ADD_IN_CAL1_ADD_IN_CAL_1_LEN (24u)

/** \brief  Mask for Ifx_GTM_DPLL_ADD_IN_CAL1_Bits.ADD_IN_CAL_1 */
#define IFX_GTM_DPLL_ADD_IN_CAL1_ADD_IN_CAL_1_MSK (0xffffffu)

/** \brief  Offset for Ifx_GTM_DPLL_ADD_IN_CAL1_Bits.ADD_IN_CAL_1 */
#define IFX_GTM_DPLL_ADD_IN_CAL1_ADD_IN_CAL_1_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_ADD_IN_CAL2_Bits.ADD_IN_CAL_2 */
#define IFX_GTM_DPLL_ADD_IN_CAL2_ADD_IN_CAL_2_LEN (24u)

/** \brief  Mask for Ifx_GTM_DPLL_ADD_IN_CAL2_Bits.ADD_IN_CAL_2 */
#define IFX_GTM_DPLL_ADD_IN_CAL2_ADD_IN_CAL_2_MSK (0xffffffu)

/** \brief  Offset for Ifx_GTM_DPLL_ADD_IN_CAL2_Bits.ADD_IN_CAL_2 */
#define IFX_GTM_DPLL_ADD_IN_CAL2_ADD_IN_CAL_2_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_ADD_IN_LD1_Bits.ADD_IN_LD_1 */
#define IFX_GTM_DPLL_ADD_IN_LD1_ADD_IN_LD_1_LEN (24u)

/** \brief  Mask for Ifx_GTM_DPLL_ADD_IN_LD1_Bits.ADD_IN_LD_1 */
#define IFX_GTM_DPLL_ADD_IN_LD1_ADD_IN_LD_1_MSK (0xffffffu)

/** \brief  Offset for Ifx_GTM_DPLL_ADD_IN_LD1_Bits.ADD_IN_LD_1 */
#define IFX_GTM_DPLL_ADD_IN_LD1_ADD_IN_LD_1_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_ADD_IN_LD2_Bits.ADD_IN_LD_2 */
#define IFX_GTM_DPLL_ADD_IN_LD2_ADD_IN_LD_2_LEN (24u)

/** \brief  Mask for Ifx_GTM_DPLL_ADD_IN_LD2_Bits.ADD_IN_LD_2 */
#define IFX_GTM_DPLL_ADD_IN_LD2_ADD_IN_LD_2_MSK (0xffffffu)

/** \brief  Offset for Ifx_GTM_DPLL_ADD_IN_LD2_Bits.ADD_IN_LD_2 */
#define IFX_GTM_DPLL_ADD_IN_LD2_ADD_IN_LD_2_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_ADT_S_Bits.NS */
#define IFX_GTM_DPLL_ADT_S_NS_LEN (6u)

/** \brief  Mask for Ifx_GTM_DPLL_ADT_S_Bits.NS */
#define IFX_GTM_DPLL_ADT_S_NS_MSK (0x3fu)

/** \brief  Offset for Ifx_GTM_DPLL_ADT_S_Bits.NS */
#define IFX_GTM_DPLL_ADT_S_NS_OFF (16u)

/** \brief  Length for Ifx_GTM_DPLL_ADT_S_Bits.PD_S */
#define IFX_GTM_DPLL_ADT_S_PD_S_LEN (16u)

/** \brief  Mask for Ifx_GTM_DPLL_ADT_S_Bits.PD_S */
#define IFX_GTM_DPLL_ADT_S_PD_S_MSK (0xffffu)

/** \brief  Offset for Ifx_GTM_DPLL_ADT_S_Bits.PD_S */
#define IFX_GTM_DPLL_ADT_S_PD_S_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_AOSV_2_Bits.AOSV_2A */
#define IFX_GTM_DPLL_AOSV_2_AOSV_2A_LEN (8u)

/** \brief  Mask for Ifx_GTM_DPLL_AOSV_2_Bits.AOSV_2A */
#define IFX_GTM_DPLL_AOSV_2_AOSV_2A_MSK (0xffu)

/** \brief  Offset for Ifx_GTM_DPLL_AOSV_2_Bits.AOSV_2A */
#define IFX_GTM_DPLL_AOSV_2_AOSV_2A_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_AOSV_2_Bits.AOSV_2B */
#define IFX_GTM_DPLL_AOSV_2_AOSV_2B_LEN (8u)

/** \brief  Mask for Ifx_GTM_DPLL_AOSV_2_Bits.AOSV_2B */
#define IFX_GTM_DPLL_AOSV_2_AOSV_2B_MSK (0xffu)

/** \brief  Offset for Ifx_GTM_DPLL_AOSV_2_Bits.AOSV_2B */
#define IFX_GTM_DPLL_AOSV_2_AOSV_2B_OFF (8u)

/** \brief  Length for Ifx_GTM_DPLL_AOSV_2_Bits.AOSV_2C */
#define IFX_GTM_DPLL_AOSV_2_AOSV_2C_LEN (8u)

/** \brief  Mask for Ifx_GTM_DPLL_AOSV_2_Bits.AOSV_2C */
#define IFX_GTM_DPLL_AOSV_2_AOSV_2C_MSK (0xffu)

/** \brief  Offset for Ifx_GTM_DPLL_AOSV_2_Bits.AOSV_2C */
#define IFX_GTM_DPLL_AOSV_2_AOSV_2C_OFF (16u)

/** \brief  Length for Ifx_GTM_DPLL_AOSV_2_Bits.AOSV_2D */
#define IFX_GTM_DPLL_AOSV_2_AOSV_2D_LEN (8u)

/** \brief  Mask for Ifx_GTM_DPLL_AOSV_2_Bits.AOSV_2D */
#define IFX_GTM_DPLL_AOSV_2_AOSV_2D_MSK (0xffu)

/** \brief  Offset for Ifx_GTM_DPLL_AOSV_2_Bits.AOSV_2D */
#define IFX_GTM_DPLL_AOSV_2_AOSV_2D_OFF (24u)

/** \brief  Length for Ifx_GTM_DPLL_APS_1C3_Bits.APS_1C3 */
#define IFX_GTM_DPLL_APS_1C3_APS_1C3_LEN (6u)

/** \brief  Mask for Ifx_GTM_DPLL_APS_1C3_Bits.APS_1C3 */
#define IFX_GTM_DPLL_APS_1C3_APS_1C3_MSK (0x3fu)

/** \brief  Offset for Ifx_GTM_DPLL_APS_1C3_Bits.APS_1C3 */
#define IFX_GTM_DPLL_APS_1C3_APS_1C3_OFF (2u)

/** \brief  Length for Ifx_GTM_DPLL_APS_Bits.APS_1C2 */
#define IFX_GTM_DPLL_APS_APS_1C2_LEN (6u)

/** \brief  Mask for Ifx_GTM_DPLL_APS_Bits.APS_1C2 */
#define IFX_GTM_DPLL_APS_APS_1C2_MSK (0x3fu)

/** \brief  Offset for Ifx_GTM_DPLL_APS_Bits.APS_1C2 */
#define IFX_GTM_DPLL_APS_APS_1C2_OFF (14u)

/** \brief  Length for Ifx_GTM_DPLL_APS_Bits.APS */
#define IFX_GTM_DPLL_APS_APS_LEN (6u)

/** \brief  Mask for Ifx_GTM_DPLL_APS_Bits.APS */
#define IFX_GTM_DPLL_APS_APS_MSK (0x3fu)

/** \brief  Offset for Ifx_GTM_DPLL_APS_Bits.APS */
#define IFX_GTM_DPLL_APS_APS_OFF (2u)

/** \brief  Length for Ifx_GTM_DPLL_APS_SYNC_Bits.APS_1C2_EXT */
#define IFX_GTM_DPLL_APS_SYNC_APS_1C2_EXT_LEN (6u)

/** \brief  Mask for Ifx_GTM_DPLL_APS_SYNC_Bits.APS_1C2_EXT */
#define IFX_GTM_DPLL_APS_SYNC_APS_1C2_EXT_MSK (0x3fu)

/** \brief  Offset for Ifx_GTM_DPLL_APS_SYNC_Bits.APS_1C2_EXT */
#define IFX_GTM_DPLL_APS_SYNC_APS_1C2_EXT_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_APS_SYNC_Bits.APS_1C2_OLD */
#define IFX_GTM_DPLL_APS_SYNC_APS_1C2_OLD_LEN (6u)

/** \brief  Mask for Ifx_GTM_DPLL_APS_SYNC_Bits.APS_1C2_OLD */
#define IFX_GTM_DPLL_APS_SYNC_APS_1C2_OLD_MSK (0x3fu)

/** \brief  Offset for Ifx_GTM_DPLL_APS_SYNC_Bits.APS_1C2_OLD */
#define IFX_GTM_DPLL_APS_SYNC_APS_1C2_OLD_OFF (14u)

/** \brief  Length for Ifx_GTM_DPLL_APS_SYNC_Bits.APS_1C2_STATUS */
#define IFX_GTM_DPLL_APS_SYNC_APS_1C2_STATUS_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_APS_SYNC_Bits.APS_1C2_STATUS */
#define IFX_GTM_DPLL_APS_SYNC_APS_1C2_STATUS_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_APS_SYNC_Bits.APS_1C2_STATUS */
#define IFX_GTM_DPLL_APS_SYNC_APS_1C2_STATUS_OFF (6u)

/** \brief  Length for Ifx_GTM_DPLL_APS_Bits.WAPS_1C2 */
#define IFX_GTM_DPLL_APS_WAPS_1C2_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_APS_Bits.WAPS_1C2 */
#define IFX_GTM_DPLL_APS_WAPS_1C2_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_APS_Bits.WAPS_1C2 */
#define IFX_GTM_DPLL_APS_WAPS_1C2_OFF (13u)

/** \brief  Length for Ifx_GTM_DPLL_APS_Bits.WAPS */
#define IFX_GTM_DPLL_APS_WAPS_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_APS_Bits.WAPS */
#define IFX_GTM_DPLL_APS_WAPS_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_APS_Bits.WAPS */
#define IFX_GTM_DPLL_APS_WAPS_OFF (1u)

/** \brief  Length for Ifx_GTM_DPLL_APT_2C_Bits.APT_2C */
#define IFX_GTM_DPLL_APT_2C_APT_2C_LEN (10u)

/** \brief  Mask for Ifx_GTM_DPLL_APT_2C_Bits.APT_2C */
#define IFX_GTM_DPLL_APT_2C_APT_2C_MSK (0x3ffu)

/** \brief  Offset for Ifx_GTM_DPLL_APT_2C_Bits.APT_2C */
#define IFX_GTM_DPLL_APT_2C_APT_2C_OFF (2u)

/** \brief  Length for Ifx_GTM_DPLL_APT_Bits.APT_2B */
#define IFX_GTM_DPLL_APT_APT_2B_LEN (10u)

/** \brief  Mask for Ifx_GTM_DPLL_APT_Bits.APT_2B */
#define IFX_GTM_DPLL_APT_APT_2B_MSK (0x3ffu)

/** \brief  Offset for Ifx_GTM_DPLL_APT_Bits.APT_2B */
#define IFX_GTM_DPLL_APT_APT_2B_OFF (14u)

/** \brief  Length for Ifx_GTM_DPLL_APT_Bits.APT */
#define IFX_GTM_DPLL_APT_APT_LEN (10u)

/** \brief  Mask for Ifx_GTM_DPLL_APT_Bits.APT */
#define IFX_GTM_DPLL_APT_APT_MSK (0x3ffu)

/** \brief  Offset for Ifx_GTM_DPLL_APT_Bits.APT */
#define IFX_GTM_DPLL_APT_APT_OFF (2u)

/** \brief  Length for Ifx_GTM_DPLL_APT_SYNC_Bits.APT_2B_EXT */
#define IFX_GTM_DPLL_APT_SYNC_APT_2B_EXT_LEN (6u)

/** \brief  Mask for Ifx_GTM_DPLL_APT_SYNC_Bits.APT_2B_EXT */
#define IFX_GTM_DPLL_APT_SYNC_APT_2B_EXT_MSK (0x3fu)

/** \brief  Offset for Ifx_GTM_DPLL_APT_SYNC_Bits.APT_2B_EXT */
#define IFX_GTM_DPLL_APT_SYNC_APT_2B_EXT_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_APT_SYNC_Bits.APT_2B_OLD */
#define IFX_GTM_DPLL_APT_SYNC_APT_2B_OLD_LEN (10u)

/** \brief  Mask for Ifx_GTM_DPLL_APT_SYNC_Bits.APT_2B_OLD */
#define IFX_GTM_DPLL_APT_SYNC_APT_2B_OLD_MSK (0x3ffu)

/** \brief  Offset for Ifx_GTM_DPLL_APT_SYNC_Bits.APT_2B_OLD */
#define IFX_GTM_DPLL_APT_SYNC_APT_2B_OLD_OFF (14u)

/** \brief  Length for Ifx_GTM_DPLL_APT_SYNC_Bits.APT_2B_STATUS */
#define IFX_GTM_DPLL_APT_SYNC_APT_2B_STATUS_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_APT_SYNC_Bits.APT_2B_STATUS */
#define IFX_GTM_DPLL_APT_SYNC_APT_2B_STATUS_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_APT_SYNC_Bits.APT_2B_STATUS */
#define IFX_GTM_DPLL_APT_SYNC_APT_2B_STATUS_OFF (6u)

/** \brief  Length for Ifx_GTM_DPLL_APT_Bits.WAPT_2B */
#define IFX_GTM_DPLL_APT_WAPT_2B_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_APT_Bits.WAPT_2B */
#define IFX_GTM_DPLL_APT_WAPT_2B_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_APT_Bits.WAPT_2B */
#define IFX_GTM_DPLL_APT_WAPT_2B_OFF (13u)

/** \brief  Length for Ifx_GTM_DPLL_APT_Bits.WAPT */
#define IFX_GTM_DPLL_APT_WAPT_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_APT_Bits.WAPT */
#define IFX_GTM_DPLL_APT_WAPT_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_APT_Bits.WAPT */
#define IFX_GTM_DPLL_APT_WAPT_OFF (1u)

/** \brief  Length for Ifx_GTM_DPLL_CDT_SX_Bits.CDT_SX */
#define IFX_GTM_DPLL_CDT_SX_CDT_SX_LEN (24u)

/** \brief  Mask for Ifx_GTM_DPLL_CDT_SX_Bits.CDT_SX */
#define IFX_GTM_DPLL_CDT_SX_CDT_SX_MSK (0xffffffu)

/** \brief  Offset for Ifx_GTM_DPLL_CDT_SX_Bits.CDT_SX */
#define IFX_GTM_DPLL_CDT_SX_CDT_SX_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_CDT_SX_NOM_Bits.CDT_SX_NOM */
#define IFX_GTM_DPLL_CDT_SX_NOM_CDT_SX_NOM_LEN (24u)

/** \brief  Mask for Ifx_GTM_DPLL_CDT_SX_NOM_Bits.CDT_SX_NOM */
#define IFX_GTM_DPLL_CDT_SX_NOM_CDT_SX_NOM_MSK (0xffffffu)

/** \brief  Offset for Ifx_GTM_DPLL_CDT_SX_NOM_Bits.CDT_SX_NOM */
#define IFX_GTM_DPLL_CDT_SX_NOM_CDT_SX_NOM_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_CDT_TX_Bits.CDT_TX */
#define IFX_GTM_DPLL_CDT_TX_CDT_TX_LEN (24u)

/** \brief  Mask for Ifx_GTM_DPLL_CDT_TX_Bits.CDT_TX */
#define IFX_GTM_DPLL_CDT_TX_CDT_TX_MSK (0xffffffu)

/** \brief  Offset for Ifx_GTM_DPLL_CDT_TX_Bits.CDT_TX */
#define IFX_GTM_DPLL_CDT_TX_CDT_TX_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_CDT_TX_NOM_Bits.CDT_TX_NOM */
#define IFX_GTM_DPLL_CDT_TX_NOM_CDT_TX_NOM_LEN (24u)

/** \brief  Mask for Ifx_GTM_DPLL_CDT_TX_NOM_Bits.CDT_TX_NOM */
#define IFX_GTM_DPLL_CDT_TX_NOM_CDT_TX_NOM_MSK (0xffffffu)

/** \brief  Offset for Ifx_GTM_DPLL_CDT_TX_NOM_Bits.CDT_TX_NOM */
#define IFX_GTM_DPLL_CDT_TX_NOM_CDT_TX_NOM_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_CNT_NUM1_Bits.CNT_NUM_1 */
#define IFX_GTM_DPLL_CNT_NUM1_CNT_NUM_1_LEN (24u)

/** \brief  Mask for Ifx_GTM_DPLL_CNT_NUM1_Bits.CNT_NUM_1 */
#define IFX_GTM_DPLL_CNT_NUM1_CNT_NUM_1_MSK (0xffffffu)

/** \brief  Offset for Ifx_GTM_DPLL_CNT_NUM1_Bits.CNT_NUM_1 */
#define IFX_GTM_DPLL_CNT_NUM1_CNT_NUM_1_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_CNT_NUM2_Bits.CNT_NUM_2 */
#define IFX_GTM_DPLL_CNT_NUM2_CNT_NUM_2_LEN (24u)

/** \brief  Mask for Ifx_GTM_DPLL_CNT_NUM2_Bits.CNT_NUM_2 */
#define IFX_GTM_DPLL_CNT_NUM2_CNT_NUM_2_MSK (0xffffffu)

/** \brief  Offset for Ifx_GTM_DPLL_CNT_NUM2_Bits.CNT_NUM_2 */
#define IFX_GTM_DPLL_CNT_NUM2_CNT_NUM_2_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_CRTL_1_SHADOW_STATE_Bits.COA */
#define IFX_GTM_DPLL_CRTL_1_SHADOW_STATE_COA_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CRTL_1_SHADOW_STATE_Bits.COA */
#define IFX_GTM_DPLL_CRTL_1_SHADOW_STATE_COA_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CRTL_1_SHADOW_STATE_Bits.COA */
#define IFX_GTM_DPLL_CRTL_1_SHADOW_STATE_COA_OFF (3u)

/** \brief  Length for Ifx_GTM_DPLL_CRTL_1_SHADOW_STATE_Bits.DLM1 */
#define IFX_GTM_DPLL_CRTL_1_SHADOW_STATE_DLM1_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CRTL_1_SHADOW_STATE_Bits.DLM1 */
#define IFX_GTM_DPLL_CRTL_1_SHADOW_STATE_DLM1_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CRTL_1_SHADOW_STATE_Bits.DLM1 */
#define IFX_GTM_DPLL_CRTL_1_SHADOW_STATE_DLM1_OFF (6u)

/** \brief  Length for Ifx_GTM_DPLL_CRTL_1_SHADOW_STATE_Bits.DLM2 */
#define IFX_GTM_DPLL_CRTL_1_SHADOW_STATE_DLM2_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CRTL_1_SHADOW_STATE_Bits.DLM2 */
#define IFX_GTM_DPLL_CRTL_1_SHADOW_STATE_DLM2_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CRTL_1_SHADOW_STATE_Bits.DLM2 */
#define IFX_GTM_DPLL_CRTL_1_SHADOW_STATE_DLM2_OFF (9u)

/** \brief  Length for Ifx_GTM_DPLL_CRTL_1_SHADOW_STATE_Bits.DMO */
#define IFX_GTM_DPLL_CRTL_1_SHADOW_STATE_DMO_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CRTL_1_SHADOW_STATE_Bits.DMO */
#define IFX_GTM_DPLL_CRTL_1_SHADOW_STATE_DMO_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CRTL_1_SHADOW_STATE_Bits.DMO */
#define IFX_GTM_DPLL_CRTL_1_SHADOW_STATE_DMO_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_CRTL_1_SHADOW_STATE_Bits.PCM1 */
#define IFX_GTM_DPLL_CRTL_1_SHADOW_STATE_PCM1_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CRTL_1_SHADOW_STATE_Bits.PCM1 */
#define IFX_GTM_DPLL_CRTL_1_SHADOW_STATE_PCM1_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CRTL_1_SHADOW_STATE_Bits.PCM1 */
#define IFX_GTM_DPLL_CRTL_1_SHADOW_STATE_PCM1_OFF (7u)

/** \brief  Length for Ifx_GTM_DPLL_CRTL_1_SHADOW_STATE_Bits.PCM2 */
#define IFX_GTM_DPLL_CRTL_1_SHADOW_STATE_PCM2_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CRTL_1_SHADOW_STATE_Bits.PCM2 */
#define IFX_GTM_DPLL_CRTL_1_SHADOW_STATE_PCM2_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CRTL_1_SHADOW_STATE_Bits.PCM2 */
#define IFX_GTM_DPLL_CRTL_1_SHADOW_STATE_PCM2_OFF (10u)

/** \brief  Length for Ifx_GTM_DPLL_CRTL_1_SHADOW_STATE_Bits.PIT */
#define IFX_GTM_DPLL_CRTL_1_SHADOW_STATE_PIT_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CRTL_1_SHADOW_STATE_Bits.PIT */
#define IFX_GTM_DPLL_CRTL_1_SHADOW_STATE_PIT_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CRTL_1_SHADOW_STATE_Bits.PIT */
#define IFX_GTM_DPLL_CRTL_1_SHADOW_STATE_PIT_OFF (4u)

/** \brief  Length for Ifx_GTM_DPLL_CRTL_1_SHADOW_STATE_Bits.SGE1 */
#define IFX_GTM_DPLL_CRTL_1_SHADOW_STATE_SGE1_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CRTL_1_SHADOW_STATE_Bits.SGE1 */
#define IFX_GTM_DPLL_CRTL_1_SHADOW_STATE_SGE1_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CRTL_1_SHADOW_STATE_Bits.SGE1 */
#define IFX_GTM_DPLL_CRTL_1_SHADOW_STATE_SGE1_OFF (5u)

/** \brief  Length for Ifx_GTM_DPLL_CRTL_1_SHADOW_STATE_Bits.SGE2 */
#define IFX_GTM_DPLL_CRTL_1_SHADOW_STATE_SGE2_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CRTL_1_SHADOW_STATE_Bits.SGE2 */
#define IFX_GTM_DPLL_CRTL_1_SHADOW_STATE_SGE2_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CRTL_1_SHADOW_STATE_Bits.SGE2 */
#define IFX_GTM_DPLL_CRTL_1_SHADOW_STATE_SGE2_OFF (8u)

/** \brief  Length for Ifx_GTM_DPLL_CRTL_1_SHADOW_STATE_Bits.SYN_NS */
#define IFX_GTM_DPLL_CRTL_1_SHADOW_STATE_SYN_NS_LEN (21u)

/** \brief  Mask for Ifx_GTM_DPLL_CRTL_1_SHADOW_STATE_Bits.SYN_NS */
#define IFX_GTM_DPLL_CRTL_1_SHADOW_STATE_SYN_NS_MSK (0x1fffffu)

/** \brief  Offset for Ifx_GTM_DPLL_CRTL_1_SHADOW_STATE_Bits.SYN_NS */
#define IFX_GTM_DPLL_CRTL_1_SHADOW_STATE_SYN_NS_OFF (11u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_0_Bits.AMS */
#define IFX_GTM_DPLL_CTRL_0_AMS_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_0_Bits.AMS */
#define IFX_GTM_DPLL_CTRL_0_AMS_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_0_Bits.AMS */
#define IFX_GTM_DPLL_CTRL_0_AMS_OFF (25u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_0_Bits.AMT */
#define IFX_GTM_DPLL_CTRL_0_AMT_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_0_Bits.AMT */
#define IFX_GTM_DPLL_CTRL_0_AMT_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_0_Bits.AMT */
#define IFX_GTM_DPLL_CTRL_0_AMT_OFF (26u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_0_Bits.IDS */
#define IFX_GTM_DPLL_CTRL_0_IDS_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_0_Bits.IDS */
#define IFX_GTM_DPLL_CTRL_0_IDS_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_0_Bits.IDS */
#define IFX_GTM_DPLL_CTRL_0_IDS_OFF (27u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_0_Bits.IDT */
#define IFX_GTM_DPLL_CTRL_0_IDT_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_0_Bits.IDT */
#define IFX_GTM_DPLL_CTRL_0_IDT_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_0_Bits.IDT */
#define IFX_GTM_DPLL_CTRL_0_IDT_OFF (28u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_0_Bits.IFP */
#define IFX_GTM_DPLL_CTRL_0_IFP_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_0_Bits.IFP */
#define IFX_GTM_DPLL_CTRL_0_IFP_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_0_Bits.IFP */
#define IFX_GTM_DPLL_CTRL_0_IFP_OFF (10u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_0_Bits.MLT */
#define IFX_GTM_DPLL_CTRL_0_MLT_LEN (10u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_0_Bits.MLT */
#define IFX_GTM_DPLL_CTRL_0_MLT_MSK (0x3ffu)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_0_Bits.MLT */
#define IFX_GTM_DPLL_CTRL_0_MLT_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_0_Bits.RMO */
#define IFX_GTM_DPLL_CTRL_0_RMO_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_0_Bits.RMO */
#define IFX_GTM_DPLL_CTRL_0_RMO_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_0_Bits.RMO */
#define IFX_GTM_DPLL_CTRL_0_RMO_OFF (31u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_0_Bits.SEN */
#define IFX_GTM_DPLL_CTRL_0_SEN_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_0_Bits.SEN */
#define IFX_GTM_DPLL_CTRL_0_SEN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_0_Bits.SEN */
#define IFX_GTM_DPLL_CTRL_0_SEN_OFF (29u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_0_SHADOW_STATE_Bits.AMS */
#define IFX_GTM_DPLL_CTRL_0_SHADOW_STATE_AMS_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_0_SHADOW_STATE_Bits.AMS */
#define IFX_GTM_DPLL_CTRL_0_SHADOW_STATE_AMS_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_0_SHADOW_STATE_Bits.AMS */
#define IFX_GTM_DPLL_CTRL_0_SHADOW_STATE_AMS_OFF (25u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_0_SHADOW_STATE_Bits.IDS */
#define IFX_GTM_DPLL_CTRL_0_SHADOW_STATE_IDS_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_0_SHADOW_STATE_Bits.IDS */
#define IFX_GTM_DPLL_CTRL_0_SHADOW_STATE_IDS_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_0_SHADOW_STATE_Bits.IDS */
#define IFX_GTM_DPLL_CTRL_0_SHADOW_STATE_IDS_OFF (27u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_0_SHADOW_STATE_Bits.IFP */
#define IFX_GTM_DPLL_CTRL_0_SHADOW_STATE_IFP_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_0_SHADOW_STATE_Bits.IFP */
#define IFX_GTM_DPLL_CTRL_0_SHADOW_STATE_IFP_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_0_SHADOW_STATE_Bits.IFP */
#define IFX_GTM_DPLL_CTRL_0_SHADOW_STATE_IFP_OFF (10u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_0_SHADOW_STATE_Bits.RMO */
#define IFX_GTM_DPLL_CTRL_0_SHADOW_STATE_RMO_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_0_SHADOW_STATE_Bits.RMO */
#define IFX_GTM_DPLL_CTRL_0_SHADOW_STATE_RMO_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_0_SHADOW_STATE_Bits.RMO */
#define IFX_GTM_DPLL_CTRL_0_SHADOW_STATE_RMO_OFF (31u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_0_SHADOW_TRIGGER_Bits.AMT */
#define IFX_GTM_DPLL_CTRL_0_SHADOW_TRIGGER_AMT_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_0_SHADOW_TRIGGER_Bits.AMT */
#define IFX_GTM_DPLL_CTRL_0_SHADOW_TRIGGER_AMT_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_0_SHADOW_TRIGGER_Bits.AMT */
#define IFX_GTM_DPLL_CTRL_0_SHADOW_TRIGGER_AMT_OFF (26u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_0_SHADOW_TRIGGER_Bits.IDS */
#define IFX_GTM_DPLL_CTRL_0_SHADOW_TRIGGER_IDS_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_0_SHADOW_TRIGGER_Bits.IDS */
#define IFX_GTM_DPLL_CTRL_0_SHADOW_TRIGGER_IDS_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_0_SHADOW_TRIGGER_Bits.IDS */
#define IFX_GTM_DPLL_CTRL_0_SHADOW_TRIGGER_IDS_OFF (27u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_0_SHADOW_TRIGGER_Bits.IDT */
#define IFX_GTM_DPLL_CTRL_0_SHADOW_TRIGGER_IDT_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_0_SHADOW_TRIGGER_Bits.IDT */
#define IFX_GTM_DPLL_CTRL_0_SHADOW_TRIGGER_IDT_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_0_SHADOW_TRIGGER_Bits.IDT */
#define IFX_GTM_DPLL_CTRL_0_SHADOW_TRIGGER_IDT_OFF (28u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_0_SHADOW_TRIGGER_Bits.IFP */
#define IFX_GTM_DPLL_CTRL_0_SHADOW_TRIGGER_IFP_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_0_SHADOW_TRIGGER_Bits.IFP */
#define IFX_GTM_DPLL_CTRL_0_SHADOW_TRIGGER_IFP_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_0_SHADOW_TRIGGER_Bits.IFP */
#define IFX_GTM_DPLL_CTRL_0_SHADOW_TRIGGER_IFP_OFF (10u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_0_SHADOW_TRIGGER_Bits.MLT */
#define IFX_GTM_DPLL_CTRL_0_SHADOW_TRIGGER_MLT_LEN (10u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_0_SHADOW_TRIGGER_Bits.MLT */
#define IFX_GTM_DPLL_CTRL_0_SHADOW_TRIGGER_MLT_MSK (0x3ffu)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_0_SHADOW_TRIGGER_Bits.MLT */
#define IFX_GTM_DPLL_CTRL_0_SHADOW_TRIGGER_MLT_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_0_SHADOW_TRIGGER_Bits.RMO */
#define IFX_GTM_DPLL_CTRL_0_SHADOW_TRIGGER_RMO_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_0_SHADOW_TRIGGER_Bits.RMO */
#define IFX_GTM_DPLL_CTRL_0_SHADOW_TRIGGER_RMO_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_0_SHADOW_TRIGGER_Bits.RMO */
#define IFX_GTM_DPLL_CTRL_0_SHADOW_TRIGGER_RMO_OFF (31u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_0_Bits.SNU */
#define IFX_GTM_DPLL_CTRL_0_SNU_LEN (5u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_0_Bits.SNU */
#define IFX_GTM_DPLL_CTRL_0_SNU_MSK (0x1fu)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_0_Bits.SNU */
#define IFX_GTM_DPLL_CTRL_0_SNU_OFF (11u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_0_Bits.TEN */
#define IFX_GTM_DPLL_CTRL_0_TEN_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_0_Bits.TEN */
#define IFX_GTM_DPLL_CTRL_0_TEN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_0_Bits.TEN */
#define IFX_GTM_DPLL_CTRL_0_TEN_OFF (30u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_0_Bits.TNU */
#define IFX_GTM_DPLL_CTRL_0_TNU_LEN (9u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_0_Bits.TNU */
#define IFX_GTM_DPLL_CTRL_0_TNU_MSK (0x1ffu)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_0_Bits.TNU */
#define IFX_GTM_DPLL_CTRL_0_TNU_OFF (16u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_1_Bits.COA */
#define IFX_GTM_DPLL_CTRL_1_COA_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_1_Bits.COA */
#define IFX_GTM_DPLL_CTRL_1_COA_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_1_Bits.COA */
#define IFX_GTM_DPLL_CTRL_1_COA_OFF (3u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_1_Bits.DEN */
#define IFX_GTM_DPLL_CTRL_1_DEN_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_1_Bits.DEN */
#define IFX_GTM_DPLL_CTRL_1_DEN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_1_Bits.DEN */
#define IFX_GTM_DPLL_CTRL_1_DEN_OFF (1u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_1_Bits.DLM1 */
#define IFX_GTM_DPLL_CTRL_1_DLM1_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_1_Bits.DLM1 */
#define IFX_GTM_DPLL_CTRL_1_DLM1_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_1_Bits.DLM1 */
#define IFX_GTM_DPLL_CTRL_1_DLM1_OFF (6u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_1_Bits.DLM2 */
#define IFX_GTM_DPLL_CTRL_1_DLM2_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_1_Bits.DLM2 */
#define IFX_GTM_DPLL_CTRL_1_DLM2_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_1_Bits.DLM2 */
#define IFX_GTM_DPLL_CTRL_1_DLM2_OFF (9u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_1_Bits.DMO */
#define IFX_GTM_DPLL_CTRL_1_DMO_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_1_Bits.DMO */
#define IFX_GTM_DPLL_CTRL_1_DMO_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_1_Bits.DMO */
#define IFX_GTM_DPLL_CTRL_1_DMO_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_1_Bits.IDDS */
#define IFX_GTM_DPLL_CTRL_1_IDDS_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_1_Bits.IDDS */
#define IFX_GTM_DPLL_CTRL_1_IDDS_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_1_Bits.IDDS */
#define IFX_GTM_DPLL_CTRL_1_IDDS_OFF (2u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_1_Bits.LCD */
#define IFX_GTM_DPLL_CTRL_1_LCD_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_1_Bits.LCD */
#define IFX_GTM_DPLL_CTRL_1_LCD_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_1_Bits.LCD */
#define IFX_GTM_DPLL_CTRL_1_LCD_OFF (22u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_1_Bits.PCM1 */
#define IFX_GTM_DPLL_CTRL_1_PCM1_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_1_Bits.PCM1 */
#define IFX_GTM_DPLL_CTRL_1_PCM1_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_1_Bits.PCM1 */
#define IFX_GTM_DPLL_CTRL_1_PCM1_OFF (7u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_1_Bits.PCM2 */
#define IFX_GTM_DPLL_CTRL_1_PCM2_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_1_Bits.PCM2 */
#define IFX_GTM_DPLL_CTRL_1_PCM2_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_1_Bits.PCM2 */
#define IFX_GTM_DPLL_CTRL_1_PCM2_OFF (10u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_1_Bits.PIT */
#define IFX_GTM_DPLL_CTRL_1_PIT_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_1_Bits.PIT */
#define IFX_GTM_DPLL_CTRL_1_PIT_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_1_Bits.PIT */
#define IFX_GTM_DPLL_CTRL_1_PIT_OFF (4u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_1_Bits.SGE1 */
#define IFX_GTM_DPLL_CTRL_1_SGE1_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_1_Bits.SGE1 */
#define IFX_GTM_DPLL_CTRL_1_SGE1_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_1_Bits.SGE1 */
#define IFX_GTM_DPLL_CTRL_1_SGE1_OFF (5u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_1_Bits.SGE2 */
#define IFX_GTM_DPLL_CTRL_1_SGE2_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_1_Bits.SGE2 */
#define IFX_GTM_DPLL_CTRL_1_SGE2_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_1_Bits.SGE2 */
#define IFX_GTM_DPLL_CTRL_1_SGE2_OFF (8u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_1_SHADOW_TRIGGER_Bits.COA */
#define IFX_GTM_DPLL_CTRL_1_SHADOW_TRIGGER_COA_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_1_SHADOW_TRIGGER_Bits.COA */
#define IFX_GTM_DPLL_CTRL_1_SHADOW_TRIGGER_COA_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_1_SHADOW_TRIGGER_Bits.COA */
#define IFX_GTM_DPLL_CTRL_1_SHADOW_TRIGGER_COA_OFF (3u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_1_SHADOW_TRIGGER_Bits.DLM1 */
#define IFX_GTM_DPLL_CTRL_1_SHADOW_TRIGGER_DLM1_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_1_SHADOW_TRIGGER_Bits.DLM1 */
#define IFX_GTM_DPLL_CTRL_1_SHADOW_TRIGGER_DLM1_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_1_SHADOW_TRIGGER_Bits.DLM1 */
#define IFX_GTM_DPLL_CTRL_1_SHADOW_TRIGGER_DLM1_OFF (6u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_1_SHADOW_TRIGGER_Bits.DMO */
#define IFX_GTM_DPLL_CTRL_1_SHADOW_TRIGGER_DMO_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_1_SHADOW_TRIGGER_Bits.DMO */
#define IFX_GTM_DPLL_CTRL_1_SHADOW_TRIGGER_DMO_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_1_SHADOW_TRIGGER_Bits.DMO */
#define IFX_GTM_DPLL_CTRL_1_SHADOW_TRIGGER_DMO_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_1_SHADOW_TRIGGER_Bits.PCM1 */
#define IFX_GTM_DPLL_CTRL_1_SHADOW_TRIGGER_PCM1_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_1_SHADOW_TRIGGER_Bits.PCM1 */
#define IFX_GTM_DPLL_CTRL_1_SHADOW_TRIGGER_PCM1_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_1_SHADOW_TRIGGER_Bits.PCM1 */
#define IFX_GTM_DPLL_CTRL_1_SHADOW_TRIGGER_PCM1_OFF (7u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_1_SHADOW_TRIGGER_Bits.PIT */
#define IFX_GTM_DPLL_CTRL_1_SHADOW_TRIGGER_PIT_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_1_SHADOW_TRIGGER_Bits.PIT */
#define IFX_GTM_DPLL_CTRL_1_SHADOW_TRIGGER_PIT_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_1_SHADOW_TRIGGER_Bits.PIT */
#define IFX_GTM_DPLL_CTRL_1_SHADOW_TRIGGER_PIT_OFF (4u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_1_SHADOW_TRIGGER_Bits.SGE1 */
#define IFX_GTM_DPLL_CTRL_1_SHADOW_TRIGGER_SGE1_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_1_SHADOW_TRIGGER_Bits.SGE1 */
#define IFX_GTM_DPLL_CTRL_1_SHADOW_TRIGGER_SGE1_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_1_SHADOW_TRIGGER_Bits.SGE1 */
#define IFX_GTM_DPLL_CTRL_1_SHADOW_TRIGGER_SGE1_OFF (5u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_1_Bits.SMC */
#define IFX_GTM_DPLL_CTRL_1_SMC_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_1_Bits.SMC */
#define IFX_GTM_DPLL_CTRL_1_SMC_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_1_Bits.SMC */
#define IFX_GTM_DPLL_CTRL_1_SMC_OFF (27u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_1_Bits.SSL */
#define IFX_GTM_DPLL_CTRL_1_SSL_LEN (2u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_1_Bits.SSL */
#define IFX_GTM_DPLL_CTRL_1_SSL_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_1_Bits.SSL */
#define IFX_GTM_DPLL_CTRL_1_SSL_OFF (28u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_1_Bits.SWR */
#define IFX_GTM_DPLL_CTRL_1_SWR_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_1_Bits.SWR */
#define IFX_GTM_DPLL_CTRL_1_SWR_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_1_Bits.SWR */
#define IFX_GTM_DPLL_CTRL_1_SWR_OFF (23u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_1_Bits.SYN_NS */
#define IFX_GTM_DPLL_CTRL_1_SYN_NS_LEN (5u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_1_Bits.SYN_NS */
#define IFX_GTM_DPLL_CTRL_1_SYN_NS_MSK (0x1fu)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_1_Bits.SYN_NS */
#define IFX_GTM_DPLL_CTRL_1_SYN_NS_OFF (11u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_1_Bits.SYN_NT */
#define IFX_GTM_DPLL_CTRL_1_SYN_NT_LEN (5u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_1_Bits.SYN_NT */
#define IFX_GTM_DPLL_CTRL_1_SYN_NT_MSK (0x1fu)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_1_Bits.SYN_NT */
#define IFX_GTM_DPLL_CTRL_1_SYN_NT_OFF (16u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_1_Bits.SYSF */
#define IFX_GTM_DPLL_CTRL_1_SYSF_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_1_Bits.SYSF */
#define IFX_GTM_DPLL_CTRL_1_SYSF_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_1_Bits.SYSF */
#define IFX_GTM_DPLL_CTRL_1_SYSF_OFF (24u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_1_Bits.TS0_HRS */
#define IFX_GTM_DPLL_CTRL_1_TS0_HRS_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_1_Bits.TS0_HRS */
#define IFX_GTM_DPLL_CTRL_1_TS0_HRS_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_1_Bits.TS0_HRS */
#define IFX_GTM_DPLL_CTRL_1_TS0_HRS_OFF (25u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_1_Bits.TS0_HRT */
#define IFX_GTM_DPLL_CTRL_1_TS0_HRT_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_1_Bits.TS0_HRT */
#define IFX_GTM_DPLL_CTRL_1_TS0_HRT_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_1_Bits.TS0_HRT */
#define IFX_GTM_DPLL_CTRL_1_TS0_HRT_OFF (26u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_1_Bits.TSL */
#define IFX_GTM_DPLL_CTRL_1_TSL_LEN (2u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_1_Bits.TSL */
#define IFX_GTM_DPLL_CTRL_1_TSL_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_1_Bits.TSL */
#define IFX_GTM_DPLL_CTRL_1_TSL_OFF (30u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_2_Bits.AEN0 */
#define IFX_GTM_DPLL_CTRL_2_AEN0_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_2_Bits.AEN0 */
#define IFX_GTM_DPLL_CTRL_2_AEN0_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_2_Bits.AEN0 */
#define IFX_GTM_DPLL_CTRL_2_AEN0_OFF (8u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_2_Bits.AEN1 */
#define IFX_GTM_DPLL_CTRL_2_AEN1_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_2_Bits.AEN1 */
#define IFX_GTM_DPLL_CTRL_2_AEN1_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_2_Bits.AEN1 */
#define IFX_GTM_DPLL_CTRL_2_AEN1_OFF (9u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_2_Bits.AEN2 */
#define IFX_GTM_DPLL_CTRL_2_AEN2_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_2_Bits.AEN2 */
#define IFX_GTM_DPLL_CTRL_2_AEN2_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_2_Bits.AEN2 */
#define IFX_GTM_DPLL_CTRL_2_AEN2_OFF (10u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_2_Bits.AEN3 */
#define IFX_GTM_DPLL_CTRL_2_AEN3_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_2_Bits.AEN3 */
#define IFX_GTM_DPLL_CTRL_2_AEN3_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_2_Bits.AEN3 */
#define IFX_GTM_DPLL_CTRL_2_AEN3_OFF (11u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_2_Bits.AEN4 */
#define IFX_GTM_DPLL_CTRL_2_AEN4_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_2_Bits.AEN4 */
#define IFX_GTM_DPLL_CTRL_2_AEN4_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_2_Bits.AEN4 */
#define IFX_GTM_DPLL_CTRL_2_AEN4_OFF (12u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_2_Bits.AEN5 */
#define IFX_GTM_DPLL_CTRL_2_AEN5_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_2_Bits.AEN5 */
#define IFX_GTM_DPLL_CTRL_2_AEN5_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_2_Bits.AEN5 */
#define IFX_GTM_DPLL_CTRL_2_AEN5_OFF (13u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_2_Bits.AEN6 */
#define IFX_GTM_DPLL_CTRL_2_AEN6_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_2_Bits.AEN6 */
#define IFX_GTM_DPLL_CTRL_2_AEN6_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_2_Bits.AEN6 */
#define IFX_GTM_DPLL_CTRL_2_AEN6_OFF (14u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_2_Bits.AEN7 */
#define IFX_GTM_DPLL_CTRL_2_AEN7_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_2_Bits.AEN7 */
#define IFX_GTM_DPLL_CTRL_2_AEN7_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_2_Bits.AEN7 */
#define IFX_GTM_DPLL_CTRL_2_AEN7_OFF (15u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_2_Bits.WAD0 */
#define IFX_GTM_DPLL_CTRL_2_WAD0_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_2_Bits.WAD0 */
#define IFX_GTM_DPLL_CTRL_2_WAD0_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_2_Bits.WAD0 */
#define IFX_GTM_DPLL_CTRL_2_WAD0_OFF (16u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_2_Bits.WAD1 */
#define IFX_GTM_DPLL_CTRL_2_WAD1_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_2_Bits.WAD1 */
#define IFX_GTM_DPLL_CTRL_2_WAD1_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_2_Bits.WAD1 */
#define IFX_GTM_DPLL_CTRL_2_WAD1_OFF (17u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_2_Bits.WAD2 */
#define IFX_GTM_DPLL_CTRL_2_WAD2_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_2_Bits.WAD2 */
#define IFX_GTM_DPLL_CTRL_2_WAD2_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_2_Bits.WAD2 */
#define IFX_GTM_DPLL_CTRL_2_WAD2_OFF (18u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_2_Bits.WAD3 */
#define IFX_GTM_DPLL_CTRL_2_WAD3_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_2_Bits.WAD3 */
#define IFX_GTM_DPLL_CTRL_2_WAD3_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_2_Bits.WAD3 */
#define IFX_GTM_DPLL_CTRL_2_WAD3_OFF (19u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_2_Bits.WAD4 */
#define IFX_GTM_DPLL_CTRL_2_WAD4_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_2_Bits.WAD4 */
#define IFX_GTM_DPLL_CTRL_2_WAD4_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_2_Bits.WAD4 */
#define IFX_GTM_DPLL_CTRL_2_WAD4_OFF (20u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_2_Bits.WAD5 */
#define IFX_GTM_DPLL_CTRL_2_WAD5_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_2_Bits.WAD5 */
#define IFX_GTM_DPLL_CTRL_2_WAD5_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_2_Bits.WAD5 */
#define IFX_GTM_DPLL_CTRL_2_WAD5_OFF (21u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_2_Bits.WAD6 */
#define IFX_GTM_DPLL_CTRL_2_WAD6_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_2_Bits.WAD6 */
#define IFX_GTM_DPLL_CTRL_2_WAD6_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_2_Bits.WAD6 */
#define IFX_GTM_DPLL_CTRL_2_WAD6_OFF (22u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_2_Bits.WAD7 */
#define IFX_GTM_DPLL_CTRL_2_WAD7_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_2_Bits.WAD7 */
#define IFX_GTM_DPLL_CTRL_2_WAD7_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_2_Bits.WAD7 */
#define IFX_GTM_DPLL_CTRL_2_WAD7_OFF (23u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_3_Bits.AEN10 */
#define IFX_GTM_DPLL_CTRL_3_AEN10_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_3_Bits.AEN10 */
#define IFX_GTM_DPLL_CTRL_3_AEN10_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_3_Bits.AEN10 */
#define IFX_GTM_DPLL_CTRL_3_AEN10_OFF (10u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_3_Bits.AEN11 */
#define IFX_GTM_DPLL_CTRL_3_AEN11_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_3_Bits.AEN11 */
#define IFX_GTM_DPLL_CTRL_3_AEN11_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_3_Bits.AEN11 */
#define IFX_GTM_DPLL_CTRL_3_AEN11_OFF (11u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_3_Bits.AEN12 */
#define IFX_GTM_DPLL_CTRL_3_AEN12_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_3_Bits.AEN12 */
#define IFX_GTM_DPLL_CTRL_3_AEN12_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_3_Bits.AEN12 */
#define IFX_GTM_DPLL_CTRL_3_AEN12_OFF (12u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_3_Bits.AEN13 */
#define IFX_GTM_DPLL_CTRL_3_AEN13_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_3_Bits.AEN13 */
#define IFX_GTM_DPLL_CTRL_3_AEN13_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_3_Bits.AEN13 */
#define IFX_GTM_DPLL_CTRL_3_AEN13_OFF (13u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_3_Bits.AEN14 */
#define IFX_GTM_DPLL_CTRL_3_AEN14_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_3_Bits.AEN14 */
#define IFX_GTM_DPLL_CTRL_3_AEN14_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_3_Bits.AEN14 */
#define IFX_GTM_DPLL_CTRL_3_AEN14_OFF (14u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_3_Bits.AEN15 */
#define IFX_GTM_DPLL_CTRL_3_AEN15_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_3_Bits.AEN15 */
#define IFX_GTM_DPLL_CTRL_3_AEN15_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_3_Bits.AEN15 */
#define IFX_GTM_DPLL_CTRL_3_AEN15_OFF (15u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_3_Bits.AEN8 */
#define IFX_GTM_DPLL_CTRL_3_AEN8_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_3_Bits.AEN8 */
#define IFX_GTM_DPLL_CTRL_3_AEN8_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_3_Bits.AEN8 */
#define IFX_GTM_DPLL_CTRL_3_AEN8_OFF (8u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_3_Bits.AEN9 */
#define IFX_GTM_DPLL_CTRL_3_AEN9_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_3_Bits.AEN9 */
#define IFX_GTM_DPLL_CTRL_3_AEN9_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_3_Bits.AEN9 */
#define IFX_GTM_DPLL_CTRL_3_AEN9_OFF (9u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_3_Bits.WAD10 */
#define IFX_GTM_DPLL_CTRL_3_WAD10_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_3_Bits.WAD10 */
#define IFX_GTM_DPLL_CTRL_3_WAD10_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_3_Bits.WAD10 */
#define IFX_GTM_DPLL_CTRL_3_WAD10_OFF (18u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_3_Bits.WAD11 */
#define IFX_GTM_DPLL_CTRL_3_WAD11_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_3_Bits.WAD11 */
#define IFX_GTM_DPLL_CTRL_3_WAD11_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_3_Bits.WAD11 */
#define IFX_GTM_DPLL_CTRL_3_WAD11_OFF (19u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_3_Bits.WAD12 */
#define IFX_GTM_DPLL_CTRL_3_WAD12_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_3_Bits.WAD12 */
#define IFX_GTM_DPLL_CTRL_3_WAD12_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_3_Bits.WAD12 */
#define IFX_GTM_DPLL_CTRL_3_WAD12_OFF (20u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_3_Bits.WAD13 */
#define IFX_GTM_DPLL_CTRL_3_WAD13_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_3_Bits.WAD13 */
#define IFX_GTM_DPLL_CTRL_3_WAD13_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_3_Bits.WAD13 */
#define IFX_GTM_DPLL_CTRL_3_WAD13_OFF (21u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_3_Bits.WAD14 */
#define IFX_GTM_DPLL_CTRL_3_WAD14_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_3_Bits.WAD14 */
#define IFX_GTM_DPLL_CTRL_3_WAD14_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_3_Bits.WAD14 */
#define IFX_GTM_DPLL_CTRL_3_WAD14_OFF (22u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_3_Bits.WAD15 */
#define IFX_GTM_DPLL_CTRL_3_WAD15_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_3_Bits.WAD15 */
#define IFX_GTM_DPLL_CTRL_3_WAD15_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_3_Bits.WAD15 */
#define IFX_GTM_DPLL_CTRL_3_WAD15_OFF (23u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_3_Bits.WAD8 */
#define IFX_GTM_DPLL_CTRL_3_WAD8_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_3_Bits.WAD8 */
#define IFX_GTM_DPLL_CTRL_3_WAD8_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_3_Bits.WAD8 */
#define IFX_GTM_DPLL_CTRL_3_WAD8_OFF (16u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_3_Bits.WAD9 */
#define IFX_GTM_DPLL_CTRL_3_WAD9_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_3_Bits.WAD9 */
#define IFX_GTM_DPLL_CTRL_3_WAD9_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_3_Bits.WAD9 */
#define IFX_GTM_DPLL_CTRL_3_WAD9_OFF (17u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_4_Bits.AEN16 */
#define IFX_GTM_DPLL_CTRL_4_AEN16_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_4_Bits.AEN16 */
#define IFX_GTM_DPLL_CTRL_4_AEN16_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_4_Bits.AEN16 */
#define IFX_GTM_DPLL_CTRL_4_AEN16_OFF (8u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_4_Bits.AEN17 */
#define IFX_GTM_DPLL_CTRL_4_AEN17_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_4_Bits.AEN17 */
#define IFX_GTM_DPLL_CTRL_4_AEN17_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_4_Bits.AEN17 */
#define IFX_GTM_DPLL_CTRL_4_AEN17_OFF (9u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_4_Bits.AEN18 */
#define IFX_GTM_DPLL_CTRL_4_AEN18_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_4_Bits.AEN18 */
#define IFX_GTM_DPLL_CTRL_4_AEN18_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_4_Bits.AEN18 */
#define IFX_GTM_DPLL_CTRL_4_AEN18_OFF (10u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_4_Bits.AEN19 */
#define IFX_GTM_DPLL_CTRL_4_AEN19_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_4_Bits.AEN19 */
#define IFX_GTM_DPLL_CTRL_4_AEN19_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_4_Bits.AEN19 */
#define IFX_GTM_DPLL_CTRL_4_AEN19_OFF (11u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_4_Bits.AEN20 */
#define IFX_GTM_DPLL_CTRL_4_AEN20_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_4_Bits.AEN20 */
#define IFX_GTM_DPLL_CTRL_4_AEN20_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_4_Bits.AEN20 */
#define IFX_GTM_DPLL_CTRL_4_AEN20_OFF (12u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_4_Bits.AEN21 */
#define IFX_GTM_DPLL_CTRL_4_AEN21_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_4_Bits.AEN21 */
#define IFX_GTM_DPLL_CTRL_4_AEN21_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_4_Bits.AEN21 */
#define IFX_GTM_DPLL_CTRL_4_AEN21_OFF (13u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_4_Bits.AEN22 */
#define IFX_GTM_DPLL_CTRL_4_AEN22_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_4_Bits.AEN22 */
#define IFX_GTM_DPLL_CTRL_4_AEN22_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_4_Bits.AEN22 */
#define IFX_GTM_DPLL_CTRL_4_AEN22_OFF (14u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_4_Bits.AEN23 */
#define IFX_GTM_DPLL_CTRL_4_AEN23_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_4_Bits.AEN23 */
#define IFX_GTM_DPLL_CTRL_4_AEN23_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_4_Bits.AEN23 */
#define IFX_GTM_DPLL_CTRL_4_AEN23_OFF (15u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_4_Bits.WAD16 */
#define IFX_GTM_DPLL_CTRL_4_WAD16_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_4_Bits.WAD16 */
#define IFX_GTM_DPLL_CTRL_4_WAD16_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_4_Bits.WAD16 */
#define IFX_GTM_DPLL_CTRL_4_WAD16_OFF (16u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_4_Bits.WAD17 */
#define IFX_GTM_DPLL_CTRL_4_WAD17_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_4_Bits.WAD17 */
#define IFX_GTM_DPLL_CTRL_4_WAD17_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_4_Bits.WAD17 */
#define IFX_GTM_DPLL_CTRL_4_WAD17_OFF (17u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_4_Bits.WAD18 */
#define IFX_GTM_DPLL_CTRL_4_WAD18_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_4_Bits.WAD18 */
#define IFX_GTM_DPLL_CTRL_4_WAD18_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_4_Bits.WAD18 */
#define IFX_GTM_DPLL_CTRL_4_WAD18_OFF (18u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_4_Bits.WAD19 */
#define IFX_GTM_DPLL_CTRL_4_WAD19_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_4_Bits.WAD19 */
#define IFX_GTM_DPLL_CTRL_4_WAD19_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_4_Bits.WAD19 */
#define IFX_GTM_DPLL_CTRL_4_WAD19_OFF (19u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_4_Bits.WAD20 */
#define IFX_GTM_DPLL_CTRL_4_WAD20_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_4_Bits.WAD20 */
#define IFX_GTM_DPLL_CTRL_4_WAD20_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_4_Bits.WAD20 */
#define IFX_GTM_DPLL_CTRL_4_WAD20_OFF (20u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_4_Bits.WAD21 */
#define IFX_GTM_DPLL_CTRL_4_WAD21_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_4_Bits.WAD21 */
#define IFX_GTM_DPLL_CTRL_4_WAD21_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_4_Bits.WAD21 */
#define IFX_GTM_DPLL_CTRL_4_WAD21_OFF (21u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_4_Bits.WAD22 */
#define IFX_GTM_DPLL_CTRL_4_WAD22_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_4_Bits.WAD22 */
#define IFX_GTM_DPLL_CTRL_4_WAD22_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_4_Bits.WAD22 */
#define IFX_GTM_DPLL_CTRL_4_WAD22_OFF (22u)

/** \brief  Length for Ifx_GTM_DPLL_CTRL_4_Bits.WAD23 */
#define IFX_GTM_DPLL_CTRL_4_WAD23_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_CTRL_4_Bits.WAD23 */
#define IFX_GTM_DPLL_CTRL_4_WAD23_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_CTRL_4_Bits.WAD23 */
#define IFX_GTM_DPLL_CTRL_4_WAD23_OFF (23u)

/** \brief  Length for Ifx_GTM_DPLL_DLA_Bits.DLA */
#define IFX_GTM_DPLL_DLA_DLA_LEN (24u)

/** \brief  Mask for Ifx_GTM_DPLL_DLA_Bits.DLA */
#define IFX_GTM_DPLL_DLA_DLA_MSK (0xffffffu)

/** \brief  Offset for Ifx_GTM_DPLL_DLA_Bits.DLA */
#define IFX_GTM_DPLL_DLA_DLA_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_DT_S_ACT_Bits.DT_S_ACT */
#define IFX_GTM_DPLL_DT_S_ACT_DT_S_ACT_LEN (24u)

/** \brief  Mask for Ifx_GTM_DPLL_DT_S_ACT_Bits.DT_S_ACT */
#define IFX_GTM_DPLL_DT_S_ACT_DT_S_ACT_MSK (0xffffffu)

/** \brief  Offset for Ifx_GTM_DPLL_DT_S_ACT_Bits.DT_S_ACT */
#define IFX_GTM_DPLL_DT_S_ACT_DT_S_ACT_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_DT_S_Bits.DT_S */
#define IFX_GTM_DPLL_DT_S_DT_S_LEN (24u)

/** \brief  Mask for Ifx_GTM_DPLL_DT_S_Bits.DT_S */
#define IFX_GTM_DPLL_DT_S_DT_S_MSK (0xffffffu)

/** \brief  Offset for Ifx_GTM_DPLL_DT_S_Bits.DT_S */
#define IFX_GTM_DPLL_DT_S_DT_S_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_DT_T_ACT_Bits.DT_T_ACT */
#define IFX_GTM_DPLL_DT_T_ACT_DT_T_ACT_LEN (24u)

/** \brief  Mask for Ifx_GTM_DPLL_DT_T_ACT_Bits.DT_T_ACT */
#define IFX_GTM_DPLL_DT_T_ACT_DT_T_ACT_MSK (0xffffffu)

/** \brief  Offset for Ifx_GTM_DPLL_DT_T_ACT_Bits.DT_T_ACT */
#define IFX_GTM_DPLL_DT_T_ACT_DT_T_ACT_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_DTA_Bits.DTA */
#define IFX_GTM_DPLL_DTA_DTA_LEN (24u)

/** \brief  Mask for Ifx_GTM_DPLL_DTA_Bits.DTA */
#define IFX_GTM_DPLL_DTA_DTA_MSK (0xffffffu)

/** \brief  Offset for Ifx_GTM_DPLL_DTA_Bits.DTA */
#define IFX_GTM_DPLL_DTA_DTA_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_EDT_S_Bits.EDT_S */
#define IFX_GTM_DPLL_EDT_S_EDT_S_LEN (24u)

/** \brief  Mask for Ifx_GTM_DPLL_EDT_S_Bits.EDT_S */
#define IFX_GTM_DPLL_EDT_S_EDT_S_MSK (0xffffffu)

/** \brief  Offset for Ifx_GTM_DPLL_EDT_S_Bits.EDT_S */
#define IFX_GTM_DPLL_EDT_S_EDT_S_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_EDT_T_Bits.EDT_T */
#define IFX_GTM_DPLL_EDT_T_EDT_T_LEN (24u)

/** \brief  Mask for Ifx_GTM_DPLL_EDT_T_Bits.EDT_T */
#define IFX_GTM_DPLL_EDT_T_EDT_T_MSK (0xffffffu)

/** \brief  Offset for Ifx_GTM_DPLL_EDT_T_Bits.EDT_T */
#define IFX_GTM_DPLL_EDT_T_EDT_T_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_EIRQ_EN_Bits.CDSI_EIRQ_EN */
#define IFX_GTM_DPLL_EIRQ_EN_CDSI_EIRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_EIRQ_EN_Bits.CDSI_EIRQ_EN */
#define IFX_GTM_DPLL_EIRQ_EN_CDSI_EIRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_EIRQ_EN_Bits.CDSI_EIRQ_EN */
#define IFX_GTM_DPLL_EIRQ_EN_CDSI_EIRQ_EN_OFF (24u)

/** \brief  Length for Ifx_GTM_DPLL_EIRQ_EN_Bits.CDTI_EIRQ_EN */
#define IFX_GTM_DPLL_EIRQ_EN_CDTI_EIRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_EIRQ_EN_Bits.CDTI_EIRQ_EN */
#define IFX_GTM_DPLL_EIRQ_EN_CDTI_EIRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_EIRQ_EN_Bits.CDTI_EIRQ_EN */
#define IFX_GTM_DPLL_EIRQ_EN_CDTI_EIRQ_EN_OFF (23u)

/** \brief  Length for Ifx_GTM_DPLL_EIRQ_EN_Bits.DCGI */
#define IFX_GTM_DPLL_EIRQ_EN_DCGI_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_EIRQ_EN_Bits.DCGI */
#define IFX_GTM_DPLL_EIRQ_EN_DCGI_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_EIRQ_EN_Bits.DCGI */
#define IFX_GTM_DPLL_EIRQ_EN_DCGI_OFF (27u)

/** \brief  Length for Ifx_GTM_DPLL_EIRQ_EN_Bits.EI_EIRQ_EN */
#define IFX_GTM_DPLL_EIRQ_EN_EI_EIRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_EIRQ_EN_Bits.EI_EIRQ_EN */
#define IFX_GTM_DPLL_EIRQ_EN_EI_EIRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_EIRQ_EN_Bits.EI_EIRQ_EN */
#define IFX_GTM_DPLL_EIRQ_EN_EI_EIRQ_EN_OFF (15u)

/** \brief  Length for Ifx_GTM_DPLL_EIRQ_EN_Bits.GL1I_EIRQ_EN */
#define IFX_GTM_DPLL_EIRQ_EN_GL1I_EIRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_EIRQ_EN_Bits.GL1I_EIRQ_EN */
#define IFX_GTM_DPLL_EIRQ_EN_GL1I_EIRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_EIRQ_EN_Bits.GL1I_EIRQ_EN */
#define IFX_GTM_DPLL_EIRQ_EN_GL1I_EIRQ_EN_OFF (13u)

/** \brief  Length for Ifx_GTM_DPLL_EIRQ_EN_Bits.GL2I_EIRQ_EN */
#define IFX_GTM_DPLL_EIRQ_EN_GL2I_EIRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_EIRQ_EN_Bits.GL2I_EIRQ_EN */
#define IFX_GTM_DPLL_EIRQ_EN_GL2I_EIRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_EIRQ_EN_Bits.GL2I_EIRQ_EN */
#define IFX_GTM_DPLL_EIRQ_EN_GL2I_EIRQ_EN_OFF (16u)

/** \brief  Length for Ifx_GTM_DPLL_EIRQ_EN_Bits.LL1I_EIRQ_EN */
#define IFX_GTM_DPLL_EIRQ_EN_LL1I_EIRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_EIRQ_EN_Bits.LL1I_EIRQ_EN */
#define IFX_GTM_DPLL_EIRQ_EN_LL1I_EIRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_EIRQ_EN_Bits.LL1I_EIRQ_EN */
#define IFX_GTM_DPLL_EIRQ_EN_LL1I_EIRQ_EN_OFF (14u)

/** \brief  Length for Ifx_GTM_DPLL_EIRQ_EN_Bits.LL2I_EIRQ_EN */
#define IFX_GTM_DPLL_EIRQ_EN_LL2I_EIRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_EIRQ_EN_Bits.LL2I_EIRQ_EN */
#define IFX_GTM_DPLL_EIRQ_EN_LL2I_EIRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_EIRQ_EN_Bits.LL2I_EIRQ_EN */
#define IFX_GTM_DPLL_EIRQ_EN_LL2I_EIRQ_EN_OFF (17u)

/** \brief  Length for Ifx_GTM_DPLL_EIRQ_EN_Bits.MSI_EIRQ_EN */
#define IFX_GTM_DPLL_EIRQ_EN_MSI_EIRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_EIRQ_EN_Bits.MSI_EIRQ_EN */
#define IFX_GTM_DPLL_EIRQ_EN_MSI_EIRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_EIRQ_EN_Bits.MSI_EIRQ_EN */
#define IFX_GTM_DPLL_EIRQ_EN_MSI_EIRQ_EN_OFF (6u)

/** \brief  Length for Ifx_GTM_DPLL_EIRQ_EN_Bits.MTI_EIRQ_EN */
#define IFX_GTM_DPLL_EIRQ_EN_MTI_EIRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_EIRQ_EN_Bits.MTI_EIRQ_EN */
#define IFX_GTM_DPLL_EIRQ_EN_MTI_EIRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_EIRQ_EN_Bits.MTI_EIRQ_EN */
#define IFX_GTM_DPLL_EIRQ_EN_MTI_EIRQ_EN_OFF (7u)

/** \brief  Length for Ifx_GTM_DPLL_EIRQ_EN_Bits.PDI_EIRQ_EN */
#define IFX_GTM_DPLL_EIRQ_EN_PDI_EIRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_EIRQ_EN_Bits.PDI_EIRQ_EN */
#define IFX_GTM_DPLL_EIRQ_EN_PDI_EIRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_EIRQ_EN_Bits.PDI_EIRQ_EN */
#define IFX_GTM_DPLL_EIRQ_EN_PDI_EIRQ_EN_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_EIRQ_EN_Bits.PEI_EIRQ_EN */
#define IFX_GTM_DPLL_EIRQ_EN_PEI_EIRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_EIRQ_EN_Bits.PEI_EIRQ_EN */
#define IFX_GTM_DPLL_EIRQ_EN_PEI_EIRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_EIRQ_EN_Bits.PEI_EIRQ_EN */
#define IFX_GTM_DPLL_EIRQ_EN_PEI_EIRQ_EN_OFF (1u)

/** \brief  Length for Ifx_GTM_DPLL_EIRQ_EN_Bits.PWI_EIRQ_EN */
#define IFX_GTM_DPLL_EIRQ_EN_PWI_EIRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_EIRQ_EN_Bits.PWI_EIRQ_EN */
#define IFX_GTM_DPLL_EIRQ_EN_PWI_EIRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_EIRQ_EN_Bits.PWI_EIRQ_EN */
#define IFX_GTM_DPLL_EIRQ_EN_PWI_EIRQ_EN_OFF (10u)

/** \brief  Length for Ifx_GTM_DPLL_EIRQ_EN_Bits.SASI_EIRQ_EN */
#define IFX_GTM_DPLL_EIRQ_EN_SASI_EIRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_EIRQ_EN_Bits.SASI_EIRQ_EN */
#define IFX_GTM_DPLL_EIRQ_EN_SASI_EIRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_EIRQ_EN_Bits.SASI_EIRQ_EN */
#define IFX_GTM_DPLL_EIRQ_EN_SASI_EIRQ_EN_OFF (8u)

/** \brief  Length for Ifx_GTM_DPLL_EIRQ_EN_Bits.SISI_EIRQ_EN */
#define IFX_GTM_DPLL_EIRQ_EN_SISI_EIRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_EIRQ_EN_Bits.SISI_EIRQ_EN */
#define IFX_GTM_DPLL_EIRQ_EN_SISI_EIRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_EIRQ_EN_Bits.SISI_EIRQ_EN */
#define IFX_GTM_DPLL_EIRQ_EN_SISI_EIRQ_EN_OFF (4u)

/** \brief  Length for Ifx_GTM_DPLL_EIRQ_EN_Bits.SORI */
#define IFX_GTM_DPLL_EIRQ_EN_SORI_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_EIRQ_EN_Bits.SORI */
#define IFX_GTM_DPLL_EIRQ_EN_SORI_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_EIRQ_EN_Bits.SORI */
#define IFX_GTM_DPLL_EIRQ_EN_SORI_OFF (26u)

/** \brief  Length for Ifx_GTM_DPLL_EIRQ_EN_Bits.TASI_EIRQ_EN */
#define IFX_GTM_DPLL_EIRQ_EN_TASI_EIRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_EIRQ_EN_Bits.TASI_EIRQ_EN */
#define IFX_GTM_DPLL_EIRQ_EN_TASI_EIRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_EIRQ_EN_Bits.TASI_EIRQ_EN */
#define IFX_GTM_DPLL_EIRQ_EN_TASI_EIRQ_EN_OFF (9u)

/** \brief  Length for Ifx_GTM_DPLL_EIRQ_EN_Bits.TAXI_EIRQ_EN */
#define IFX_GTM_DPLL_EIRQ_EN_TAXI_EIRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_EIRQ_EN_Bits.TAXI_EIRQ_EN */
#define IFX_GTM_DPLL_EIRQ_EN_TAXI_EIRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_EIRQ_EN_Bits.TAXI_EIRQ_EN */
#define IFX_GTM_DPLL_EIRQ_EN_TAXI_EIRQ_EN_OFF (3u)

/** \brief  Length for Ifx_GTM_DPLL_EIRQ_EN_Bits.TE0I_EIRQ_EN */
#define IFX_GTM_DPLL_EIRQ_EN_TE0I_EIRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_EIRQ_EN_Bits.TE0I_EIRQ_EN */
#define IFX_GTM_DPLL_EIRQ_EN_TE0I_EIRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_EIRQ_EN_Bits.TE0I_EIRQ_EN */
#define IFX_GTM_DPLL_EIRQ_EN_TE0I_EIRQ_EN_OFF (18u)

/** \brief  Length for Ifx_GTM_DPLL_EIRQ_EN_Bits.TE1I_EIRQ_EN */
#define IFX_GTM_DPLL_EIRQ_EN_TE1I_EIRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_EIRQ_EN_Bits.TE1I_EIRQ_EN */
#define IFX_GTM_DPLL_EIRQ_EN_TE1I_EIRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_EIRQ_EN_Bits.TE1I_EIRQ_EN */
#define IFX_GTM_DPLL_EIRQ_EN_TE1I_EIRQ_EN_OFF (19u)

/** \brief  Length for Ifx_GTM_DPLL_EIRQ_EN_Bits.TE2I_EIRQ_EN */
#define IFX_GTM_DPLL_EIRQ_EN_TE2I_EIRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_EIRQ_EN_Bits.TE2I_EIRQ_EN */
#define IFX_GTM_DPLL_EIRQ_EN_TE2I_EIRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_EIRQ_EN_Bits.TE2I_EIRQ_EN */
#define IFX_GTM_DPLL_EIRQ_EN_TE2I_EIRQ_EN_OFF (20u)

/** \brief  Length for Ifx_GTM_DPLL_EIRQ_EN_Bits.TE3I_EIRQ_EN */
#define IFX_GTM_DPLL_EIRQ_EN_TE3I_EIRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_EIRQ_EN_Bits.TE3I_EIRQ_EN */
#define IFX_GTM_DPLL_EIRQ_EN_TE3I_EIRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_EIRQ_EN_Bits.TE3I_EIRQ_EN */
#define IFX_GTM_DPLL_EIRQ_EN_TE3I_EIRQ_EN_OFF (21u)

/** \brief  Length for Ifx_GTM_DPLL_EIRQ_EN_Bits.TE4I_EIRQ_EN */
#define IFX_GTM_DPLL_EIRQ_EN_TE4I_EIRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_EIRQ_EN_Bits.TE4I_EIRQ_EN */
#define IFX_GTM_DPLL_EIRQ_EN_TE4I_EIRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_EIRQ_EN_Bits.TE4I_EIRQ_EN */
#define IFX_GTM_DPLL_EIRQ_EN_TE4I_EIRQ_EN_OFF (22u)

/** \brief  Length for Ifx_GTM_DPLL_EIRQ_EN_Bits.TINI_EIRQ_EN */
#define IFX_GTM_DPLL_EIRQ_EN_TINI_EIRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_EIRQ_EN_Bits.TINI_EIRQ_EN */
#define IFX_GTM_DPLL_EIRQ_EN_TINI_EIRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_EIRQ_EN_Bits.TINI_EIRQ_EN */
#define IFX_GTM_DPLL_EIRQ_EN_TINI_EIRQ_EN_OFF (2u)

/** \brief  Length for Ifx_GTM_DPLL_EIRQ_EN_Bits.TISI_EIRQ_EN */
#define IFX_GTM_DPLL_EIRQ_EN_TISI_EIRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_EIRQ_EN_Bits.TISI_EIRQ_EN */
#define IFX_GTM_DPLL_EIRQ_EN_TISI_EIRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_EIRQ_EN_Bits.TISI_EIRQ_EN */
#define IFX_GTM_DPLL_EIRQ_EN_TISI_EIRQ_EN_OFF (5u)

/** \brief  Length for Ifx_GTM_DPLL_EIRQ_EN_Bits.TORI */
#define IFX_GTM_DPLL_EIRQ_EN_TORI_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_EIRQ_EN_Bits.TORI */
#define IFX_GTM_DPLL_EIRQ_EN_TORI_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_EIRQ_EN_Bits.TORI */
#define IFX_GTM_DPLL_EIRQ_EN_TORI_OFF (25u)

/** \brief  Length for Ifx_GTM_DPLL_EIRQ_EN_Bits.W1I_EIRQ_EN */
#define IFX_GTM_DPLL_EIRQ_EN_W1I_EIRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_EIRQ_EN_Bits.W1I_EIRQ_EN */
#define IFX_GTM_DPLL_EIRQ_EN_W1I_EIRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_EIRQ_EN_Bits.W1I_EIRQ_EN */
#define IFX_GTM_DPLL_EIRQ_EN_W1I_EIRQ_EN_OFF (12u)

/** \brief  Length for Ifx_GTM_DPLL_EIRQ_EN_Bits.W2I_EIRQ_EN */
#define IFX_GTM_DPLL_EIRQ_EN_W2I_EIRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_EIRQ_EN_Bits.W2I_EIRQ_EN */
#define IFX_GTM_DPLL_EIRQ_EN_W2I_EIRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_EIRQ_EN_Bits.W2I_EIRQ_EN */
#define IFX_GTM_DPLL_EIRQ_EN_W2I_EIRQ_EN_OFF (11u)

/** \brief  Length for Ifx_GTM_DPLL_FTV_S_Bits.STATE_FT */
#define IFX_GTM_DPLL_FTV_S_STATE_FT_LEN (24u)

/** \brief  Mask for Ifx_GTM_DPLL_FTV_S_Bits.STATE_FT */
#define IFX_GTM_DPLL_FTV_S_STATE_FT_MSK (0xffffffu)

/** \brief  Offset for Ifx_GTM_DPLL_FTV_S_Bits.STATE_FT */
#define IFX_GTM_DPLL_FTV_S_STATE_FT_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_FTV_T_Bits.TRIGGER_FT */
#define IFX_GTM_DPLL_FTV_T_TRIGGER_FT_LEN (24u)

/** \brief  Mask for Ifx_GTM_DPLL_FTV_T_Bits.TRIGGER_FT */
#define IFX_GTM_DPLL_FTV_T_TRIGGER_FT_MSK (0xffffffu)

/** \brief  Offset for Ifx_GTM_DPLL_FTV_T_Bits.TRIGGER_FT */
#define IFX_GTM_DPLL_FTV_T_TRIGGER_FT_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_ID_PMTR_Bits.ID_PMTR_x */
#define IFX_GTM_DPLL_ID_PMTR_ID_PMTR_X_LEN (9u)

/** \brief  Mask for Ifx_GTM_DPLL_ID_PMTR_Bits.ID_PMTR_x */
#define IFX_GTM_DPLL_ID_PMTR_ID_PMTR_X_MSK (0x1ffu)

/** \brief  Offset for Ifx_GTM_DPLL_ID_PMTR_Bits.ID_PMTR_x */
#define IFX_GTM_DPLL_ID_PMTR_ID_PMTR_X_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_INC_CNT1_Bits.INC_CNT1 */
#define IFX_GTM_DPLL_INC_CNT1_INC_CNT1_LEN (24u)

/** \brief  Mask for Ifx_GTM_DPLL_INC_CNT1_Bits.INC_CNT1 */
#define IFX_GTM_DPLL_INC_CNT1_INC_CNT1_MSK (0xffffffu)

/** \brief  Offset for Ifx_GTM_DPLL_INC_CNT1_Bits.INC_CNT1 */
#define IFX_GTM_DPLL_INC_CNT1_INC_CNT1_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_INC_CNT2_Bits.INC_CNT2 */
#define IFX_GTM_DPLL_INC_CNT2_INC_CNT2_LEN (24u)

/** \brief  Mask for Ifx_GTM_DPLL_INC_CNT2_Bits.INC_CNT2 */
#define IFX_GTM_DPLL_INC_CNT2_INC_CNT2_MSK (0xffffffu)

/** \brief  Offset for Ifx_GTM_DPLL_INC_CNT2_Bits.INC_CNT2 */
#define IFX_GTM_DPLL_INC_CNT2_INC_CNT2_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_EN_Bits.CDSI_IRQ_EN */
#define IFX_GTM_DPLL_IRQ_EN_CDSI_IRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_EN_Bits.CDSI_IRQ_EN */
#define IFX_GTM_DPLL_IRQ_EN_CDSI_IRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_EN_Bits.CDSI_IRQ_EN */
#define IFX_GTM_DPLL_IRQ_EN_CDSI_IRQ_EN_OFF (24u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_EN_Bits.CDTI_IRQ_EN */
#define IFX_GTM_DPLL_IRQ_EN_CDTI_IRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_EN_Bits.CDTI_IRQ_EN */
#define IFX_GTM_DPLL_IRQ_EN_CDTI_IRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_EN_Bits.CDTI_IRQ_EN */
#define IFX_GTM_DPLL_IRQ_EN_CDTI_IRQ_EN_OFF (23u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_EN_Bits.DCGI */
#define IFX_GTM_DPLL_IRQ_EN_DCGI_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_EN_Bits.DCGI */
#define IFX_GTM_DPLL_IRQ_EN_DCGI_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_EN_Bits.DCGI */
#define IFX_GTM_DPLL_IRQ_EN_DCGI_OFF (27u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_EN_Bits.EI_IRQ_EN */
#define IFX_GTM_DPLL_IRQ_EN_EI_IRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_EN_Bits.EI_IRQ_EN */
#define IFX_GTM_DPLL_IRQ_EN_EI_IRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_EN_Bits.EI_IRQ_EN */
#define IFX_GTM_DPLL_IRQ_EN_EI_IRQ_EN_OFF (15u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_EN_Bits.GL1I_IRQ_EN */
#define IFX_GTM_DPLL_IRQ_EN_GL1I_IRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_EN_Bits.GL1I_IRQ_EN */
#define IFX_GTM_DPLL_IRQ_EN_GL1I_IRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_EN_Bits.GL1I_IRQ_EN */
#define IFX_GTM_DPLL_IRQ_EN_GL1I_IRQ_EN_OFF (13u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_EN_Bits.GL2I_IRQ_EN */
#define IFX_GTM_DPLL_IRQ_EN_GL2I_IRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_EN_Bits.GL2I_IRQ_EN */
#define IFX_GTM_DPLL_IRQ_EN_GL2I_IRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_EN_Bits.GL2I_IRQ_EN */
#define IFX_GTM_DPLL_IRQ_EN_GL2I_IRQ_EN_OFF (16u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_EN_Bits.LL1I_IRQ_EN */
#define IFX_GTM_DPLL_IRQ_EN_LL1I_IRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_EN_Bits.LL1I_IRQ_EN */
#define IFX_GTM_DPLL_IRQ_EN_LL1I_IRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_EN_Bits.LL1I_IRQ_EN */
#define IFX_GTM_DPLL_IRQ_EN_LL1I_IRQ_EN_OFF (14u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_EN_Bits.LL2I_IRQ_EN */
#define IFX_GTM_DPLL_IRQ_EN_LL2I_IRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_EN_Bits.LL2I_IRQ_EN */
#define IFX_GTM_DPLL_IRQ_EN_LL2I_IRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_EN_Bits.LL2I_IRQ_EN */
#define IFX_GTM_DPLL_IRQ_EN_LL2I_IRQ_EN_OFF (17u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_EN_Bits.MSI_IRQ_EN */
#define IFX_GTM_DPLL_IRQ_EN_MSI_IRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_EN_Bits.MSI_IRQ_EN */
#define IFX_GTM_DPLL_IRQ_EN_MSI_IRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_EN_Bits.MSI_IRQ_EN */
#define IFX_GTM_DPLL_IRQ_EN_MSI_IRQ_EN_OFF (6u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_EN_Bits.MTI_IRQ_EN */
#define IFX_GTM_DPLL_IRQ_EN_MTI_IRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_EN_Bits.MTI_IRQ_EN */
#define IFX_GTM_DPLL_IRQ_EN_MTI_IRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_EN_Bits.MTI_IRQ_EN */
#define IFX_GTM_DPLL_IRQ_EN_MTI_IRQ_EN_OFF (7u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_EN_Bits.PDI_IRQ_EN */
#define IFX_GTM_DPLL_IRQ_EN_PDI_IRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_EN_Bits.PDI_IRQ_EN */
#define IFX_GTM_DPLL_IRQ_EN_PDI_IRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_EN_Bits.PDI_IRQ_EN */
#define IFX_GTM_DPLL_IRQ_EN_PDI_IRQ_EN_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_EN_Bits.PEI_IRQ_EN */
#define IFX_GTM_DPLL_IRQ_EN_PEI_IRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_EN_Bits.PEI_IRQ_EN */
#define IFX_GTM_DPLL_IRQ_EN_PEI_IRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_EN_Bits.PEI_IRQ_EN */
#define IFX_GTM_DPLL_IRQ_EN_PEI_IRQ_EN_OFF (1u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_EN_Bits.PWI_IRQ_EN */
#define IFX_GTM_DPLL_IRQ_EN_PWI_IRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_EN_Bits.PWI_IRQ_EN */
#define IFX_GTM_DPLL_IRQ_EN_PWI_IRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_EN_Bits.PWI_IRQ_EN */
#define IFX_GTM_DPLL_IRQ_EN_PWI_IRQ_EN_OFF (10u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_EN_Bits.SASI_IRQ_EN */
#define IFX_GTM_DPLL_IRQ_EN_SASI_IRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_EN_Bits.SASI_IRQ_EN */
#define IFX_GTM_DPLL_IRQ_EN_SASI_IRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_EN_Bits.SASI_IRQ_EN */
#define IFX_GTM_DPLL_IRQ_EN_SASI_IRQ_EN_OFF (8u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_EN_Bits.SISI_IRQ_EN */
#define IFX_GTM_DPLL_IRQ_EN_SISI_IRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_EN_Bits.SISI_IRQ_EN */
#define IFX_GTM_DPLL_IRQ_EN_SISI_IRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_EN_Bits.SISI_IRQ_EN */
#define IFX_GTM_DPLL_IRQ_EN_SISI_IRQ_EN_OFF (4u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_EN_Bits.SORI */
#define IFX_GTM_DPLL_IRQ_EN_SORI_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_EN_Bits.SORI */
#define IFX_GTM_DPLL_IRQ_EN_SORI_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_EN_Bits.SORI */
#define IFX_GTM_DPLL_IRQ_EN_SORI_OFF (26u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_EN_Bits.TASI_IRQ_EN */
#define IFX_GTM_DPLL_IRQ_EN_TASI_IRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_EN_Bits.TASI_IRQ_EN */
#define IFX_GTM_DPLL_IRQ_EN_TASI_IRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_EN_Bits.TASI_IRQ_EN */
#define IFX_GTM_DPLL_IRQ_EN_TASI_IRQ_EN_OFF (9u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_EN_Bits.TAXI_IRQ_EN */
#define IFX_GTM_DPLL_IRQ_EN_TAXI_IRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_EN_Bits.TAXI_IRQ_EN */
#define IFX_GTM_DPLL_IRQ_EN_TAXI_IRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_EN_Bits.TAXI_IRQ_EN */
#define IFX_GTM_DPLL_IRQ_EN_TAXI_IRQ_EN_OFF (3u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_EN_Bits.TE0I_IRQ_EN */
#define IFX_GTM_DPLL_IRQ_EN_TE0I_IRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_EN_Bits.TE0I_IRQ_EN */
#define IFX_GTM_DPLL_IRQ_EN_TE0I_IRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_EN_Bits.TE0I_IRQ_EN */
#define IFX_GTM_DPLL_IRQ_EN_TE0I_IRQ_EN_OFF (18u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_EN_Bits.TE1I_IRQ_EN */
#define IFX_GTM_DPLL_IRQ_EN_TE1I_IRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_EN_Bits.TE1I_IRQ_EN */
#define IFX_GTM_DPLL_IRQ_EN_TE1I_IRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_EN_Bits.TE1I_IRQ_EN */
#define IFX_GTM_DPLL_IRQ_EN_TE1I_IRQ_EN_OFF (19u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_EN_Bits.TE2I_IRQ_EN */
#define IFX_GTM_DPLL_IRQ_EN_TE2I_IRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_EN_Bits.TE2I_IRQ_EN */
#define IFX_GTM_DPLL_IRQ_EN_TE2I_IRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_EN_Bits.TE2I_IRQ_EN */
#define IFX_GTM_DPLL_IRQ_EN_TE2I_IRQ_EN_OFF (20u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_EN_Bits.TE3I_IRQ_EN */
#define IFX_GTM_DPLL_IRQ_EN_TE3I_IRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_EN_Bits.TE3I_IRQ_EN */
#define IFX_GTM_DPLL_IRQ_EN_TE3I_IRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_EN_Bits.TE3I_IRQ_EN */
#define IFX_GTM_DPLL_IRQ_EN_TE3I_IRQ_EN_OFF (21u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_EN_Bits.TE4I_IRQ_EN */
#define IFX_GTM_DPLL_IRQ_EN_TE4I_IRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_EN_Bits.TE4I_IRQ_EN */
#define IFX_GTM_DPLL_IRQ_EN_TE4I_IRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_EN_Bits.TE4I_IRQ_EN */
#define IFX_GTM_DPLL_IRQ_EN_TE4I_IRQ_EN_OFF (22u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_EN_Bits.TINI_IRQ_EN */
#define IFX_GTM_DPLL_IRQ_EN_TINI_IRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_EN_Bits.TINI_IRQ_EN */
#define IFX_GTM_DPLL_IRQ_EN_TINI_IRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_EN_Bits.TINI_IRQ_EN */
#define IFX_GTM_DPLL_IRQ_EN_TINI_IRQ_EN_OFF (2u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_EN_Bits.TISI_IRQ_EN */
#define IFX_GTM_DPLL_IRQ_EN_TISI_IRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_EN_Bits.TISI_IRQ_EN */
#define IFX_GTM_DPLL_IRQ_EN_TISI_IRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_EN_Bits.TISI_IRQ_EN */
#define IFX_GTM_DPLL_IRQ_EN_TISI_IRQ_EN_OFF (5u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_EN_Bits.TORI */
#define IFX_GTM_DPLL_IRQ_EN_TORI_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_EN_Bits.TORI */
#define IFX_GTM_DPLL_IRQ_EN_TORI_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_EN_Bits.TORI */
#define IFX_GTM_DPLL_IRQ_EN_TORI_OFF (25u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_EN_Bits.W1I_IRQ_EN */
#define IFX_GTM_DPLL_IRQ_EN_W1I_IRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_EN_Bits.W1I_IRQ_EN */
#define IFX_GTM_DPLL_IRQ_EN_W1I_IRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_EN_Bits.W1I_IRQ_EN */
#define IFX_GTM_DPLL_IRQ_EN_W1I_IRQ_EN_OFF (12u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_EN_Bits.W2I_IRQ_EN */
#define IFX_GTM_DPLL_IRQ_EN_W2I_IRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_EN_Bits.W2I_IRQ_EN */
#define IFX_GTM_DPLL_IRQ_EN_W2I_IRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_EN_Bits.W2I_IRQ_EN */
#define IFX_GTM_DPLL_IRQ_EN_W2I_IRQ_EN_OFF (11u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_CDSI */
#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_CDSI_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_CDSI */
#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_CDSI_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_CDSI */
#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_CDSI_OFF (24u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_CDTI */
#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_CDTI_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_CDTI */
#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_CDTI_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_CDTI */
#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_CDTI_OFF (23u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_DCGI */
#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_DCGI_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_DCGI */
#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_DCGI_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_DCGI */
#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_DCGI_OFF (27u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_EI */
#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_EI_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_EI */
#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_EI_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_EI */
#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_EI_OFF (15u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_GL1I */
#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_GL1I_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_GL1I */
#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_GL1I_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_GL1I */
#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_GL1I_OFF (13u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_GL2I */
#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_GL2I_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_GL2I */
#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_GL2I_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_GL2I */
#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_GL2I_OFF (16u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_LL1I */
#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_LL1I_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_LL1I */
#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_LL1I_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_LL1I */
#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_LL1I_OFF (14u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_LL2I */
#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_LL2I_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_LL2I */
#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_LL2I_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_LL2I */
#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_LL2I_OFF (17u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_MSI */
#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_MSI_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_MSI */
#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_MSI_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_MSI */
#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_MSI_OFF (6u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_MTI */
#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_MTI_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_MTI */
#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_MTI_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_MTI */
#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_MTI_OFF (7u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_PDI */
#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_PDI_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_PDI */
#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_PDI_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_PDI */
#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_PDI_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_PEI */
#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_PEI_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_PEI */
#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_PEI_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_PEI */
#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_PEI_OFF (1u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_PWI */
#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_PWI_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_PWI */
#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_PWI_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_PWI */
#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_PWI_OFF (10u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_SASI */
#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_SASI_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_SASI */
#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_SASI_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_SASI */
#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_SASI_OFF (8u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_SISI */
#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_SISI_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_SISI */
#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_SISI_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_SISI */
#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_SISI_OFF (4u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_SORI */
#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_SORI_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_SORI */
#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_SORI_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_SORI */
#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_SORI_OFF (26u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_TASI */
#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_TASI_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_TASI */
#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_TASI_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_TASI */
#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_TASI_OFF (9u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_TAXI */
#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_TAXI_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_TAXI */
#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_TAXI_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_TAXI */
#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_TAXI_OFF (3u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_TE0I */
#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_TE0I_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_TE0I */
#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_TE0I_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_TE0I */
#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_TE0I_OFF (18u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_TE1I */
#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_TE1I_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_TE1I */
#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_TE1I_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_TE1I */
#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_TE1I_OFF (19u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_TE2I */
#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_TE2I_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_TE2I */
#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_TE2I_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_TE2I */
#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_TE2I_OFF (20u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_TE3I */
#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_TE3I_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_TE3I */
#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_TE3I_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_TE3I */
#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_TE3I_OFF (21u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_TE4I */
#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_TE4I_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_TE4I */
#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_TE4I_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_TE4I */
#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_TE4I_OFF (22u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_TINI */
#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_TINI_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_TINI */
#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_TINI_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_TINI */
#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_TINI_OFF (2u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_TISI */
#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_TISI_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_TISI */
#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_TISI_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_TISI */
#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_TISI_OFF (5u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_TORI */
#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_TORI_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_TORI */
#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_TORI_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_TORI */
#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_TORI_OFF (25u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_W1I */
#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_W1I_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_W1I */
#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_W1I_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_W1I */
#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_W1I_OFF (12u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_W2I */
#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_W2I_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_W2I */
#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_W2I_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_FORCINT_Bits.TRG_W2I */
#define IFX_GTM_DPLL_IRQ_FORCINT_TRG_W2I_OFF (11u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_MODE_Bits.IRQ_MODE */
#define IFX_GTM_DPLL_IRQ_MODE_IRQ_MODE_LEN (2u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_MODE_Bits.IRQ_MODE */
#define IFX_GTM_DPLL_IRQ_MODE_IRQ_MODE_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_MODE_Bits.IRQ_MODE */
#define IFX_GTM_DPLL_IRQ_MODE_IRQ_MODE_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.CDSI */
#define IFX_GTM_DPLL_IRQ_NOTIFY_CDSI_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.CDSI */
#define IFX_GTM_DPLL_IRQ_NOTIFY_CDSI_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.CDSI */
#define IFX_GTM_DPLL_IRQ_NOTIFY_CDSI_OFF (24u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.CDTI */
#define IFX_GTM_DPLL_IRQ_NOTIFY_CDTI_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.CDTI */
#define IFX_GTM_DPLL_IRQ_NOTIFY_CDTI_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.CDTI */
#define IFX_GTM_DPLL_IRQ_NOTIFY_CDTI_OFF (23u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.DCGI */
#define IFX_GTM_DPLL_IRQ_NOTIFY_DCGI_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.DCGI */
#define IFX_GTM_DPLL_IRQ_NOTIFY_DCGI_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.DCGI */
#define IFX_GTM_DPLL_IRQ_NOTIFY_DCGI_OFF (27u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.EI */
#define IFX_GTM_DPLL_IRQ_NOTIFY_EI_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.EI */
#define IFX_GTM_DPLL_IRQ_NOTIFY_EI_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.EI */
#define IFX_GTM_DPLL_IRQ_NOTIFY_EI_OFF (15u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.GL1I */
#define IFX_GTM_DPLL_IRQ_NOTIFY_GL1I_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.GL1I */
#define IFX_GTM_DPLL_IRQ_NOTIFY_GL1I_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.GL1I */
#define IFX_GTM_DPLL_IRQ_NOTIFY_GL1I_OFF (13u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.GL2I */
#define IFX_GTM_DPLL_IRQ_NOTIFY_GL2I_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.GL2I */
#define IFX_GTM_DPLL_IRQ_NOTIFY_GL2I_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.GL2I */
#define IFX_GTM_DPLL_IRQ_NOTIFY_GL2I_OFF (16u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.LL1I */
#define IFX_GTM_DPLL_IRQ_NOTIFY_LL1I_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.LL1I */
#define IFX_GTM_DPLL_IRQ_NOTIFY_LL1I_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.LL1I */
#define IFX_GTM_DPLL_IRQ_NOTIFY_LL1I_OFF (14u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.LL2I */
#define IFX_GTM_DPLL_IRQ_NOTIFY_LL2I_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.LL2I */
#define IFX_GTM_DPLL_IRQ_NOTIFY_LL2I_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.LL2I */
#define IFX_GTM_DPLL_IRQ_NOTIFY_LL2I_OFF (17u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.MSI */
#define IFX_GTM_DPLL_IRQ_NOTIFY_MSI_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.MSI */
#define IFX_GTM_DPLL_IRQ_NOTIFY_MSI_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.MSI */
#define IFX_GTM_DPLL_IRQ_NOTIFY_MSI_OFF (6u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.MTI */
#define IFX_GTM_DPLL_IRQ_NOTIFY_MTI_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.MTI */
#define IFX_GTM_DPLL_IRQ_NOTIFY_MTI_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.MTI */
#define IFX_GTM_DPLL_IRQ_NOTIFY_MTI_OFF (7u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.PDI */
#define IFX_GTM_DPLL_IRQ_NOTIFY_PDI_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.PDI */
#define IFX_GTM_DPLL_IRQ_NOTIFY_PDI_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.PDI */
#define IFX_GTM_DPLL_IRQ_NOTIFY_PDI_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.PEI */
#define IFX_GTM_DPLL_IRQ_NOTIFY_PEI_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.PEI */
#define IFX_GTM_DPLL_IRQ_NOTIFY_PEI_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.PEI */
#define IFX_GTM_DPLL_IRQ_NOTIFY_PEI_OFF (1u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.PWI */
#define IFX_GTM_DPLL_IRQ_NOTIFY_PWI_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.PWI */
#define IFX_GTM_DPLL_IRQ_NOTIFY_PWI_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.PWI */
#define IFX_GTM_DPLL_IRQ_NOTIFY_PWI_OFF (10u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.SASI */
#define IFX_GTM_DPLL_IRQ_NOTIFY_SASI_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.SASI */
#define IFX_GTM_DPLL_IRQ_NOTIFY_SASI_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.SASI */
#define IFX_GTM_DPLL_IRQ_NOTIFY_SASI_OFF (8u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.SISI */
#define IFX_GTM_DPLL_IRQ_NOTIFY_SISI_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.SISI */
#define IFX_GTM_DPLL_IRQ_NOTIFY_SISI_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.SISI */
#define IFX_GTM_DPLL_IRQ_NOTIFY_SISI_OFF (4u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.SORI */
#define IFX_GTM_DPLL_IRQ_NOTIFY_SORI_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.SORI */
#define IFX_GTM_DPLL_IRQ_NOTIFY_SORI_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.SORI */
#define IFX_GTM_DPLL_IRQ_NOTIFY_SORI_OFF (26u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.TASI */
#define IFX_GTM_DPLL_IRQ_NOTIFY_TASI_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.TASI */
#define IFX_GTM_DPLL_IRQ_NOTIFY_TASI_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.TASI */
#define IFX_GTM_DPLL_IRQ_NOTIFY_TASI_OFF (9u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.TAXI */
#define IFX_GTM_DPLL_IRQ_NOTIFY_TAXI_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.TAXI */
#define IFX_GTM_DPLL_IRQ_NOTIFY_TAXI_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.TAXI */
#define IFX_GTM_DPLL_IRQ_NOTIFY_TAXI_OFF (3u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.TE0I */
#define IFX_GTM_DPLL_IRQ_NOTIFY_TE0I_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.TE0I */
#define IFX_GTM_DPLL_IRQ_NOTIFY_TE0I_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.TE0I */
#define IFX_GTM_DPLL_IRQ_NOTIFY_TE0I_OFF (18u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.TE1I */
#define IFX_GTM_DPLL_IRQ_NOTIFY_TE1I_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.TE1I */
#define IFX_GTM_DPLL_IRQ_NOTIFY_TE1I_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.TE1I */
#define IFX_GTM_DPLL_IRQ_NOTIFY_TE1I_OFF (19u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.TE2I */
#define IFX_GTM_DPLL_IRQ_NOTIFY_TE2I_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.TE2I */
#define IFX_GTM_DPLL_IRQ_NOTIFY_TE2I_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.TE2I */
#define IFX_GTM_DPLL_IRQ_NOTIFY_TE2I_OFF (20u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.TE3I */
#define IFX_GTM_DPLL_IRQ_NOTIFY_TE3I_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.TE3I */
#define IFX_GTM_DPLL_IRQ_NOTIFY_TE3I_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.TE3I */
#define IFX_GTM_DPLL_IRQ_NOTIFY_TE3I_OFF (21u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.TE4I */
#define IFX_GTM_DPLL_IRQ_NOTIFY_TE4I_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.TE4I */
#define IFX_GTM_DPLL_IRQ_NOTIFY_TE4I_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.TE4I */
#define IFX_GTM_DPLL_IRQ_NOTIFY_TE4I_OFF (22u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.TINI */
#define IFX_GTM_DPLL_IRQ_NOTIFY_TINI_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.TINI */
#define IFX_GTM_DPLL_IRQ_NOTIFY_TINI_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.TINI */
#define IFX_GTM_DPLL_IRQ_NOTIFY_TINI_OFF (2u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.TISI */
#define IFX_GTM_DPLL_IRQ_NOTIFY_TISI_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.TISI */
#define IFX_GTM_DPLL_IRQ_NOTIFY_TISI_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.TISI */
#define IFX_GTM_DPLL_IRQ_NOTIFY_TISI_OFF (5u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.TORI */
#define IFX_GTM_DPLL_IRQ_NOTIFY_TORI_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.TORI */
#define IFX_GTM_DPLL_IRQ_NOTIFY_TORI_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.TORI */
#define IFX_GTM_DPLL_IRQ_NOTIFY_TORI_OFF (25u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.W1I */
#define IFX_GTM_DPLL_IRQ_NOTIFY_W1I_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.W1I */
#define IFX_GTM_DPLL_IRQ_NOTIFY_W1I_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.W1I */
#define IFX_GTM_DPLL_IRQ_NOTIFY_W1I_OFF (12u)

/** \brief  Length for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.W2I */
#define IFX_GTM_DPLL_IRQ_NOTIFY_W2I_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.W2I */
#define IFX_GTM_DPLL_IRQ_NOTIFY_W2I_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_IRQ_NOTIFY_Bits.W2I */
#define IFX_GTM_DPLL_IRQ_NOTIFY_W2I_OFF (11u)

/** \brief  Length for Ifx_GTM_DPLL_MEDT_S_Bits.MEDT_S */
#define IFX_GTM_DPLL_MEDT_S_MEDT_S_LEN (24u)

/** \brief  Mask for Ifx_GTM_DPLL_MEDT_S_Bits.MEDT_S */
#define IFX_GTM_DPLL_MEDT_S_MEDT_S_MSK (0xffffffu)

/** \brief  Offset for Ifx_GTM_DPLL_MEDT_S_Bits.MEDT_S */
#define IFX_GTM_DPLL_MEDT_S_MEDT_S_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_MEDT_T_Bits.MEDT_T */
#define IFX_GTM_DPLL_MEDT_T_MEDT_T_LEN (24u)

/** \brief  Mask for Ifx_GTM_DPLL_MEDT_T_Bits.MEDT_T */
#define IFX_GTM_DPLL_MEDT_T_MEDT_T_MSK (0xffffffu)

/** \brief  Offset for Ifx_GTM_DPLL_MEDT_T_Bits.MEDT_T */
#define IFX_GTM_DPLL_MEDT_T_MEDT_T_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_MLS1_Bits.MLS1 */
#define IFX_GTM_DPLL_MLS1_MLS1_LEN (18u)

/** \brief  Mask for Ifx_GTM_DPLL_MLS1_Bits.MLS1 */
#define IFX_GTM_DPLL_MLS1_MLS1_MSK (0x3ffffu)

/** \brief  Offset for Ifx_GTM_DPLL_MLS1_Bits.MLS1 */
#define IFX_GTM_DPLL_MLS1_MLS1_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_MLS2_Bits.MLS2 */
#define IFX_GTM_DPLL_MLS2_MLS2_LEN (18u)

/** \brief  Mask for Ifx_GTM_DPLL_MLS2_Bits.MLS2 */
#define IFX_GTM_DPLL_MLS2_MLS2_MSK (0x3ffffu)

/** \brief  Offset for Ifx_GTM_DPLL_MLS2_Bits.MLS2 */
#define IFX_GTM_DPLL_MLS2_MLS2_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_MPVAL1_Bits.MPVAL1 */
#define IFX_GTM_DPLL_MPVAL1_MPVAL1_LEN (16u)

/** \brief  Mask for Ifx_GTM_DPLL_MPVAL1_Bits.MPVAL1 */
#define IFX_GTM_DPLL_MPVAL1_MPVAL1_MSK (0xffffu)

/** \brief  Offset for Ifx_GTM_DPLL_MPVAL1_Bits.MPVAL1 */
#define IFX_GTM_DPLL_MPVAL1_MPVAL1_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_MPVAL1_Bits.SIX1 */
#define IFX_GTM_DPLL_MPVAL1_SIX1_LEN (8u)

/** \brief  Mask for Ifx_GTM_DPLL_MPVAL1_Bits.SIX1 */
#define IFX_GTM_DPLL_MPVAL1_SIX1_MSK (0xffu)

/** \brief  Offset for Ifx_GTM_DPLL_MPVAL1_Bits.SIX1 */
#define IFX_GTM_DPLL_MPVAL1_SIX1_OFF (16u)

/** \brief  Length for Ifx_GTM_DPLL_MPVAL2_Bits.MPVAL2 */
#define IFX_GTM_DPLL_MPVAL2_MPVAL2_LEN (16u)

/** \brief  Mask for Ifx_GTM_DPLL_MPVAL2_Bits.MPVAL2 */
#define IFX_GTM_DPLL_MPVAL2_MPVAL2_MSK (0xffffu)

/** \brief  Offset for Ifx_GTM_DPLL_MPVAL2_Bits.MPVAL2 */
#define IFX_GTM_DPLL_MPVAL2_MPVAL2_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_MPVAL2_Bits.SIX2 */
#define IFX_GTM_DPLL_MPVAL2_SIX2_LEN (8u)

/** \brief  Mask for Ifx_GTM_DPLL_MPVAL2_Bits.SIX2 */
#define IFX_GTM_DPLL_MPVAL2_SIX2_MSK (0xffu)

/** \brief  Offset for Ifx_GTM_DPLL_MPVAL2_Bits.SIX2 */
#define IFX_GTM_DPLL_MPVAL2_SIX2_OFF (16u)

/** \brief  Length for Ifx_GTM_DPLL_NA_Bits.DB */
#define IFX_GTM_DPLL_NA_DB_LEN (10u)

/** \brief  Mask for Ifx_GTM_DPLL_NA_Bits.DB */
#define IFX_GTM_DPLL_NA_DB_MSK (0x3ffu)

/** \brief  Offset for Ifx_GTM_DPLL_NA_Bits.DB */
#define IFX_GTM_DPLL_NA_DB_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_NA_Bits.DW */
#define IFX_GTM_DPLL_NA_DW_LEN (10u)

/** \brief  Mask for Ifx_GTM_DPLL_NA_Bits.DW */
#define IFX_GTM_DPLL_NA_DW_MSK (0x3ffu)

/** \brief  Offset for Ifx_GTM_DPLL_NA_Bits.DW */
#define IFX_GTM_DPLL_NA_DW_OFF (10u)

/** \brief  Length for Ifx_GTM_DPLL_NMB_S_Bits.NMB_S */
#define IFX_GTM_DPLL_NMB_S_NMB_S_LEN (20u)

/** \brief  Mask for Ifx_GTM_DPLL_NMB_S_Bits.NMB_S */
#define IFX_GTM_DPLL_NMB_S_NMB_S_MSK (0xfffffu)

/** \brief  Offset for Ifx_GTM_DPLL_NMB_S_Bits.NMB_S */
#define IFX_GTM_DPLL_NMB_S_NMB_S_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_NMB_S_TAR_Bits.NMB_S_TAR */
#define IFX_GTM_DPLL_NMB_S_TAR_NMB_S_TAR_LEN (20u)

/** \brief  Mask for Ifx_GTM_DPLL_NMB_S_TAR_Bits.NMB_S_TAR */
#define IFX_GTM_DPLL_NMB_S_TAR_NMB_S_TAR_MSK (0xfffffu)

/** \brief  Offset for Ifx_GTM_DPLL_NMB_S_TAR_Bits.NMB_S_TAR */
#define IFX_GTM_DPLL_NMB_S_TAR_NMB_S_TAR_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_NMB_S_TAR_OLD_Bits.NMB_S_TAR_OLD */
#define IFX_GTM_DPLL_NMB_S_TAR_OLD_NMB_S_TAR_OLD_LEN (20u)

/** \brief  Mask for Ifx_GTM_DPLL_NMB_S_TAR_OLD_Bits.NMB_S_TAR_OLD */
#define IFX_GTM_DPLL_NMB_S_TAR_OLD_NMB_S_TAR_OLD_MSK (0xfffffu)

/** \brief  Offset for Ifx_GTM_DPLL_NMB_S_TAR_OLD_Bits.NMB_S_TAR_OLD */
#define IFX_GTM_DPLL_NMB_S_TAR_OLD_NMB_S_TAR_OLD_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_NMB_T_Bits.NMB_T */
#define IFX_GTM_DPLL_NMB_T_NMB_T_LEN (16u)

/** \brief  Mask for Ifx_GTM_DPLL_NMB_T_Bits.NMB_T */
#define IFX_GTM_DPLL_NMB_T_NMB_T_MSK (0xffffu)

/** \brief  Offset for Ifx_GTM_DPLL_NMB_T_Bits.NMB_T */
#define IFX_GTM_DPLL_NMB_T_NMB_T_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_NMB_T_TAR_Bits.NMB_T_TAR */
#define IFX_GTM_DPLL_NMB_T_TAR_NMB_T_TAR_LEN (16u)

/** \brief  Mask for Ifx_GTM_DPLL_NMB_T_TAR_Bits.NMB_T_TAR */
#define IFX_GTM_DPLL_NMB_T_TAR_NMB_T_TAR_MSK (0xffffu)

/** \brief  Offset for Ifx_GTM_DPLL_NMB_T_TAR_Bits.NMB_T_TAR */
#define IFX_GTM_DPLL_NMB_T_TAR_NMB_T_TAR_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_NMB_T_TAR_OLD_Bits.NMB_T_TAR_OLD */
#define IFX_GTM_DPLL_NMB_T_TAR_OLD_NMB_T_TAR_OLD_LEN (16u)

/** \brief  Mask for Ifx_GTM_DPLL_NMB_T_TAR_OLD_Bits.NMB_T_TAR_OLD */
#define IFX_GTM_DPLL_NMB_T_TAR_OLD_NMB_T_TAR_OLD_MSK (0xffffu)

/** \brief  Offset for Ifx_GTM_DPLL_NMB_T_TAR_OLD_Bits.NMB_T_TAR_OLD */
#define IFX_GTM_DPLL_NMB_T_TAR_OLD_NMB_T_TAR_OLD_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_NTI_CNT_Bits.NTI_CNT */
#define IFX_GTM_DPLL_NTI_CNT_NTI_CNT_LEN (10u)

/** \brief  Mask for Ifx_GTM_DPLL_NTI_CNT_Bits.NTI_CNT */
#define IFX_GTM_DPLL_NTI_CNT_NTI_CNT_MSK (0x3ffu)

/** \brief  Offset for Ifx_GTM_DPLL_NTI_CNT_Bits.NTI_CNT */
#define IFX_GTM_DPLL_NTI_CNT_NTI_CNT_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_NUSC_Bits.FSS */
#define IFX_GTM_DPLL_NUSC_FSS_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_NUSC_Bits.FSS */
#define IFX_GTM_DPLL_NUSC_FSS_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_NUSC_Bits.FSS */
#define IFX_GTM_DPLL_NUSC_FSS_OFF (6u)

/** \brief  Length for Ifx_GTM_DPLL_NUSC_Bits.NUSE */
#define IFX_GTM_DPLL_NUSC_NUSE_LEN (6u)

/** \brief  Mask for Ifx_GTM_DPLL_NUSC_Bits.NUSE */
#define IFX_GTM_DPLL_NUSC_NUSE_MSK (0x3fu)

/** \brief  Offset for Ifx_GTM_DPLL_NUSC_Bits.NUSE */
#define IFX_GTM_DPLL_NUSC_NUSE_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_NUSC_Bits.SYN_S */
#define IFX_GTM_DPLL_NUSC_SYN_S_LEN (6u)

/** \brief  Mask for Ifx_GTM_DPLL_NUSC_Bits.SYN_S */
#define IFX_GTM_DPLL_NUSC_SYN_S_MSK (0x3fu)

/** \brief  Offset for Ifx_GTM_DPLL_NUSC_Bits.SYN_S */
#define IFX_GTM_DPLL_NUSC_SYN_S_OFF (7u)

/** \brief  Length for Ifx_GTM_DPLL_NUSC_Bits.SYN_S_OLD */
#define IFX_GTM_DPLL_NUSC_SYN_S_OLD_LEN (6u)

/** \brief  Mask for Ifx_GTM_DPLL_NUSC_Bits.SYN_S_OLD */
#define IFX_GTM_DPLL_NUSC_SYN_S_OLD_MSK (0x3fu)

/** \brief  Offset for Ifx_GTM_DPLL_NUSC_Bits.SYN_S_OLD */
#define IFX_GTM_DPLL_NUSC_SYN_S_OLD_OFF (13u)

/** \brief  Length for Ifx_GTM_DPLL_NUSC_Bits.VSN */
#define IFX_GTM_DPLL_NUSC_VSN_LEN (6u)

/** \brief  Mask for Ifx_GTM_DPLL_NUSC_Bits.VSN */
#define IFX_GTM_DPLL_NUSC_VSN_MSK (0x3fu)

/** \brief  Offset for Ifx_GTM_DPLL_NUSC_Bits.VSN */
#define IFX_GTM_DPLL_NUSC_VSN_OFF (19u)

/** \brief  Length for Ifx_GTM_DPLL_NUSC_Bits.WNUS */
#define IFX_GTM_DPLL_NUSC_WNUS_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_NUSC_Bits.WNUS */
#define IFX_GTM_DPLL_NUSC_WNUS_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_NUSC_Bits.WNUS */
#define IFX_GTM_DPLL_NUSC_WNUS_OFF (29u)

/** \brief  Length for Ifx_GTM_DPLL_NUSC_Bits.WSYN */
#define IFX_GTM_DPLL_NUSC_WSYN_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_NUSC_Bits.WSYN */
#define IFX_GTM_DPLL_NUSC_WSYN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_NUSC_Bits.WSYN */
#define IFX_GTM_DPLL_NUSC_WSYN_OFF (30u)

/** \brief  Length for Ifx_GTM_DPLL_NUSC_Bits.WVSN */
#define IFX_GTM_DPLL_NUSC_WVSN_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_NUSC_Bits.WVSN */
#define IFX_GTM_DPLL_NUSC_WVSN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_NUSC_Bits.WVSN */
#define IFX_GTM_DPLL_NUSC_WVSN_OFF (31u)

/** \brief  Length for Ifx_GTM_DPLL_NUTC_Bits.FST */
#define IFX_GTM_DPLL_NUTC_FST_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_NUTC_Bits.FST */
#define IFX_GTM_DPLL_NUTC_FST_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_NUTC_Bits.FST */
#define IFX_GTM_DPLL_NUTC_FST_OFF (10u)

/** \brief  Length for Ifx_GTM_DPLL_NUTC_Bits.NUTE */
#define IFX_GTM_DPLL_NUTC_NUTE_LEN (10u)

/** \brief  Mask for Ifx_GTM_DPLL_NUTC_Bits.NUTE */
#define IFX_GTM_DPLL_NUTC_NUTE_MSK (0x3ffu)

/** \brief  Offset for Ifx_GTM_DPLL_NUTC_Bits.NUTE */
#define IFX_GTM_DPLL_NUTC_NUTE_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_NUTC_Bits.SYN_T */
#define IFX_GTM_DPLL_NUTC_SYN_T_LEN (3u)

/** \brief  Mask for Ifx_GTM_DPLL_NUTC_Bits.SYN_T */
#define IFX_GTM_DPLL_NUTC_SYN_T_MSK (0x7u)

/** \brief  Offset for Ifx_GTM_DPLL_NUTC_Bits.SYN_T */
#define IFX_GTM_DPLL_NUTC_SYN_T_OFF (13u)

/** \brief  Length for Ifx_GTM_DPLL_NUTC_Bits.SYN_T_OLD */
#define IFX_GTM_DPLL_NUTC_SYN_T_OLD_LEN (3u)

/** \brief  Mask for Ifx_GTM_DPLL_NUTC_Bits.SYN_T_OLD */
#define IFX_GTM_DPLL_NUTC_SYN_T_OLD_MSK (0x7u)

/** \brief  Offset for Ifx_GTM_DPLL_NUTC_Bits.SYN_T_OLD */
#define IFX_GTM_DPLL_NUTC_SYN_T_OLD_OFF (16u)

/** \brief  Length for Ifx_GTM_DPLL_NUTC_Bits.VTN */
#define IFX_GTM_DPLL_NUTC_VTN_LEN (6u)

/** \brief  Mask for Ifx_GTM_DPLL_NUTC_Bits.VTN */
#define IFX_GTM_DPLL_NUTC_VTN_MSK (0x3fu)

/** \brief  Offset for Ifx_GTM_DPLL_NUTC_Bits.VTN */
#define IFX_GTM_DPLL_NUTC_VTN_OFF (19u)

/** \brief  Length for Ifx_GTM_DPLL_NUTC_Bits.WNUT */
#define IFX_GTM_DPLL_NUTC_WNUT_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_NUTC_Bits.WNUT */
#define IFX_GTM_DPLL_NUTC_WNUT_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_NUTC_Bits.WNUT */
#define IFX_GTM_DPLL_NUTC_WNUT_OFF (29u)

/** \brief  Length for Ifx_GTM_DPLL_NUTC_Bits.WSYN */
#define IFX_GTM_DPLL_NUTC_WSYN_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_NUTC_Bits.WSYN */
#define IFX_GTM_DPLL_NUTC_WSYN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_NUTC_Bits.WSYN */
#define IFX_GTM_DPLL_NUTC_WSYN_OFF (30u)

/** \brief  Length for Ifx_GTM_DPLL_NUTC_Bits.WVTN */
#define IFX_GTM_DPLL_NUTC_WVTN_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_NUTC_Bits.WVTN */
#define IFX_GTM_DPLL_NUTC_WVTN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_NUTC_Bits.WVTN */
#define IFX_GTM_DPLL_NUTC_WVTN_OFF (31u)

/** \brief  Length for Ifx_GTM_DPLL_OSW_Bits.OSS */
#define IFX_GTM_DPLL_OSW_OSS_LEN (2u)

/** \brief  Mask for Ifx_GTM_DPLL_OSW_Bits.OSS */
#define IFX_GTM_DPLL_OSW_OSS_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_DPLL_OSW_Bits.OSS */
#define IFX_GTM_DPLL_OSW_OSS_OFF (8u)

/** \brief  Length for Ifx_GTM_DPLL_OSW_Bits.SWON_S */
#define IFX_GTM_DPLL_OSW_SWON_S_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_OSW_Bits.SWON_S */
#define IFX_GTM_DPLL_OSW_SWON_S_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_OSW_Bits.SWON_S */
#define IFX_GTM_DPLL_OSW_SWON_S_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_OSW_Bits.SWON_T */
#define IFX_GTM_DPLL_OSW_SWON_T_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_OSW_Bits.SWON_T */
#define IFX_GTM_DPLL_OSW_SWON_T_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_OSW_Bits.SWON_T */
#define IFX_GTM_DPLL_OSW_SWON_T_OFF (1u)

/** \brief  Length for Ifx_GTM_DPLL_PDT_T_Bits.DB */
#define IFX_GTM_DPLL_PDT_T_DB_LEN (14u)

/** \brief  Mask for Ifx_GTM_DPLL_PDT_T_Bits.DB */
#define IFX_GTM_DPLL_PDT_T_DB_MSK (0x3fffu)

/** \brief  Offset for Ifx_GTM_DPLL_PDT_T_Bits.DB */
#define IFX_GTM_DPLL_PDT_T_DB_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_PDT_T_Bits.DW */
#define IFX_GTM_DPLL_PDT_T_DW_LEN (10u)

/** \brief  Mask for Ifx_GTM_DPLL_PDT_T_Bits.DW */
#define IFX_GTM_DPLL_PDT_T_DW_MSK (0x3ffu)

/** \brief  Offset for Ifx_GTM_DPLL_PDT_T_Bits.DW */
#define IFX_GTM_DPLL_PDT_T_DW_OFF (14u)

/** \brief  Length for Ifx_GTM_DPLL_PSA_Bits.PSA */
#define IFX_GTM_DPLL_PSA_PSA_LEN (24u)

/** \brief  Mask for Ifx_GTM_DPLL_PSA_Bits.PSA */
#define IFX_GTM_DPLL_PSA_PSA_MSK (0xffffffu)

/** \brief  Offset for Ifx_GTM_DPLL_PSA_Bits.PSA */
#define IFX_GTM_DPLL_PSA_PSA_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_PSAC_Bits.PSAC */
#define IFX_GTM_DPLL_PSAC_PSAC_LEN (24u)

/** \brief  Mask for Ifx_GTM_DPLL_PSAC_Bits.PSAC */
#define IFX_GTM_DPLL_PSAC_PSAC_MSK (0xffffffu)

/** \brief  Offset for Ifx_GTM_DPLL_PSAC_Bits.PSAC */
#define IFX_GTM_DPLL_PSAC_PSAC_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_PSSC_Bits.PSSC */
#define IFX_GTM_DPLL_PSSC_PSSC_LEN (24u)

/** \brief  Mask for Ifx_GTM_DPLL_PSSC_Bits.PSSC */
#define IFX_GTM_DPLL_PSSC_PSSC_MSK (0xffffffu)

/** \brief  Offset for Ifx_GTM_DPLL_PSSC_Bits.PSSC */
#define IFX_GTM_DPLL_PSSC_PSSC_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_PSSM_0_Bits.PSSM */
#define IFX_GTM_DPLL_PSSM_0_PSSM_LEN (24u)

/** \brief  Mask for Ifx_GTM_DPLL_PSSM_0_Bits.PSSM */
#define IFX_GTM_DPLL_PSSM_0_PSSM_MSK (0xffffffu)

/** \brief  Offset for Ifx_GTM_DPLL_PSSM_0_Bits.PSSM */
#define IFX_GTM_DPLL_PSSM_0_PSSM_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_PSSM_1_Bits.PSSM */
#define IFX_GTM_DPLL_PSSM_1_PSSM_LEN (24u)

/** \brief  Mask for Ifx_GTM_DPLL_PSSM_1_Bits.PSSM */
#define IFX_GTM_DPLL_PSSM_1_PSSM_MSK (0xffffffu)

/** \brief  Offset for Ifx_GTM_DPLL_PSSM_1_Bits.PSSM */
#define IFX_GTM_DPLL_PSSM_1_PSSM_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_PSTC_Bits.PSTC */
#define IFX_GTM_DPLL_PSTC_PSTC_LEN (24u)

/** \brief  Mask for Ifx_GTM_DPLL_PSTC_Bits.PSTC */
#define IFX_GTM_DPLL_PSTC_PSTC_MSK (0xffffffu)

/** \brief  Offset for Ifx_GTM_DPLL_PSTC_Bits.PSTC */
#define IFX_GTM_DPLL_PSTC_PSTC_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_PSTM_0_Bits.PSTM */
#define IFX_GTM_DPLL_PSTM_0_PSTM_LEN (24u)

/** \brief  Mask for Ifx_GTM_DPLL_PSTM_0_Bits.PSTM */
#define IFX_GTM_DPLL_PSTM_0_PSTM_MSK (0xffffffu)

/** \brief  Offset for Ifx_GTM_DPLL_PSTM_0_Bits.PSTM */
#define IFX_GTM_DPLL_PSTM_0_PSTM_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_PSTM_1_Bits.PSTM */
#define IFX_GTM_DPLL_PSTM_1_PSTM_LEN (24u)

/** \brief  Mask for Ifx_GTM_DPLL_PSTM_1_Bits.PSTM */
#define IFX_GTM_DPLL_PSTM_1_PSTM_MSK (0xffffffu)

/** \brief  Offset for Ifx_GTM_DPLL_PSTM_1_Bits.PSTM */
#define IFX_GTM_DPLL_PSTM_1_PSTM_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_PVT_Bits.PVT */
#define IFX_GTM_DPLL_PVT_PVT_LEN (24u)

/** \brief  Mask for Ifx_GTM_DPLL_PVT_Bits.PVT */
#define IFX_GTM_DPLL_PVT_PVT_MSK (0xffffffu)

/** \brief  Offset for Ifx_GTM_DPLL_PVT_Bits.PVT */
#define IFX_GTM_DPLL_PVT_PVT_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_RAM_INI_Bits.INIT_1A */
#define IFX_GTM_DPLL_RAM_INI_INIT_1A_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_RAM_INI_Bits.INIT_1A */
#define IFX_GTM_DPLL_RAM_INI_INIT_1A_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_RAM_INI_Bits.INIT_1A */
#define IFX_GTM_DPLL_RAM_INI_INIT_1A_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_RAM_INI_Bits.INIT_1B */
#define IFX_GTM_DPLL_RAM_INI_INIT_1B_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_RAM_INI_Bits.INIT_1B */
#define IFX_GTM_DPLL_RAM_INI_INIT_1B_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_RAM_INI_Bits.INIT_1B */
#define IFX_GTM_DPLL_RAM_INI_INIT_1B_OFF (1u)

/** \brief  Length for Ifx_GTM_DPLL_RAM_INI_Bits.INIT_2 */
#define IFX_GTM_DPLL_RAM_INI_INIT_2_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_RAM_INI_Bits.INIT_2 */
#define IFX_GTM_DPLL_RAM_INI_INIT_2_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_RAM_INI_Bits.INIT_2 */
#define IFX_GTM_DPLL_RAM_INI_INIT_2_OFF (2u)

/** \brief  Length for Ifx_GTM_DPLL_RAM_INI_Bits.INIT_RAM */
#define IFX_GTM_DPLL_RAM_INI_INIT_RAM_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_RAM_INI_Bits.INIT_RAM */
#define IFX_GTM_DPLL_RAM_INI_INIT_RAM_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_RAM_INI_Bits.INIT_RAM */
#define IFX_GTM_DPLL_RAM_INI_INIT_RAM_OFF (4u)

/** \brief  Length for Ifx_GTM_DPLL_RCDT_SX_NOM_Bits.RCDT_SX_NOM */
#define IFX_GTM_DPLL_RCDT_SX_NOM_RCDT_SX_NOM_LEN (24u)

/** \brief  Mask for Ifx_GTM_DPLL_RCDT_SX_NOM_Bits.RCDT_SX_NOM */
#define IFX_GTM_DPLL_RCDT_SX_NOM_RCDT_SX_NOM_MSK (0xffffffu)

/** \brief  Offset for Ifx_GTM_DPLL_RCDT_SX_NOM_Bits.RCDT_SX_NOM */
#define IFX_GTM_DPLL_RCDT_SX_NOM_RCDT_SX_NOM_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_RCDT_SX_Bits.RCDT_SX */
#define IFX_GTM_DPLL_RCDT_SX_RCDT_SX_LEN (24u)

/** \brief  Mask for Ifx_GTM_DPLL_RCDT_SX_Bits.RCDT_SX */
#define IFX_GTM_DPLL_RCDT_SX_RCDT_SX_MSK (0xffffffu)

/** \brief  Offset for Ifx_GTM_DPLL_RCDT_SX_Bits.RCDT_SX */
#define IFX_GTM_DPLL_RCDT_SX_RCDT_SX_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_RCDT_TX_NOM_Bits.RCDT_TX_NOM */
#define IFX_GTM_DPLL_RCDT_TX_NOM_RCDT_TX_NOM_LEN (24u)

/** \brief  Mask for Ifx_GTM_DPLL_RCDT_TX_NOM_Bits.RCDT_TX_NOM */
#define IFX_GTM_DPLL_RCDT_TX_NOM_RCDT_TX_NOM_MSK (0xffffffu)

/** \brief  Offset for Ifx_GTM_DPLL_RCDT_TX_NOM_Bits.RCDT_TX_NOM */
#define IFX_GTM_DPLL_RCDT_TX_NOM_RCDT_TX_NOM_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_RCDT_TX_Bits.RCDT_TX */
#define IFX_GTM_DPLL_RCDT_TX_RCDT_TX_LEN (24u)

/** \brief  Mask for Ifx_GTM_DPLL_RCDT_TX_Bits.RCDT_TX */
#define IFX_GTM_DPLL_RCDT_TX_RCDT_TX_MSK (0xffffffu)

/** \brief  Offset for Ifx_GTM_DPLL_RCDT_TX_Bits.RCDT_TX */
#define IFX_GTM_DPLL_RCDT_TX_RCDT_TX_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_RDT_S_ACT_Bits.RDT_S_ACT */
#define IFX_GTM_DPLL_RDT_S_ACT_RDT_S_ACT_LEN (24u)

/** \brief  Mask for Ifx_GTM_DPLL_RDT_S_ACT_Bits.RDT_S_ACT */
#define IFX_GTM_DPLL_RDT_S_ACT_RDT_S_ACT_MSK (0xffffffu)

/** \brief  Offset for Ifx_GTM_DPLL_RDT_S_ACT_Bits.RDT_S_ACT */
#define IFX_GTM_DPLL_RDT_S_ACT_RDT_S_ACT_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_RDT_S_Bits.RDT_S */
#define IFX_GTM_DPLL_RDT_S_RDT_S_LEN (24u)

/** \brief  Mask for Ifx_GTM_DPLL_RDT_S_Bits.RDT_S */
#define IFX_GTM_DPLL_RDT_S_RDT_S_MSK (0xffffffu)

/** \brief  Offset for Ifx_GTM_DPLL_RDT_S_Bits.RDT_S */
#define IFX_GTM_DPLL_RDT_S_RDT_S_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_RDT_T_ACT_Bits.RDT_T_ACT */
#define IFX_GTM_DPLL_RDT_T_ACT_RDT_T_ACT_LEN (24u)

/** \brief  Mask for Ifx_GTM_DPLL_RDT_T_ACT_Bits.RDT_T_ACT */
#define IFX_GTM_DPLL_RDT_T_ACT_RDT_T_ACT_MSK (0xffffffu)

/** \brief  Offset for Ifx_GTM_DPLL_RDT_T_ACT_Bits.RDT_T_ACT */
#define IFX_GTM_DPLL_RDT_T_ACT_RDT_T_ACT_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_SLR_Bits.SLR */
#define IFX_GTM_DPLL_SLR_SLR_LEN (8u)

/** \brief  Mask for Ifx_GTM_DPLL_SLR_Bits.SLR */
#define IFX_GTM_DPLL_SLR_SLR_MSK (0xffu)

/** \brief  Offset for Ifx_GTM_DPLL_SLR_Bits.SLR */
#define IFX_GTM_DPLL_SLR_SLR_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_STATUS_Bits.BWD1 */
#define IFX_GTM_DPLL_STATUS_BWD1_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_STATUS_Bits.BWD1 */
#define IFX_GTM_DPLL_STATUS_BWD1_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_STATUS_Bits.BWD1 */
#define IFX_GTM_DPLL_STATUS_BWD1_OFF (23u)

/** \brief  Length for Ifx_GTM_DPLL_STATUS_Bits.BWD2 */
#define IFX_GTM_DPLL_STATUS_BWD2_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_STATUS_Bits.BWD2 */
#define IFX_GTM_DPLL_STATUS_BWD2_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_STATUS_Bits.BWD2 */
#define IFX_GTM_DPLL_STATUS_BWD2_OFF (22u)

/** \brief  Length for Ifx_GTM_DPLL_STATUS_Bits.CAIP1 */
#define IFX_GTM_DPLL_STATUS_CAIP1_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_STATUS_Bits.CAIP1 */
#define IFX_GTM_DPLL_STATUS_CAIP1_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_STATUS_Bits.CAIP1 */
#define IFX_GTM_DPLL_STATUS_CAIP1_OFF (19u)

/** \brief  Length for Ifx_GTM_DPLL_STATUS_Bits.CAIP2 */
#define IFX_GTM_DPLL_STATUS_CAIP2_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_STATUS_Bits.CAIP2 */
#define IFX_GTM_DPLL_STATUS_CAIP2_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_STATUS_Bits.CAIP2 */
#define IFX_GTM_DPLL_STATUS_CAIP2_OFF (18u)

/** \brief  Length for Ifx_GTM_DPLL_STATUS_Bits.CRO */
#define IFX_GTM_DPLL_STATUS_CRO_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_STATUS_Bits.CRO */
#define IFX_GTM_DPLL_STATUS_CRO_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_STATUS_Bits.CRO */
#define IFX_GTM_DPLL_STATUS_CRO_OFF (4u)

/** \brief  Length for Ifx_GTM_DPLL_STATUS_Bits.CSO */
#define IFX_GTM_DPLL_STATUS_CSO_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_STATUS_Bits.CSO */
#define IFX_GTM_DPLL_STATUS_CSO_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_STATUS_Bits.CSO */
#define IFX_GTM_DPLL_STATUS_CSO_OFF (1u)

/** \brief  Length for Ifx_GTM_DPLL_STATUS_Bits.CSVS */
#define IFX_GTM_DPLL_STATUS_CSVS_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_STATUS_Bits.CSVS */
#define IFX_GTM_DPLL_STATUS_CSVS_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_STATUS_Bits.CSVS */
#define IFX_GTM_DPLL_STATUS_CSVS_OFF (16u)

/** \brief  Length for Ifx_GTM_DPLL_STATUS_Bits.CSVT */
#define IFX_GTM_DPLL_STATUS_CSVT_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_STATUS_Bits.CSVT */
#define IFX_GTM_DPLL_STATUS_CSVT_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_STATUS_Bits.CSVT */
#define IFX_GTM_DPLL_STATUS_CSVT_OFF (17u)

/** \brief  Length for Ifx_GTM_DPLL_STATUS_Bits.CTO */
#define IFX_GTM_DPLL_STATUS_CTO_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_STATUS_Bits.CTO */
#define IFX_GTM_DPLL_STATUS_CTO_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_STATUS_Bits.CTO */
#define IFX_GTM_DPLL_STATUS_CTO_OFF (3u)

/** \brief  Length for Ifx_GTM_DPLL_STATUS_Bits.ERR */
#define IFX_GTM_DPLL_STATUS_ERR_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_STATUS_Bits.ERR */
#define IFX_GTM_DPLL_STATUS_ERR_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_STATUS_Bits.ERR */
#define IFX_GTM_DPLL_STATUS_ERR_OFF (31u)

/** \brief  Length for Ifx_GTM_DPLL_STATUS_Bits.FSD */
#define IFX_GTM_DPLL_STATUS_FSD_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_STATUS_Bits.FSD */
#define IFX_GTM_DPLL_STATUS_FSD_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_STATUS_Bits.FSD */
#define IFX_GTM_DPLL_STATUS_FSD_OFF (28u)

/** \brief  Length for Ifx_GTM_DPLL_STATUS_Bits.FTD */
#define IFX_GTM_DPLL_STATUS_FTD_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_STATUS_Bits.FTD */
#define IFX_GTM_DPLL_STATUS_FTD_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_STATUS_Bits.FTD */
#define IFX_GTM_DPLL_STATUS_FTD_OFF (29u)

/** \brief  Length for Ifx_GTM_DPLL_STATUS_Bits.ISN */
#define IFX_GTM_DPLL_STATUS_ISN_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_STATUS_Bits.ISN */
#define IFX_GTM_DPLL_STATUS_ISN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_STATUS_Bits.ISN */
#define IFX_GTM_DPLL_STATUS_ISN_OFF (20u)

/** \brief  Length for Ifx_GTM_DPLL_STATUS_Bits.ITN */
#define IFX_GTM_DPLL_STATUS_ITN_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_STATUS_Bits.ITN */
#define IFX_GTM_DPLL_STATUS_ITN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_STATUS_Bits.ITN */
#define IFX_GTM_DPLL_STATUS_ITN_OFF (21u)

/** \brief  Length for Ifx_GTM_DPLL_STATUS_Bits.LOCK1 */
#define IFX_GTM_DPLL_STATUS_LOCK1_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_STATUS_Bits.LOCK1 */
#define IFX_GTM_DPLL_STATUS_LOCK1_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_STATUS_Bits.LOCK1 */
#define IFX_GTM_DPLL_STATUS_LOCK1_OFF (30u)

/** \brief  Length for Ifx_GTM_DPLL_STATUS_Bits.LOCK2 */
#define IFX_GTM_DPLL_STATUS_LOCK2_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_STATUS_Bits.LOCK2 */
#define IFX_GTM_DPLL_STATUS_LOCK2_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_STATUS_Bits.LOCK2 */
#define IFX_GTM_DPLL_STATUS_LOCK2_OFF (25u)

/** \brief  Length for Ifx_GTM_DPLL_STATUS_Bits.LOW_RES */
#define IFX_GTM_DPLL_STATUS_LOW_RES_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_STATUS_Bits.LOW_RES */
#define IFX_GTM_DPLL_STATUS_LOW_RES_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_STATUS_Bits.LOW_RES */
#define IFX_GTM_DPLL_STATUS_LOW_RES_OFF (15u)

/** \brief  Length for Ifx_GTM_DPLL_STATUS_Bits.MS */
#define IFX_GTM_DPLL_STATUS_MS_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_STATUS_Bits.MS */
#define IFX_GTM_DPLL_STATUS_MS_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_STATUS_Bits.MS */
#define IFX_GTM_DPLL_STATUS_MS_OFF (9u)

/** \brief  Length for Ifx_GTM_DPLL_STATUS_Bits.MT */
#define IFX_GTM_DPLL_STATUS_MT_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_STATUS_Bits.MT */
#define IFX_GTM_DPLL_STATUS_MT_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_STATUS_Bits.MT */
#define IFX_GTM_DPLL_STATUS_MT_OFF (11u)

/** \brief  Length for Ifx_GTM_DPLL_STATUS_Bits.PSE */
#define IFX_GTM_DPLL_STATUS_PSE_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_STATUS_Bits.PSE */
#define IFX_GTM_DPLL_STATUS_PSE_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_STATUS_Bits.PSE */
#define IFX_GTM_DPLL_STATUS_PSE_OFF (7u)

/** \brief  Length for Ifx_GTM_DPLL_STATUS_Bits.RAM2_ERR */
#define IFX_GTM_DPLL_STATUS_RAM2_ERR_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_STATUS_Bits.RAM2_ERR */
#define IFX_GTM_DPLL_STATUS_RAM2_ERR_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_STATUS_Bits.RAM2_ERR */
#define IFX_GTM_DPLL_STATUS_RAM2_ERR_OFF (12u)

/** \brief  Length for Ifx_GTM_DPLL_STATUS_Bits.RCS */
#define IFX_GTM_DPLL_STATUS_RCS_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_STATUS_Bits.RCS */
#define IFX_GTM_DPLL_STATUS_RCS_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_STATUS_Bits.RCS */
#define IFX_GTM_DPLL_STATUS_RCS_OFF (5u)

/** \brief  Length for Ifx_GTM_DPLL_STATUS_Bits.RCT */
#define IFX_GTM_DPLL_STATUS_RCT_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_STATUS_Bits.RCT */
#define IFX_GTM_DPLL_STATUS_RCT_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_STATUS_Bits.RCT */
#define IFX_GTM_DPLL_STATUS_RCT_OFF (6u)

/** \brief  Length for Ifx_GTM_DPLL_STATUS_Bits.SOR */
#define IFX_GTM_DPLL_STATUS_SOR_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_STATUS_Bits.SOR */
#define IFX_GTM_DPLL_STATUS_SOR_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_STATUS_Bits.SOR */
#define IFX_GTM_DPLL_STATUS_SOR_OFF (8u)

/** \brief  Length for Ifx_GTM_DPLL_STATUS_Bits.SYS */
#define IFX_GTM_DPLL_STATUS_SYS_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_STATUS_Bits.SYS */
#define IFX_GTM_DPLL_STATUS_SYS_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_STATUS_Bits.SYS */
#define IFX_GTM_DPLL_STATUS_SYS_OFF (26u)

/** \brief  Length for Ifx_GTM_DPLL_STATUS_Bits.SYT */
#define IFX_GTM_DPLL_STATUS_SYT_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_STATUS_Bits.SYT */
#define IFX_GTM_DPLL_STATUS_SYT_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_STATUS_Bits.SYT */
#define IFX_GTM_DPLL_STATUS_SYT_OFF (27u)

/** \brief  Length for Ifx_GTM_DPLL_STATUS_Bits.TOR */
#define IFX_GTM_DPLL_STATUS_TOR_LEN (1u)

/** \brief  Mask for Ifx_GTM_DPLL_STATUS_Bits.TOR */
#define IFX_GTM_DPLL_STATUS_TOR_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DPLL_STATUS_Bits.TOR */
#define IFX_GTM_DPLL_STATUS_TOR_OFF (10u)

/** \brief  Length for Ifx_GTM_DPLL_TBU_TS0_S_Bits.TBU_TS0_S */
#define IFX_GTM_DPLL_TBU_TS0_S_TBU_TS0_S_LEN (24u)

/** \brief  Mask for Ifx_GTM_DPLL_TBU_TS0_S_Bits.TBU_TS0_S */
#define IFX_GTM_DPLL_TBU_TS0_S_TBU_TS0_S_MSK (0xffffffu)

/** \brief  Offset for Ifx_GTM_DPLL_TBU_TS0_S_Bits.TBU_TS0_S */
#define IFX_GTM_DPLL_TBU_TS0_S_TBU_TS0_S_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_TBU_TS0_T_Bits.TBU_TS0_T */
#define IFX_GTM_DPLL_TBU_TS0_T_TBU_TS0_T_LEN (24u)

/** \brief  Mask for Ifx_GTM_DPLL_TBU_TS0_T_Bits.TBU_TS0_T */
#define IFX_GTM_DPLL_TBU_TS0_T_TBU_TS0_T_MSK (0xffffffu)

/** \brief  Offset for Ifx_GTM_DPLL_TBU_TS0_T_Bits.TBU_TS0_T */
#define IFX_GTM_DPLL_TBU_TS0_T_TBU_TS0_T_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_THMA_Bits.THMA */
#define IFX_GTM_DPLL_THMA_THMA_LEN (16u)

/** \brief  Mask for Ifx_GTM_DPLL_THMA_Bits.THMA */
#define IFX_GTM_DPLL_THMA_THMA_MSK (0xffffu)

/** \brief  Offset for Ifx_GTM_DPLL_THMA_Bits.THMA */
#define IFX_GTM_DPLL_THMA_THMA_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_THMI_Bits.THMI */
#define IFX_GTM_DPLL_THMI_THMI_LEN (16u)

/** \brief  Mask for Ifx_GTM_DPLL_THMI_Bits.THMI */
#define IFX_GTM_DPLL_THMI_THMI_MSK (0xffffu)

/** \brief  Offset for Ifx_GTM_DPLL_THMI_Bits.THMI */
#define IFX_GTM_DPLL_THMI_THMI_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_THVAL_Bits.THVAL */
#define IFX_GTM_DPLL_THVAL_THVAL_LEN (16u)

/** \brief  Mask for Ifx_GTM_DPLL_THVAL_Bits.THVAL */
#define IFX_GTM_DPLL_THVAL_THVAL_MSK (0xffffu)

/** \brief  Offset for Ifx_GTM_DPLL_THVAL_Bits.THVAL */
#define IFX_GTM_DPLL_THVAL_THVAL_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_TLR_Bits.TLR */
#define IFX_GTM_DPLL_TLR_TLR_LEN (8u)

/** \brief  Mask for Ifx_GTM_DPLL_TLR_Bits.TLR */
#define IFX_GTM_DPLL_TLR_TLR_MSK (0xffu)

/** \brief  Offset for Ifx_GTM_DPLL_TLR_Bits.TLR */
#define IFX_GTM_DPLL_TLR_TLR_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_TOV_Bits.DB */
#define IFX_GTM_DPLL_TOV_DB_LEN (10u)

/** \brief  Mask for Ifx_GTM_DPLL_TOV_Bits.DB */
#define IFX_GTM_DPLL_TOV_DB_MSK (0x3ffu)

/** \brief  Offset for Ifx_GTM_DPLL_TOV_Bits.DB */
#define IFX_GTM_DPLL_TOV_DB_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_TOV_Bits.DW */
#define IFX_GTM_DPLL_TOV_DW_LEN (6u)

/** \brief  Mask for Ifx_GTM_DPLL_TOV_Bits.DW */
#define IFX_GTM_DPLL_TOV_DW_MSK (0x3fu)

/** \brief  Offset for Ifx_GTM_DPLL_TOV_Bits.DW */
#define IFX_GTM_DPLL_TOV_DW_OFF (10u)

/** \brief  Length for Ifx_GTM_DPLL_TOV_S_Bits.DB */
#define IFX_GTM_DPLL_TOV_S_DB_LEN (10u)

/** \brief  Mask for Ifx_GTM_DPLL_TOV_S_Bits.DB */
#define IFX_GTM_DPLL_TOV_S_DB_MSK (0x3ffu)

/** \brief  Offset for Ifx_GTM_DPLL_TOV_S_Bits.DB */
#define IFX_GTM_DPLL_TOV_S_DB_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_TOV_S_Bits.DW */
#define IFX_GTM_DPLL_TOV_S_DW_LEN (6u)

/** \brief  Mask for Ifx_GTM_DPLL_TOV_S_Bits.DW */
#define IFX_GTM_DPLL_TOV_S_DW_MSK (0x3fu)

/** \brief  Offset for Ifx_GTM_DPLL_TOV_S_Bits.DW */
#define IFX_GTM_DPLL_TOV_S_DW_OFF (10u)

/** \brief  Length for Ifx_GTM_DPLL_TS_S_0_Bits.STATE_TS */
#define IFX_GTM_DPLL_TS_S_0_STATE_TS_LEN (24u)

/** \brief  Mask for Ifx_GTM_DPLL_TS_S_0_Bits.STATE_TS */
#define IFX_GTM_DPLL_TS_S_0_STATE_TS_MSK (0xffffffu)

/** \brief  Offset for Ifx_GTM_DPLL_TS_S_0_Bits.STATE_TS */
#define IFX_GTM_DPLL_TS_S_0_STATE_TS_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_TS_S_1_Bits.STATE_TS */
#define IFX_GTM_DPLL_TS_S_1_STATE_TS_LEN (24u)

/** \brief  Mask for Ifx_GTM_DPLL_TS_S_1_Bits.STATE_TS */
#define IFX_GTM_DPLL_TS_S_1_STATE_TS_MSK (0xffffffu)

/** \brief  Offset for Ifx_GTM_DPLL_TS_S_1_Bits.STATE_TS */
#define IFX_GTM_DPLL_TS_S_1_STATE_TS_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_TS_T_0_Bits.TRIGGER_TS */
#define IFX_GTM_DPLL_TS_T_0_TRIGGER_TS_LEN (24u)

/** \brief  Mask for Ifx_GTM_DPLL_TS_T_0_Bits.TRIGGER_TS */
#define IFX_GTM_DPLL_TS_T_0_TRIGGER_TS_MSK (0xffffffu)

/** \brief  Offset for Ifx_GTM_DPLL_TS_T_0_Bits.TRIGGER_TS */
#define IFX_GTM_DPLL_TS_T_0_TRIGGER_TS_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_TS_T_1_Bits.TRIGGER_TS */
#define IFX_GTM_DPLL_TS_T_1_TRIGGER_TS_LEN (24u)

/** \brief  Mask for Ifx_GTM_DPLL_TS_T_1_Bits.TRIGGER_TS */
#define IFX_GTM_DPLL_TS_T_1_TRIGGER_TS_MSK (0xffffffu)

/** \brief  Offset for Ifx_GTM_DPLL_TS_T_1_Bits.TRIGGER_TS */
#define IFX_GTM_DPLL_TS_T_1_TRIGGER_TS_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_TSAC_Bits.TSAC */
#define IFX_GTM_DPLL_TSAC_TSAC_LEN (24u)

/** \brief  Mask for Ifx_GTM_DPLL_TSAC_Bits.TSAC */
#define IFX_GTM_DPLL_TSAC_TSAC_MSK (0xffffffu)

/** \brief  Offset for Ifx_GTM_DPLL_TSAC_Bits.TSAC */
#define IFX_GTM_DPLL_TSAC_TSAC_OFF (0u)

/** \brief  Length for Ifx_GTM_DPLL_TSF_S_Bits.TSF_S */
#define IFX_GTM_DPLL_TSF_S_TSF_S_LEN (24u)

/** \brief  Mask for Ifx_GTM_DPLL_TSF_S_Bits.TSF_S */
#define IFX_GTM_DPLL_TSF_S_TSF_S_MSK (0xffffffu)

/** \brief  Offset for Ifx_GTM_DPLL_TSF_S_Bits.TSF_S */
#define IFX_GTM_DPLL_TSF_S_TSF_S_OFF (0u)

/** \brief  Length for Ifx_GTM_DXINCON_Bits.DSS00 */
#define IFX_GTM_DXINCON_DSS00_LEN (1u)

/** \brief  Mask for Ifx_GTM_DXINCON_Bits.DSS00 */
#define IFX_GTM_DXINCON_DSS00_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DXINCON_Bits.DSS00 */
#define IFX_GTM_DXINCON_DSS00_OFF (16u)

/** \brief  Length for Ifx_GTM_DXINCON_Bits.DSS01 */
#define IFX_GTM_DXINCON_DSS01_LEN (1u)

/** \brief  Mask for Ifx_GTM_DXINCON_Bits.DSS01 */
#define IFX_GTM_DXINCON_DSS01_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DXINCON_Bits.DSS01 */
#define IFX_GTM_DXINCON_DSS01_OFF (17u)

/** \brief  Length for Ifx_GTM_DXINCON_Bits.DSS02 */
#define IFX_GTM_DXINCON_DSS02_LEN (1u)

/** \brief  Mask for Ifx_GTM_DXINCON_Bits.DSS02 */
#define IFX_GTM_DXINCON_DSS02_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DXINCON_Bits.DSS02 */
#define IFX_GTM_DXINCON_DSS02_OFF (18u)

/** \brief  Length for Ifx_GTM_DXINCON_Bits.DSS10 */
#define IFX_GTM_DXINCON_DSS10_LEN (1u)

/** \brief  Mask for Ifx_GTM_DXINCON_Bits.DSS10 */
#define IFX_GTM_DXINCON_DSS10_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DXINCON_Bits.DSS10 */
#define IFX_GTM_DXINCON_DSS10_OFF (24u)

/** \brief  Length for Ifx_GTM_DXINCON_Bits.DSS11 */
#define IFX_GTM_DXINCON_DSS11_LEN (1u)

/** \brief  Mask for Ifx_GTM_DXINCON_Bits.DSS11 */
#define IFX_GTM_DXINCON_DSS11_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DXINCON_Bits.DSS11 */
#define IFX_GTM_DXINCON_DSS11_OFF (25u)

/** \brief  Length for Ifx_GTM_DXINCON_Bits.DSS12 */
#define IFX_GTM_DXINCON_DSS12_LEN (1u)

/** \brief  Mask for Ifx_GTM_DXINCON_Bits.DSS12 */
#define IFX_GTM_DXINCON_DSS12_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DXINCON_Bits.DSS12 */
#define IFX_GTM_DXINCON_DSS12_OFF (26u)

/** \brief  Length for Ifx_GTM_DXINCON_Bits.IN00 */
#define IFX_GTM_DXINCON_IN00_LEN (1u)

/** \brief  Mask for Ifx_GTM_DXINCON_Bits.IN00 */
#define IFX_GTM_DXINCON_IN00_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DXINCON_Bits.IN00 */
#define IFX_GTM_DXINCON_IN00_OFF (0u)

/** \brief  Length for Ifx_GTM_DXINCON_Bits.IN01 */
#define IFX_GTM_DXINCON_IN01_LEN (1u)

/** \brief  Mask for Ifx_GTM_DXINCON_Bits.IN01 */
#define IFX_GTM_DXINCON_IN01_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DXINCON_Bits.IN01 */
#define IFX_GTM_DXINCON_IN01_OFF (1u)

/** \brief  Length for Ifx_GTM_DXINCON_Bits.IN02 */
#define IFX_GTM_DXINCON_IN02_LEN (1u)

/** \brief  Mask for Ifx_GTM_DXINCON_Bits.IN02 */
#define IFX_GTM_DXINCON_IN02_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DXINCON_Bits.IN02 */
#define IFX_GTM_DXINCON_IN02_OFF (2u)

/** \brief  Length for Ifx_GTM_DXINCON_Bits.IN10 */
#define IFX_GTM_DXINCON_IN10_LEN (1u)

/** \brief  Mask for Ifx_GTM_DXINCON_Bits.IN10 */
#define IFX_GTM_DXINCON_IN10_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DXINCON_Bits.IN10 */
#define IFX_GTM_DXINCON_IN10_OFF (8u)

/** \brief  Length for Ifx_GTM_DXINCON_Bits.IN11 */
#define IFX_GTM_DXINCON_IN11_LEN (1u)

/** \brief  Mask for Ifx_GTM_DXINCON_Bits.IN11 */
#define IFX_GTM_DXINCON_IN11_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DXINCON_Bits.IN11 */
#define IFX_GTM_DXINCON_IN11_OFF (9u)

/** \brief  Length for Ifx_GTM_DXINCON_Bits.IN12 */
#define IFX_GTM_DXINCON_IN12_LEN (1u)

/** \brief  Mask for Ifx_GTM_DXINCON_Bits.IN12 */
#define IFX_GTM_DXINCON_IN12_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DXINCON_Bits.IN12 */
#define IFX_GTM_DXINCON_IN12_OFF (10u)

/** \brief  Length for Ifx_GTM_DXOUTCON_Bits.OUT00 */
#define IFX_GTM_DXOUTCON_OUT00_LEN (1u)

/** \brief  Mask for Ifx_GTM_DXOUTCON_Bits.OUT00 */
#define IFX_GTM_DXOUTCON_OUT00_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DXOUTCON_Bits.OUT00 */
#define IFX_GTM_DXOUTCON_OUT00_OFF (0u)

/** \brief  Length for Ifx_GTM_DXOUTCON_Bits.OUT01 */
#define IFX_GTM_DXOUTCON_OUT01_LEN (1u)

/** \brief  Mask for Ifx_GTM_DXOUTCON_Bits.OUT01 */
#define IFX_GTM_DXOUTCON_OUT01_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DXOUTCON_Bits.OUT01 */
#define IFX_GTM_DXOUTCON_OUT01_OFF (1u)

/** \brief  Length for Ifx_GTM_DXOUTCON_Bits.OUT02 */
#define IFX_GTM_DXOUTCON_OUT02_LEN (1u)

/** \brief  Mask for Ifx_GTM_DXOUTCON_Bits.OUT02 */
#define IFX_GTM_DXOUTCON_OUT02_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DXOUTCON_Bits.OUT02 */
#define IFX_GTM_DXOUTCON_OUT02_OFF (2u)

/** \brief  Length for Ifx_GTM_DXOUTCON_Bits.OUT10 */
#define IFX_GTM_DXOUTCON_OUT10_LEN (1u)

/** \brief  Mask for Ifx_GTM_DXOUTCON_Bits.OUT10 */
#define IFX_GTM_DXOUTCON_OUT10_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DXOUTCON_Bits.OUT10 */
#define IFX_GTM_DXOUTCON_OUT10_OFF (8u)

/** \brief  Length for Ifx_GTM_DXOUTCON_Bits.OUT11 */
#define IFX_GTM_DXOUTCON_OUT11_LEN (1u)

/** \brief  Mask for Ifx_GTM_DXOUTCON_Bits.OUT11 */
#define IFX_GTM_DXOUTCON_OUT11_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DXOUTCON_Bits.OUT11 */
#define IFX_GTM_DXOUTCON_OUT11_OFF (9u)

/** \brief  Length for Ifx_GTM_DXOUTCON_Bits.OUT12 */
#define IFX_GTM_DXOUTCON_OUT12_LEN (1u)

/** \brief  Mask for Ifx_GTM_DXOUTCON_Bits.OUT12 */
#define IFX_GTM_DXOUTCON_OUT12_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_DXOUTCON_Bits.OUT12 */
#define IFX_GTM_DXOUTCON_OUT12_OFF (10u)

/** \brief  Length for Ifx_GTM_EIRQ_EN_Bits.AEI_IM_ADDR_EIRQ_EN */
#define IFX_GTM_EIRQ_EN_AEI_IM_ADDR_EIRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_EIRQ_EN_Bits.AEI_IM_ADDR_EIRQ_EN */
#define IFX_GTM_EIRQ_EN_AEI_IM_ADDR_EIRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_EIRQ_EN_Bits.AEI_IM_ADDR_EIRQ_EN */
#define IFX_GTM_EIRQ_EN_AEI_IM_ADDR_EIRQ_EN_OFF (2u)

/** \brief  Length for Ifx_GTM_EIRQ_EN_Bits.AEI_TO_XPT_EIRQ_EN */
#define IFX_GTM_EIRQ_EN_AEI_TO_XPT_EIRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_EIRQ_EN_Bits.AEI_TO_XPT_EIRQ_EN */
#define IFX_GTM_EIRQ_EN_AEI_TO_XPT_EIRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_EIRQ_EN_Bits.AEI_TO_XPT_EIRQ_EN */
#define IFX_GTM_EIRQ_EN_AEI_TO_XPT_EIRQ_EN_OFF (0u)

/** \brief  Length for Ifx_GTM_EIRQ_EN_Bits.AEI_USP_ADDR_EIRQ_EN */
#define IFX_GTM_EIRQ_EN_AEI_USP_ADDR_EIRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_EIRQ_EN_Bits.AEI_USP_ADDR_EIRQ_EN */
#define IFX_GTM_EIRQ_EN_AEI_USP_ADDR_EIRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_EIRQ_EN_Bits.AEI_USP_ADDR_EIRQ_EN */
#define IFX_GTM_EIRQ_EN_AEI_USP_ADDR_EIRQ_EN_OFF (1u)

/** \brief  Length for Ifx_GTM_EIRQ_EN_Bits.AEI_USP_BE_EIRQ_EN */
#define IFX_GTM_EIRQ_EN_AEI_USP_BE_EIRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_EIRQ_EN_Bits.AEI_USP_BE_EIRQ_EN */
#define IFX_GTM_EIRQ_EN_AEI_USP_BE_EIRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_EIRQ_EN_Bits.AEI_USP_BE_EIRQ_EN */
#define IFX_GTM_EIRQ_EN_AEI_USP_BE_EIRQ_EN_OFF (3u)

/** \brief  Length for Ifx_GTM_F2A_ENABLE_Bits.STR0_EN */
#define IFX_GTM_F2A_ENABLE_STR0_EN_LEN (2u)

/** \brief  Mask for Ifx_GTM_F2A_ENABLE_Bits.STR0_EN */
#define IFX_GTM_F2A_ENABLE_STR0_EN_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_F2A_ENABLE_Bits.STR0_EN */
#define IFX_GTM_F2A_ENABLE_STR0_EN_OFF (0u)

/** \brief  Length for Ifx_GTM_F2A_ENABLE_Bits.STR1_EN */
#define IFX_GTM_F2A_ENABLE_STR1_EN_LEN (2u)

/** \brief  Mask for Ifx_GTM_F2A_ENABLE_Bits.STR1_EN */
#define IFX_GTM_F2A_ENABLE_STR1_EN_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_F2A_ENABLE_Bits.STR1_EN */
#define IFX_GTM_F2A_ENABLE_STR1_EN_OFF (2u)

/** \brief  Length for Ifx_GTM_F2A_ENABLE_Bits.STR2_EN */
#define IFX_GTM_F2A_ENABLE_STR2_EN_LEN (2u)

/** \brief  Mask for Ifx_GTM_F2A_ENABLE_Bits.STR2_EN */
#define IFX_GTM_F2A_ENABLE_STR2_EN_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_F2A_ENABLE_Bits.STR2_EN */
#define IFX_GTM_F2A_ENABLE_STR2_EN_OFF (4u)

/** \brief  Length for Ifx_GTM_F2A_ENABLE_Bits.STR3_EN */
#define IFX_GTM_F2A_ENABLE_STR3_EN_LEN (2u)

/** \brief  Mask for Ifx_GTM_F2A_ENABLE_Bits.STR3_EN */
#define IFX_GTM_F2A_ENABLE_STR3_EN_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_F2A_ENABLE_Bits.STR3_EN */
#define IFX_GTM_F2A_ENABLE_STR3_EN_OFF (6u)

/** \brief  Length for Ifx_GTM_F2A_ENABLE_Bits.STR4_EN */
#define IFX_GTM_F2A_ENABLE_STR4_EN_LEN (2u)

/** \brief  Mask for Ifx_GTM_F2A_ENABLE_Bits.STR4_EN */
#define IFX_GTM_F2A_ENABLE_STR4_EN_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_F2A_ENABLE_Bits.STR4_EN */
#define IFX_GTM_F2A_ENABLE_STR4_EN_OFF (8u)

/** \brief  Length for Ifx_GTM_F2A_ENABLE_Bits.STR5_EN */
#define IFX_GTM_F2A_ENABLE_STR5_EN_LEN (2u)

/** \brief  Mask for Ifx_GTM_F2A_ENABLE_Bits.STR5_EN */
#define IFX_GTM_F2A_ENABLE_STR5_EN_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_F2A_ENABLE_Bits.STR5_EN */
#define IFX_GTM_F2A_ENABLE_STR5_EN_OFF (10u)

/** \brief  Length for Ifx_GTM_F2A_ENABLE_Bits.STR6_EN */
#define IFX_GTM_F2A_ENABLE_STR6_EN_LEN (2u)

/** \brief  Mask for Ifx_GTM_F2A_ENABLE_Bits.STR6_EN */
#define IFX_GTM_F2A_ENABLE_STR6_EN_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_F2A_ENABLE_Bits.STR6_EN */
#define IFX_GTM_F2A_ENABLE_STR6_EN_OFF (12u)

/** \brief  Length for Ifx_GTM_F2A_ENABLE_Bits.STR7_EN */
#define IFX_GTM_F2A_ENABLE_STR7_EN_LEN (2u)

/** \brief  Mask for Ifx_GTM_F2A_ENABLE_Bits.STR7_EN */
#define IFX_GTM_F2A_ENABLE_STR7_EN_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_F2A_ENABLE_Bits.STR7_EN */
#define IFX_GTM_F2A_ENABLE_STR7_EN_OFF (14u)

/** \brief  Length for Ifx_GTM_F2A_RD_CH_ARU_RD_FIFO_Bits.ADDR */
#define IFX_GTM_F2A_RD_CH_ARU_RD_FIFO_ADDR_LEN (9u)

/** \brief  Mask for Ifx_GTM_F2A_RD_CH_ARU_RD_FIFO_Bits.ADDR */
#define IFX_GTM_F2A_RD_CH_ARU_RD_FIFO_ADDR_MSK (0x1ffu)

/** \brief  Offset for Ifx_GTM_F2A_RD_CH_ARU_RD_FIFO_Bits.ADDR */
#define IFX_GTM_F2A_RD_CH_ARU_RD_FIFO_ADDR_OFF (0u)

/** \brief  Length for Ifx_GTM_F2A_STR_CH_STR_CFG_Bits.DIR */
#define IFX_GTM_F2A_STR_CH_STR_CFG_DIR_LEN (1u)

/** \brief  Mask for Ifx_GTM_F2A_STR_CH_STR_CFG_Bits.DIR */
#define IFX_GTM_F2A_STR_CH_STR_CFG_DIR_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_F2A_STR_CH_STR_CFG_Bits.DIR */
#define IFX_GTM_F2A_STR_CH_STR_CFG_DIR_OFF (18u)

/** \brief  Length for Ifx_GTM_F2A_STR_CH_STR_CFG_Bits.TMODE */
#define IFX_GTM_F2A_STR_CH_STR_CFG_TMODE_LEN (2u)

/** \brief  Mask for Ifx_GTM_F2A_STR_CH_STR_CFG_Bits.TMODE */
#define IFX_GTM_F2A_STR_CH_STR_CFG_TMODE_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_F2A_STR_CH_STR_CFG_Bits.TMODE */
#define IFX_GTM_F2A_STR_CH_STR_CFG_TMODE_OFF (16u)

/** \brief  Length for Ifx_GTM_FIFO_CH_CTRL_Bits.FLUSH */
#define IFX_GTM_FIFO_CH_CTRL_FLUSH_LEN (1u)

/** \brief  Mask for Ifx_GTM_FIFO_CH_CTRL_Bits.FLUSH */
#define IFX_GTM_FIFO_CH_CTRL_FLUSH_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_FIFO_CH_CTRL_Bits.FLUSH */
#define IFX_GTM_FIFO_CH_CTRL_FLUSH_OFF (2u)

/** \brief  Length for Ifx_GTM_FIFO_CH_CTRL_Bits.RAP */
#define IFX_GTM_FIFO_CH_CTRL_RAP_LEN (1u)

/** \brief  Mask for Ifx_GTM_FIFO_CH_CTRL_Bits.RAP */
#define IFX_GTM_FIFO_CH_CTRL_RAP_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_FIFO_CH_CTRL_Bits.RAP */
#define IFX_GTM_FIFO_CH_CTRL_RAP_OFF (1u)

/** \brief  Length for Ifx_GTM_FIFO_CH_CTRL_Bits.RBM */
#define IFX_GTM_FIFO_CH_CTRL_RBM_LEN (1u)

/** \brief  Mask for Ifx_GTM_FIFO_CH_CTRL_Bits.RBM */
#define IFX_GTM_FIFO_CH_CTRL_RBM_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_FIFO_CH_CTRL_Bits.RBM */
#define IFX_GTM_FIFO_CH_CTRL_RBM_OFF (0u)

/** \brief  Length for Ifx_GTM_FIFO_CH_CTRL_Bits.WULOCK */
#define IFX_GTM_FIFO_CH_CTRL_WULOCK_LEN (1u)

/** \brief  Mask for Ifx_GTM_FIFO_CH_CTRL_Bits.WULOCK */
#define IFX_GTM_FIFO_CH_CTRL_WULOCK_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_FIFO_CH_CTRL_Bits.WULOCK */
#define IFX_GTM_FIFO_CH_CTRL_WULOCK_OFF (3u)

/** \brief  Length for Ifx_GTM_FIFO_CH_EIRQ_EN_Bits.FIFO_EMPTY_EIRQ_EN */
#define IFX_GTM_FIFO_CH_EIRQ_EN_FIFO_EMPTY_EIRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_FIFO_CH_EIRQ_EN_Bits.FIFO_EMPTY_EIRQ_EN */
#define IFX_GTM_FIFO_CH_EIRQ_EN_FIFO_EMPTY_EIRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_FIFO_CH_EIRQ_EN_Bits.FIFO_EMPTY_EIRQ_EN */
#define IFX_GTM_FIFO_CH_EIRQ_EN_FIFO_EMPTY_EIRQ_EN_OFF (0u)

/** \brief  Length for Ifx_GTM_FIFO_CH_EIRQ_EN_Bits.FIFO_FULL_EIRQ_EN */
#define IFX_GTM_FIFO_CH_EIRQ_EN_FIFO_FULL_EIRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_FIFO_CH_EIRQ_EN_Bits.FIFO_FULL_EIRQ_EN */
#define IFX_GTM_FIFO_CH_EIRQ_EN_FIFO_FULL_EIRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_FIFO_CH_EIRQ_EN_Bits.FIFO_FULL_EIRQ_EN */
#define IFX_GTM_FIFO_CH_EIRQ_EN_FIFO_FULL_EIRQ_EN_OFF (1u)

/** \brief  Length for Ifx_GTM_FIFO_CH_EIRQ_EN_Bits.FIFO_LWM_EIRQ_EN */
#define IFX_GTM_FIFO_CH_EIRQ_EN_FIFO_LWM_EIRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_FIFO_CH_EIRQ_EN_Bits.FIFO_LWM_EIRQ_EN */
#define IFX_GTM_FIFO_CH_EIRQ_EN_FIFO_LWM_EIRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_FIFO_CH_EIRQ_EN_Bits.FIFO_LWM_EIRQ_EN */
#define IFX_GTM_FIFO_CH_EIRQ_EN_FIFO_LWM_EIRQ_EN_OFF (2u)

/** \brief  Length for Ifx_GTM_FIFO_CH_EIRQ_EN_Bits.FIFO_UWM_EIRQ_EN */
#define IFX_GTM_FIFO_CH_EIRQ_EN_FIFO_UWM_EIRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_FIFO_CH_EIRQ_EN_Bits.FIFO_UWM_EIRQ_EN */
#define IFX_GTM_FIFO_CH_EIRQ_EN_FIFO_UWM_EIRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_FIFO_CH_EIRQ_EN_Bits.FIFO_UWM_EIRQ_EN */
#define IFX_GTM_FIFO_CH_EIRQ_EN_FIFO_UWM_EIRQ_EN_OFF (3u)

/** \brief  Length for Ifx_GTM_FIFO_CH_EIRQ_EN_Bits.Reserved */
#define IFX_GTM_FIFO_CH_EIRQ_EN_RESERVED_LEN (28u)

/** \brief  Mask for Ifx_GTM_FIFO_CH_EIRQ_EN_Bits.Reserved */
#define IFX_GTM_FIFO_CH_EIRQ_EN_RESERVED_MSK (0xfffffffu)

/** \brief  Offset for Ifx_GTM_FIFO_CH_EIRQ_EN_Bits.Reserved */
#define IFX_GTM_FIFO_CH_EIRQ_EN_RESERVED_OFF (4u)

/** \brief  Length for Ifx_GTM_FIFO_CH_END_ADDR_Bits.ADDR */
#define IFX_GTM_FIFO_CH_END_ADDR_ADDR_LEN (10u)

/** \brief  Mask for Ifx_GTM_FIFO_CH_END_ADDR_Bits.ADDR */
#define IFX_GTM_FIFO_CH_END_ADDR_ADDR_MSK (0x3ffu)

/** \brief  Offset for Ifx_GTM_FIFO_CH_END_ADDR_Bits.ADDR */
#define IFX_GTM_FIFO_CH_END_ADDR_ADDR_OFF (0u)

/** \brief  Length for Ifx_GTM_FIFO_CH_FILL_LEVEL_Bits.LEVEL */
#define IFX_GTM_FIFO_CH_FILL_LEVEL_LEVEL_LEN (11u)

/** \brief  Mask for Ifx_GTM_FIFO_CH_FILL_LEVEL_Bits.LEVEL */
#define IFX_GTM_FIFO_CH_FILL_LEVEL_LEVEL_MSK (0x7ffu)

/** \brief  Offset for Ifx_GTM_FIFO_CH_FILL_LEVEL_Bits.LEVEL */
#define IFX_GTM_FIFO_CH_FILL_LEVEL_LEVEL_OFF (0u)

/** \brief  Length for Ifx_GTM_FIFO_CH_IRQ_EN_Bits.FIFO_EMPTY_IRQ_EN */
#define IFX_GTM_FIFO_CH_IRQ_EN_FIFO_EMPTY_IRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_FIFO_CH_IRQ_EN_Bits.FIFO_EMPTY_IRQ_EN */
#define IFX_GTM_FIFO_CH_IRQ_EN_FIFO_EMPTY_IRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_FIFO_CH_IRQ_EN_Bits.FIFO_EMPTY_IRQ_EN */
#define IFX_GTM_FIFO_CH_IRQ_EN_FIFO_EMPTY_IRQ_EN_OFF (0u)

/** \brief  Length for Ifx_GTM_FIFO_CH_IRQ_EN_Bits.FIFO_FULL_IRQ_EN */
#define IFX_GTM_FIFO_CH_IRQ_EN_FIFO_FULL_IRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_FIFO_CH_IRQ_EN_Bits.FIFO_FULL_IRQ_EN */
#define IFX_GTM_FIFO_CH_IRQ_EN_FIFO_FULL_IRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_FIFO_CH_IRQ_EN_Bits.FIFO_FULL_IRQ_EN */
#define IFX_GTM_FIFO_CH_IRQ_EN_FIFO_FULL_IRQ_EN_OFF (1u)

/** \brief  Length for Ifx_GTM_FIFO_CH_IRQ_EN_Bits.FIFO_LWM_IRQ_EN */
#define IFX_GTM_FIFO_CH_IRQ_EN_FIFO_LWM_IRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_FIFO_CH_IRQ_EN_Bits.FIFO_LWM_IRQ_EN */
#define IFX_GTM_FIFO_CH_IRQ_EN_FIFO_LWM_IRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_FIFO_CH_IRQ_EN_Bits.FIFO_LWM_IRQ_EN */
#define IFX_GTM_FIFO_CH_IRQ_EN_FIFO_LWM_IRQ_EN_OFF (2u)

/** \brief  Length for Ifx_GTM_FIFO_CH_IRQ_EN_Bits.FIFO_UWM_IRQ_EN */
#define IFX_GTM_FIFO_CH_IRQ_EN_FIFO_UWM_IRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_FIFO_CH_IRQ_EN_Bits.FIFO_UWM_IRQ_EN */
#define IFX_GTM_FIFO_CH_IRQ_EN_FIFO_UWM_IRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_FIFO_CH_IRQ_EN_Bits.FIFO_UWM_IRQ_EN */
#define IFX_GTM_FIFO_CH_IRQ_EN_FIFO_UWM_IRQ_EN_OFF (3u)

/** \brief  Length for Ifx_GTM_FIFO_CH_IRQ_FORCINT_Bits.TRG_FIFO_EMPTY */
#define IFX_GTM_FIFO_CH_IRQ_FORCINT_TRG_FIFO_EMPTY_LEN (1u)

/** \brief  Mask for Ifx_GTM_FIFO_CH_IRQ_FORCINT_Bits.TRG_FIFO_EMPTY */
#define IFX_GTM_FIFO_CH_IRQ_FORCINT_TRG_FIFO_EMPTY_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_FIFO_CH_IRQ_FORCINT_Bits.TRG_FIFO_EMPTY */
#define IFX_GTM_FIFO_CH_IRQ_FORCINT_TRG_FIFO_EMPTY_OFF (0u)

/** \brief  Length for Ifx_GTM_FIFO_CH_IRQ_FORCINT_Bits.TRG_FIFO_FULL */
#define IFX_GTM_FIFO_CH_IRQ_FORCINT_TRG_FIFO_FULL_LEN (1u)

/** \brief  Mask for Ifx_GTM_FIFO_CH_IRQ_FORCINT_Bits.TRG_FIFO_FULL */
#define IFX_GTM_FIFO_CH_IRQ_FORCINT_TRG_FIFO_FULL_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_FIFO_CH_IRQ_FORCINT_Bits.TRG_FIFO_FULL */
#define IFX_GTM_FIFO_CH_IRQ_FORCINT_TRG_FIFO_FULL_OFF (1u)

/** \brief  Length for Ifx_GTM_FIFO_CH_IRQ_FORCINT_Bits.TRG_FIFO_LWM */
#define IFX_GTM_FIFO_CH_IRQ_FORCINT_TRG_FIFO_LWM_LEN (1u)

/** \brief  Mask for Ifx_GTM_FIFO_CH_IRQ_FORCINT_Bits.TRG_FIFO_LWM */
#define IFX_GTM_FIFO_CH_IRQ_FORCINT_TRG_FIFO_LWM_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_FIFO_CH_IRQ_FORCINT_Bits.TRG_FIFO_LWM */
#define IFX_GTM_FIFO_CH_IRQ_FORCINT_TRG_FIFO_LWM_OFF (2u)

/** \brief  Length for Ifx_GTM_FIFO_CH_IRQ_FORCINT_Bits.TRG_FIFO_UWM */
#define IFX_GTM_FIFO_CH_IRQ_FORCINT_TRG_FIFO_UWM_LEN (1u)

/** \brief  Mask for Ifx_GTM_FIFO_CH_IRQ_FORCINT_Bits.TRG_FIFO_UWM */
#define IFX_GTM_FIFO_CH_IRQ_FORCINT_TRG_FIFO_UWM_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_FIFO_CH_IRQ_FORCINT_Bits.TRG_FIFO_UWM */
#define IFX_GTM_FIFO_CH_IRQ_FORCINT_TRG_FIFO_UWM_OFF (3u)

/** \brief  Length for Ifx_GTM_FIFO_CH_IRQ_MODE_Bits.DMA_HYST_DIR */
#define IFX_GTM_FIFO_CH_IRQ_MODE_DMA_HYST_DIR_LEN (1u)

/** \brief  Mask for Ifx_GTM_FIFO_CH_IRQ_MODE_Bits.DMA_HYST_DIR */
#define IFX_GTM_FIFO_CH_IRQ_MODE_DMA_HYST_DIR_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_FIFO_CH_IRQ_MODE_Bits.DMA_HYST_DIR */
#define IFX_GTM_FIFO_CH_IRQ_MODE_DMA_HYST_DIR_OFF (3u)

/** \brief  Length for Ifx_GTM_FIFO_CH_IRQ_MODE_Bits.DMA_HYSTERESIS */
#define IFX_GTM_FIFO_CH_IRQ_MODE_DMA_HYSTERESIS_LEN (1u)

/** \brief  Mask for Ifx_GTM_FIFO_CH_IRQ_MODE_Bits.DMA_HYSTERESIS */
#define IFX_GTM_FIFO_CH_IRQ_MODE_DMA_HYSTERESIS_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_FIFO_CH_IRQ_MODE_Bits.DMA_HYSTERESIS */
#define IFX_GTM_FIFO_CH_IRQ_MODE_DMA_HYSTERESIS_OFF (2u)

/** \brief  Length for Ifx_GTM_FIFO_CH_IRQ_MODE_Bits.IRQ_MODE */
#define IFX_GTM_FIFO_CH_IRQ_MODE_IRQ_MODE_LEN (2u)

/** \brief  Mask for Ifx_GTM_FIFO_CH_IRQ_MODE_Bits.IRQ_MODE */
#define IFX_GTM_FIFO_CH_IRQ_MODE_IRQ_MODE_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_FIFO_CH_IRQ_MODE_Bits.IRQ_MODE */
#define IFX_GTM_FIFO_CH_IRQ_MODE_IRQ_MODE_OFF (0u)

/** \brief  Length for Ifx_GTM_FIFO_CH_IRQ_NOTIFY_Bits.FIFO_EMPTY */
#define IFX_GTM_FIFO_CH_IRQ_NOTIFY_FIFO_EMPTY_LEN (1u)

/** \brief  Mask for Ifx_GTM_FIFO_CH_IRQ_NOTIFY_Bits.FIFO_EMPTY */
#define IFX_GTM_FIFO_CH_IRQ_NOTIFY_FIFO_EMPTY_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_FIFO_CH_IRQ_NOTIFY_Bits.FIFO_EMPTY */
#define IFX_GTM_FIFO_CH_IRQ_NOTIFY_FIFO_EMPTY_OFF (0u)

/** \brief  Length for Ifx_GTM_FIFO_CH_IRQ_NOTIFY_Bits.FIFO_FULL */
#define IFX_GTM_FIFO_CH_IRQ_NOTIFY_FIFO_FULL_LEN (1u)

/** \brief  Mask for Ifx_GTM_FIFO_CH_IRQ_NOTIFY_Bits.FIFO_FULL */
#define IFX_GTM_FIFO_CH_IRQ_NOTIFY_FIFO_FULL_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_FIFO_CH_IRQ_NOTIFY_Bits.FIFO_FULL */
#define IFX_GTM_FIFO_CH_IRQ_NOTIFY_FIFO_FULL_OFF (1u)

/** \brief  Length for Ifx_GTM_FIFO_CH_IRQ_NOTIFY_Bits.FIFO_LWM */
#define IFX_GTM_FIFO_CH_IRQ_NOTIFY_FIFO_LWM_LEN (1u)

/** \brief  Mask for Ifx_GTM_FIFO_CH_IRQ_NOTIFY_Bits.FIFO_LWM */
#define IFX_GTM_FIFO_CH_IRQ_NOTIFY_FIFO_LWM_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_FIFO_CH_IRQ_NOTIFY_Bits.FIFO_LWM */
#define IFX_GTM_FIFO_CH_IRQ_NOTIFY_FIFO_LWM_OFF (2u)

/** \brief  Length for Ifx_GTM_FIFO_CH_IRQ_NOTIFY_Bits.FIFO_UWM */
#define IFX_GTM_FIFO_CH_IRQ_NOTIFY_FIFO_UWM_LEN (1u)

/** \brief  Mask for Ifx_GTM_FIFO_CH_IRQ_NOTIFY_Bits.FIFO_UWM */
#define IFX_GTM_FIFO_CH_IRQ_NOTIFY_FIFO_UWM_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_FIFO_CH_IRQ_NOTIFY_Bits.FIFO_UWM */
#define IFX_GTM_FIFO_CH_IRQ_NOTIFY_FIFO_UWM_OFF (3u)

/** \brief  Length for Ifx_GTM_FIFO_CH_LOWER_WM_Bits.ADDR */
#define IFX_GTM_FIFO_CH_LOWER_WM_ADDR_LEN (10u)

/** \brief  Mask for Ifx_GTM_FIFO_CH_LOWER_WM_Bits.ADDR */
#define IFX_GTM_FIFO_CH_LOWER_WM_ADDR_MSK (0x3ffu)

/** \brief  Offset for Ifx_GTM_FIFO_CH_LOWER_WM_Bits.ADDR */
#define IFX_GTM_FIFO_CH_LOWER_WM_ADDR_OFF (0u)

/** \brief  Length for Ifx_GTM_FIFO_CH_RD_PTR_Bits.ADDR */
#define IFX_GTM_FIFO_CH_RD_PTR_ADDR_LEN (10u)

/** \brief  Mask for Ifx_GTM_FIFO_CH_RD_PTR_Bits.ADDR */
#define IFX_GTM_FIFO_CH_RD_PTR_ADDR_MSK (0x3ffu)

/** \brief  Offset for Ifx_GTM_FIFO_CH_RD_PTR_Bits.ADDR */
#define IFX_GTM_FIFO_CH_RD_PTR_ADDR_OFF (0u)

/** \brief  Length for Ifx_GTM_FIFO_CH_START_ADDR_Bits.ADDR */
#define IFX_GTM_FIFO_CH_START_ADDR_ADDR_LEN (10u)

/** \brief  Mask for Ifx_GTM_FIFO_CH_START_ADDR_Bits.ADDR */
#define IFX_GTM_FIFO_CH_START_ADDR_ADDR_MSK (0x3ffu)

/** \brief  Offset for Ifx_GTM_FIFO_CH_START_ADDR_Bits.ADDR */
#define IFX_GTM_FIFO_CH_START_ADDR_ADDR_OFF (0u)

/** \brief  Length for Ifx_GTM_FIFO_CH_STATUS_Bits.EMPTY */
#define IFX_GTM_FIFO_CH_STATUS_EMPTY_LEN (1u)

/** \brief  Mask for Ifx_GTM_FIFO_CH_STATUS_Bits.EMPTY */
#define IFX_GTM_FIFO_CH_STATUS_EMPTY_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_FIFO_CH_STATUS_Bits.EMPTY */
#define IFX_GTM_FIFO_CH_STATUS_EMPTY_OFF (0u)

/** \brief  Length for Ifx_GTM_FIFO_CH_STATUS_Bits.FULL */
#define IFX_GTM_FIFO_CH_STATUS_FULL_LEN (1u)

/** \brief  Mask for Ifx_GTM_FIFO_CH_STATUS_Bits.FULL */
#define IFX_GTM_FIFO_CH_STATUS_FULL_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_FIFO_CH_STATUS_Bits.FULL */
#define IFX_GTM_FIFO_CH_STATUS_FULL_OFF (1u)

/** \brief  Length for Ifx_GTM_FIFO_CH_STATUS_Bits.LOW_WM */
#define IFX_GTM_FIFO_CH_STATUS_LOW_WM_LEN (1u)

/** \brief  Mask for Ifx_GTM_FIFO_CH_STATUS_Bits.LOW_WM */
#define IFX_GTM_FIFO_CH_STATUS_LOW_WM_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_FIFO_CH_STATUS_Bits.LOW_WM */
#define IFX_GTM_FIFO_CH_STATUS_LOW_WM_OFF (2u)

/** \brief  Length for Ifx_GTM_FIFO_CH_STATUS_Bits.UP_WM */
#define IFX_GTM_FIFO_CH_STATUS_UP_WM_LEN (1u)

/** \brief  Mask for Ifx_GTM_FIFO_CH_STATUS_Bits.UP_WM */
#define IFX_GTM_FIFO_CH_STATUS_UP_WM_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_FIFO_CH_STATUS_Bits.UP_WM */
#define IFX_GTM_FIFO_CH_STATUS_UP_WM_OFF (3u)

/** \brief  Length for Ifx_GTM_FIFO_CH_UPPER_WM_Bits.ADDR */
#define IFX_GTM_FIFO_CH_UPPER_WM_ADDR_LEN (10u)

/** \brief  Mask for Ifx_GTM_FIFO_CH_UPPER_WM_Bits.ADDR */
#define IFX_GTM_FIFO_CH_UPPER_WM_ADDR_MSK (0x3ffu)

/** \brief  Offset for Ifx_GTM_FIFO_CH_UPPER_WM_Bits.ADDR */
#define IFX_GTM_FIFO_CH_UPPER_WM_ADDR_OFF (0u)

/** \brief  Length for Ifx_GTM_FIFO_CH_WR_PTR_Bits.ADDR */
#define IFX_GTM_FIFO_CH_WR_PTR_ADDR_LEN (10u)

/** \brief  Mask for Ifx_GTM_FIFO_CH_WR_PTR_Bits.ADDR */
#define IFX_GTM_FIFO_CH_WR_PTR_ADDR_MSK (0x3ffu)

/** \brief  Offset for Ifx_GTM_FIFO_CH_WR_PTR_Bits.ADDR */
#define IFX_GTM_FIFO_CH_WR_PTR_ADDR_OFF (0u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_0_Bits.AEI_IRQ */
#define IFX_GTM_ICM_IRQG_0_AEI_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_0_Bits.AEI_IRQ */
#define IFX_GTM_ICM_IRQG_0_AEI_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_0_Bits.AEI_IRQ */
#define IFX_GTM_ICM_IRQG_0_AEI_IRQ_OFF (4u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_0_Bits.ARU_ACC_ACK_IRQ */
#define IFX_GTM_ICM_IRQG_0_ARU_ACC_ACK_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_0_Bits.ARU_ACC_ACK_IRQ */
#define IFX_GTM_ICM_IRQG_0_ARU_ACC_ACK_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_0_Bits.ARU_ACC_ACK_IRQ */
#define IFX_GTM_ICM_IRQG_0_ARU_ACC_ACK_IRQ_OFF (2u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_0_Bits.ARU_NEW_DATA0_IRQ */
#define IFX_GTM_ICM_IRQG_0_ARU_NEW_DATA0_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_0_Bits.ARU_NEW_DATA0_IRQ */
#define IFX_GTM_ICM_IRQG_0_ARU_NEW_DATA0_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_0_Bits.ARU_NEW_DATA0_IRQ */
#define IFX_GTM_ICM_IRQG_0_ARU_NEW_DATA0_IRQ_OFF (0u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_0_Bits.ARU_NEW_DATA1_IRQ */
#define IFX_GTM_ICM_IRQG_0_ARU_NEW_DATA1_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_0_Bits.ARU_NEW_DATA1_IRQ */
#define IFX_GTM_ICM_IRQG_0_ARU_NEW_DATA1_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_0_Bits.ARU_NEW_DATA1_IRQ */
#define IFX_GTM_ICM_IRQG_0_ARU_NEW_DATA1_IRQ_OFF (1u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_0_Bits.BRC_IRQ */
#define IFX_GTM_ICM_IRQG_0_BRC_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_0_Bits.BRC_IRQ */
#define IFX_GTM_ICM_IRQG_0_BRC_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_0_Bits.BRC_IRQ */
#define IFX_GTM_ICM_IRQG_0_BRC_IRQ_OFF (3u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_0_Bits.CMP_IRQ */
#define IFX_GTM_ICM_IRQG_0_CMP_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_0_Bits.CMP_IRQ */
#define IFX_GTM_ICM_IRQG_0_CMP_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_0_Bits.CMP_IRQ */
#define IFX_GTM_ICM_IRQG_0_CMP_IRQ_OFF (5u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_0_Bits.PSM0_CH0_IRQ */
#define IFX_GTM_ICM_IRQG_0_PSM0_CH0_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_0_Bits.PSM0_CH0_IRQ */
#define IFX_GTM_ICM_IRQG_0_PSM0_CH0_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_0_Bits.PSM0_CH0_IRQ */
#define IFX_GTM_ICM_IRQG_0_PSM0_CH0_IRQ_OFF (16u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_0_Bits.PSM0_CH1_IRQ */
#define IFX_GTM_ICM_IRQG_0_PSM0_CH1_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_0_Bits.PSM0_CH1_IRQ */
#define IFX_GTM_ICM_IRQG_0_PSM0_CH1_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_0_Bits.PSM0_CH1_IRQ */
#define IFX_GTM_ICM_IRQG_0_PSM0_CH1_IRQ_OFF (17u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_0_Bits.PSM0_CH2_IRQ */
#define IFX_GTM_ICM_IRQG_0_PSM0_CH2_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_0_Bits.PSM0_CH2_IRQ */
#define IFX_GTM_ICM_IRQG_0_PSM0_CH2_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_0_Bits.PSM0_CH2_IRQ */
#define IFX_GTM_ICM_IRQG_0_PSM0_CH2_IRQ_OFF (18u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_0_Bits.PSM0_CH3_IRQ */
#define IFX_GTM_ICM_IRQG_0_PSM0_CH3_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_0_Bits.PSM0_CH3_IRQ */
#define IFX_GTM_ICM_IRQG_0_PSM0_CH3_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_0_Bits.PSM0_CH3_IRQ */
#define IFX_GTM_ICM_IRQG_0_PSM0_CH3_IRQ_OFF (19u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_0_Bits.PSM0_CH4_IRQ */
#define IFX_GTM_ICM_IRQG_0_PSM0_CH4_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_0_Bits.PSM0_CH4_IRQ */
#define IFX_GTM_ICM_IRQG_0_PSM0_CH4_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_0_Bits.PSM0_CH4_IRQ */
#define IFX_GTM_ICM_IRQG_0_PSM0_CH4_IRQ_OFF (20u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_0_Bits.PSM0_CH5_IRQ */
#define IFX_GTM_ICM_IRQG_0_PSM0_CH5_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_0_Bits.PSM0_CH5_IRQ */
#define IFX_GTM_ICM_IRQG_0_PSM0_CH5_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_0_Bits.PSM0_CH5_IRQ */
#define IFX_GTM_ICM_IRQG_0_PSM0_CH5_IRQ_OFF (21u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_0_Bits.PSM0_CH6_IRQ */
#define IFX_GTM_ICM_IRQG_0_PSM0_CH6_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_0_Bits.PSM0_CH6_IRQ */
#define IFX_GTM_ICM_IRQG_0_PSM0_CH6_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_0_Bits.PSM0_CH6_IRQ */
#define IFX_GTM_ICM_IRQG_0_PSM0_CH6_IRQ_OFF (22u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_0_Bits.PSM0_CH7_IRQ */
#define IFX_GTM_ICM_IRQG_0_PSM0_CH7_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_0_Bits.PSM0_CH7_IRQ */
#define IFX_GTM_ICM_IRQG_0_PSM0_CH7_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_0_Bits.PSM0_CH7_IRQ */
#define IFX_GTM_ICM_IRQG_0_PSM0_CH7_IRQ_OFF (23u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_0_Bits.SPE0_IRQ */
#define IFX_GTM_ICM_IRQG_0_SPE0_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_0_Bits.SPE0_IRQ */
#define IFX_GTM_ICM_IRQG_0_SPE0_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_0_Bits.SPE0_IRQ */
#define IFX_GTM_ICM_IRQG_0_SPE0_IRQ_OFF (6u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_0_Bits.SPE1_IRQ */
#define IFX_GTM_ICM_IRQG_0_SPE1_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_0_Bits.SPE1_IRQ */
#define IFX_GTM_ICM_IRQG_0_SPE1_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_0_Bits.SPE1_IRQ */
#define IFX_GTM_ICM_IRQG_0_SPE1_IRQ_OFF (7u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_CDIS_IRQ */
#define IFX_GTM_ICM_IRQG_1_DPLL_CDIS_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_CDIS_IRQ */
#define IFX_GTM_ICM_IRQG_1_DPLL_CDIS_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_CDIS_IRQ */
#define IFX_GTM_ICM_IRQG_1_DPLL_CDIS_IRQ_OFF (24u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_CDIT_IRQ */
#define IFX_GTM_ICM_IRQG_1_DPLL_CDIT_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_CDIT_IRQ */
#define IFX_GTM_ICM_IRQG_1_DPLL_CDIT_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_CDIT_IRQ */
#define IFX_GTM_ICM_IRQG_1_DPLL_CDIT_IRQ_OFF (23u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_DCG_IRQ */
#define IFX_GTM_ICM_IRQG_1_DPLL_DCG_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_DCG_IRQ */
#define IFX_GTM_ICM_IRQG_1_DPLL_DCG_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_DCG_IRQ */
#define IFX_GTM_ICM_IRQG_1_DPLL_DCG_IRQ_OFF (0u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_EDI_IRQ */
#define IFX_GTM_ICM_IRQG_1_DPLL_EDI_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_EDI_IRQ */
#define IFX_GTM_ICM_IRQG_1_DPLL_EDI_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_EDI_IRQ */
#define IFX_GTM_ICM_IRQG_1_DPLL_EDI_IRQ_OFF (1u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_EI_IRQ */
#define IFX_GTM_ICM_IRQG_1_DPLL_EI_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_EI_IRQ */
#define IFX_GTM_ICM_IRQG_1_DPLL_EI_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_EI_IRQ */
#define IFX_GTM_ICM_IRQG_1_DPLL_EI_IRQ_OFF (15u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_GL2I_IRQ */
#define IFX_GTM_ICM_IRQG_1_DPLL_GL2I_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_GL2I_IRQ */
#define IFX_GTM_ICM_IRQG_1_DPLL_GL2I_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_GL2I_IRQ */
#define IFX_GTM_ICM_IRQG_1_DPLL_GL2I_IRQ_OFF (16u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_GLI_IRQ */
#define IFX_GTM_ICM_IRQG_1_DPLL_GLI_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_GLI_IRQ */
#define IFX_GTM_ICM_IRQG_1_DPLL_GLI_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_GLI_IRQ */
#define IFX_GTM_ICM_IRQG_1_DPLL_GLI_IRQ_OFF (13u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_LL2I_IRQ */
#define IFX_GTM_ICM_IRQG_1_DPLL_LL2I_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_LL2I_IRQ */
#define IFX_GTM_ICM_IRQG_1_DPLL_LL2I_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_LL2I_IRQ */
#define IFX_GTM_ICM_IRQG_1_DPLL_LL2I_IRQ_OFF (17u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_LLI_IRQ */
#define IFX_GTM_ICM_IRQG_1_DPLL_LLI_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_LLI_IRQ */
#define IFX_GTM_ICM_IRQG_1_DPLL_LLI_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_LLI_IRQ */
#define IFX_GTM_ICM_IRQG_1_DPLL_LLI_IRQ_OFF (14u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_MSI_IRQ */
#define IFX_GTM_ICM_IRQG_1_DPLL_MSI_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_MSI_IRQ */
#define IFX_GTM_ICM_IRQG_1_DPLL_MSI_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_MSI_IRQ */
#define IFX_GTM_ICM_IRQG_1_DPLL_MSI_IRQ_OFF (6u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_MTI_IRQ */
#define IFX_GTM_ICM_IRQG_1_DPLL_MTI_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_MTI_IRQ */
#define IFX_GTM_ICM_IRQG_1_DPLL_MTI_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_MTI_IRQ */
#define IFX_GTM_ICM_IRQG_1_DPLL_MTI_IRQ_OFF (7u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_PWI_IRQ */
#define IFX_GTM_ICM_IRQG_1_DPLL_PWI_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_PWI_IRQ */
#define IFX_GTM_ICM_IRQG_1_DPLL_PWI_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_PWI_IRQ */
#define IFX_GTM_ICM_IRQG_1_DPLL_PWI_IRQ_OFF (10u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_SAS_IRQ */
#define IFX_GTM_ICM_IRQG_1_DPLL_SAS_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_SAS_IRQ */
#define IFX_GTM_ICM_IRQG_1_DPLL_SAS_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_SAS_IRQ */
#define IFX_GTM_ICM_IRQG_1_DPLL_SAS_IRQ_OFF (8u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_SIS_IRQ */
#define IFX_GTM_ICM_IRQG_1_DPLL_SIS_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_SIS_IRQ */
#define IFX_GTM_ICM_IRQG_1_DPLL_SIS_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_SIS_IRQ */
#define IFX_GTM_ICM_IRQG_1_DPLL_SIS_IRQ_OFF (4u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_SORI_IRQ */
#define IFX_GTM_ICM_IRQG_1_DPLL_SORI_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_SORI_IRQ */
#define IFX_GTM_ICM_IRQG_1_DPLL_SORI_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_SORI_IRQ */
#define IFX_GTM_ICM_IRQG_1_DPLL_SORI_IRQ_OFF (26u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_TAS_IRQ */
#define IFX_GTM_ICM_IRQG_1_DPLL_TAS_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_TAS_IRQ */
#define IFX_GTM_ICM_IRQG_1_DPLL_TAS_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_TAS_IRQ */
#define IFX_GTM_ICM_IRQG_1_DPLL_TAS_IRQ_OFF (9u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_TAX_IRQ */
#define IFX_GTM_ICM_IRQG_1_DPLL_TAX_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_TAX_IRQ */
#define IFX_GTM_ICM_IRQG_1_DPLL_TAX_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_TAX_IRQ */
#define IFX_GTM_ICM_IRQG_1_DPLL_TAX_IRQ_OFF (3u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_TE0_IRQ */
#define IFX_GTM_ICM_IRQG_1_DPLL_TE0_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_TE0_IRQ */
#define IFX_GTM_ICM_IRQG_1_DPLL_TE0_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_TE0_IRQ */
#define IFX_GTM_ICM_IRQG_1_DPLL_TE0_IRQ_OFF (18u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_TE1_IRQ */
#define IFX_GTM_ICM_IRQG_1_DPLL_TE1_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_TE1_IRQ */
#define IFX_GTM_ICM_IRQG_1_DPLL_TE1_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_TE1_IRQ */
#define IFX_GTM_ICM_IRQG_1_DPLL_TE1_IRQ_OFF (19u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_TE2_IRQ */
#define IFX_GTM_ICM_IRQG_1_DPLL_TE2_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_TE2_IRQ */
#define IFX_GTM_ICM_IRQG_1_DPLL_TE2_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_TE2_IRQ */
#define IFX_GTM_ICM_IRQG_1_DPLL_TE2_IRQ_OFF (20u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_TE3_IRQ */
#define IFX_GTM_ICM_IRQG_1_DPLL_TE3_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_TE3_IRQ */
#define IFX_GTM_ICM_IRQG_1_DPLL_TE3_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_TE3_IRQ */
#define IFX_GTM_ICM_IRQG_1_DPLL_TE3_IRQ_OFF (21u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_TE4_IRQ */
#define IFX_GTM_ICM_IRQG_1_DPLL_TE4_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_TE4_IRQ */
#define IFX_GTM_ICM_IRQG_1_DPLL_TE4_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_TE4_IRQ */
#define IFX_GTM_ICM_IRQG_1_DPLL_TE4_IRQ_OFF (22u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_TIN_IRQ */
#define IFX_GTM_ICM_IRQG_1_DPLL_TIN_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_TIN_IRQ */
#define IFX_GTM_ICM_IRQG_1_DPLL_TIN_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_TIN_IRQ */
#define IFX_GTM_ICM_IRQG_1_DPLL_TIN_IRQ_OFF (2u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_TIS_IRQ */
#define IFX_GTM_ICM_IRQG_1_DPLL_TIS_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_TIS_IRQ */
#define IFX_GTM_ICM_IRQG_1_DPLL_TIS_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_TIS_IRQ */
#define IFX_GTM_ICM_IRQG_1_DPLL_TIS_IRQ_OFF (5u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_TORI_IRQ */
#define IFX_GTM_ICM_IRQG_1_DPLL_TORI_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_TORI_IRQ */
#define IFX_GTM_ICM_IRQG_1_DPLL_TORI_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_TORI_IRQ */
#define IFX_GTM_ICM_IRQG_1_DPLL_TORI_IRQ_OFF (25u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_W1I_IRQ */
#define IFX_GTM_ICM_IRQG_1_DPLL_W1I_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_W1I_IRQ */
#define IFX_GTM_ICM_IRQG_1_DPLL_W1I_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_W1I_IRQ */
#define IFX_GTM_ICM_IRQG_1_DPLL_W1I_IRQ_OFF (12u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_W2I_IRQ */
#define IFX_GTM_ICM_IRQG_1_DPLL_W2I_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_W2I_IRQ */
#define IFX_GTM_ICM_IRQG_1_DPLL_W2I_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_1_Bits.DPLL_W2I_IRQ */
#define IFX_GTM_ICM_IRQG_1_DPLL_W2I_IRQ_OFF (11u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_2_Bits.TIM0_CH0_IRQ */
#define IFX_GTM_ICM_IRQG_2_TIM0_CH0_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_2_Bits.TIM0_CH0_IRQ */
#define IFX_GTM_ICM_IRQG_2_TIM0_CH0_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_2_Bits.TIM0_CH0_IRQ */
#define IFX_GTM_ICM_IRQG_2_TIM0_CH0_IRQ_OFF (0u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_2_Bits.TIM0_CH1_IRQ */
#define IFX_GTM_ICM_IRQG_2_TIM0_CH1_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_2_Bits.TIM0_CH1_IRQ */
#define IFX_GTM_ICM_IRQG_2_TIM0_CH1_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_2_Bits.TIM0_CH1_IRQ */
#define IFX_GTM_ICM_IRQG_2_TIM0_CH1_IRQ_OFF (1u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_2_Bits.TIM0_CH2_IRQ */
#define IFX_GTM_ICM_IRQG_2_TIM0_CH2_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_2_Bits.TIM0_CH2_IRQ */
#define IFX_GTM_ICM_IRQG_2_TIM0_CH2_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_2_Bits.TIM0_CH2_IRQ */
#define IFX_GTM_ICM_IRQG_2_TIM0_CH2_IRQ_OFF (2u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_2_Bits.TIM0_CH3_IRQ */
#define IFX_GTM_ICM_IRQG_2_TIM0_CH3_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_2_Bits.TIM0_CH3_IRQ */
#define IFX_GTM_ICM_IRQG_2_TIM0_CH3_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_2_Bits.TIM0_CH3_IRQ */
#define IFX_GTM_ICM_IRQG_2_TIM0_CH3_IRQ_OFF (3u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_2_Bits.TIM0_CH4_IRQ */
#define IFX_GTM_ICM_IRQG_2_TIM0_CH4_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_2_Bits.TIM0_CH4_IRQ */
#define IFX_GTM_ICM_IRQG_2_TIM0_CH4_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_2_Bits.TIM0_CH4_IRQ */
#define IFX_GTM_ICM_IRQG_2_TIM0_CH4_IRQ_OFF (4u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_2_Bits.TIM0_CH5_IRQ */
#define IFX_GTM_ICM_IRQG_2_TIM0_CH5_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_2_Bits.TIM0_CH5_IRQ */
#define IFX_GTM_ICM_IRQG_2_TIM0_CH5_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_2_Bits.TIM0_CH5_IRQ */
#define IFX_GTM_ICM_IRQG_2_TIM0_CH5_IRQ_OFF (5u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_2_Bits.TIM0_CH6_IRQ */
#define IFX_GTM_ICM_IRQG_2_TIM0_CH6_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_2_Bits.TIM0_CH6_IRQ */
#define IFX_GTM_ICM_IRQG_2_TIM0_CH6_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_2_Bits.TIM0_CH6_IRQ */
#define IFX_GTM_ICM_IRQG_2_TIM0_CH6_IRQ_OFF (6u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_2_Bits.TIM0_CH7_IRQ */
#define IFX_GTM_ICM_IRQG_2_TIM0_CH7_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_2_Bits.TIM0_CH7_IRQ */
#define IFX_GTM_ICM_IRQG_2_TIM0_CH7_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_2_Bits.TIM0_CH7_IRQ */
#define IFX_GTM_ICM_IRQG_2_TIM0_CH7_IRQ_OFF (7u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_2_Bits.TIM1_CH0_IRQ */
#define IFX_GTM_ICM_IRQG_2_TIM1_CH0_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_2_Bits.TIM1_CH0_IRQ */
#define IFX_GTM_ICM_IRQG_2_TIM1_CH0_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_2_Bits.TIM1_CH0_IRQ */
#define IFX_GTM_ICM_IRQG_2_TIM1_CH0_IRQ_OFF (8u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_2_Bits.TIM1_CH1_IRQ */
#define IFX_GTM_ICM_IRQG_2_TIM1_CH1_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_2_Bits.TIM1_CH1_IRQ */
#define IFX_GTM_ICM_IRQG_2_TIM1_CH1_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_2_Bits.TIM1_CH1_IRQ */
#define IFX_GTM_ICM_IRQG_2_TIM1_CH1_IRQ_OFF (9u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_2_Bits.TIM1_CH2_IRQ */
#define IFX_GTM_ICM_IRQG_2_TIM1_CH2_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_2_Bits.TIM1_CH2_IRQ */
#define IFX_GTM_ICM_IRQG_2_TIM1_CH2_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_2_Bits.TIM1_CH2_IRQ */
#define IFX_GTM_ICM_IRQG_2_TIM1_CH2_IRQ_OFF (10u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_2_Bits.TIM1_CH3_IRQ */
#define IFX_GTM_ICM_IRQG_2_TIM1_CH3_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_2_Bits.TIM1_CH3_IRQ */
#define IFX_GTM_ICM_IRQG_2_TIM1_CH3_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_2_Bits.TIM1_CH3_IRQ */
#define IFX_GTM_ICM_IRQG_2_TIM1_CH3_IRQ_OFF (11u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_2_Bits.TIM1_CH4_IRQ */
#define IFX_GTM_ICM_IRQG_2_TIM1_CH4_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_2_Bits.TIM1_CH4_IRQ */
#define IFX_GTM_ICM_IRQG_2_TIM1_CH4_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_2_Bits.TIM1_CH4_IRQ */
#define IFX_GTM_ICM_IRQG_2_TIM1_CH4_IRQ_OFF (12u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_2_Bits.TIM1_CH5_IRQ */
#define IFX_GTM_ICM_IRQG_2_TIM1_CH5_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_2_Bits.TIM1_CH5_IRQ */
#define IFX_GTM_ICM_IRQG_2_TIM1_CH5_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_2_Bits.TIM1_CH5_IRQ */
#define IFX_GTM_ICM_IRQG_2_TIM1_CH5_IRQ_OFF (13u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_2_Bits.TIM1_CH6_IRQ */
#define IFX_GTM_ICM_IRQG_2_TIM1_CH6_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_2_Bits.TIM1_CH6_IRQ */
#define IFX_GTM_ICM_IRQG_2_TIM1_CH6_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_2_Bits.TIM1_CH6_IRQ */
#define IFX_GTM_ICM_IRQG_2_TIM1_CH6_IRQ_OFF (14u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_2_Bits.TIM1_CH7_IRQ */
#define IFX_GTM_ICM_IRQG_2_TIM1_CH7_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_2_Bits.TIM1_CH7_IRQ */
#define IFX_GTM_ICM_IRQG_2_TIM1_CH7_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_2_Bits.TIM1_CH7_IRQ */
#define IFX_GTM_ICM_IRQG_2_TIM1_CH7_IRQ_OFF (15u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_2_Bits.TIM2_CH0_IRQ */
#define IFX_GTM_ICM_IRQG_2_TIM2_CH0_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_2_Bits.TIM2_CH0_IRQ */
#define IFX_GTM_ICM_IRQG_2_TIM2_CH0_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_2_Bits.TIM2_CH0_IRQ */
#define IFX_GTM_ICM_IRQG_2_TIM2_CH0_IRQ_OFF (16u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_2_Bits.TIM2_CH1_IRQ */
#define IFX_GTM_ICM_IRQG_2_TIM2_CH1_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_2_Bits.TIM2_CH1_IRQ */
#define IFX_GTM_ICM_IRQG_2_TIM2_CH1_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_2_Bits.TIM2_CH1_IRQ */
#define IFX_GTM_ICM_IRQG_2_TIM2_CH1_IRQ_OFF (17u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_2_Bits.TIM2_CH2_IRQ */
#define IFX_GTM_ICM_IRQG_2_TIM2_CH2_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_2_Bits.TIM2_CH2_IRQ */
#define IFX_GTM_ICM_IRQG_2_TIM2_CH2_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_2_Bits.TIM2_CH2_IRQ */
#define IFX_GTM_ICM_IRQG_2_TIM2_CH2_IRQ_OFF (18u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_2_Bits.TIM2_CH3_IRQ */
#define IFX_GTM_ICM_IRQG_2_TIM2_CH3_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_2_Bits.TIM2_CH3_IRQ */
#define IFX_GTM_ICM_IRQG_2_TIM2_CH3_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_2_Bits.TIM2_CH3_IRQ */
#define IFX_GTM_ICM_IRQG_2_TIM2_CH3_IRQ_OFF (19u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_2_Bits.TIM2_CH4_IRQ */
#define IFX_GTM_ICM_IRQG_2_TIM2_CH4_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_2_Bits.TIM2_CH4_IRQ */
#define IFX_GTM_ICM_IRQG_2_TIM2_CH4_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_2_Bits.TIM2_CH4_IRQ */
#define IFX_GTM_ICM_IRQG_2_TIM2_CH4_IRQ_OFF (20u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_2_Bits.TIM2_CH5_IRQ */
#define IFX_GTM_ICM_IRQG_2_TIM2_CH5_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_2_Bits.TIM2_CH5_IRQ */
#define IFX_GTM_ICM_IRQG_2_TIM2_CH5_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_2_Bits.TIM2_CH5_IRQ */
#define IFX_GTM_ICM_IRQG_2_TIM2_CH5_IRQ_OFF (21u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_2_Bits.TIM2_CH6_IRQ */
#define IFX_GTM_ICM_IRQG_2_TIM2_CH6_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_2_Bits.TIM2_CH6_IRQ */
#define IFX_GTM_ICM_IRQG_2_TIM2_CH6_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_2_Bits.TIM2_CH6_IRQ */
#define IFX_GTM_ICM_IRQG_2_TIM2_CH6_IRQ_OFF (22u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_2_Bits.TIM2_CH7_IRQ */
#define IFX_GTM_ICM_IRQG_2_TIM2_CH7_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_2_Bits.TIM2_CH7_IRQ */
#define IFX_GTM_ICM_IRQG_2_TIM2_CH7_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_2_Bits.TIM2_CH7_IRQ */
#define IFX_GTM_ICM_IRQG_2_TIM2_CH7_IRQ_OFF (23u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_4_Bits.MCS0_CH0_IRQ */
#define IFX_GTM_ICM_IRQG_4_MCS0_CH0_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_4_Bits.MCS0_CH0_IRQ */
#define IFX_GTM_ICM_IRQG_4_MCS0_CH0_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_4_Bits.MCS0_CH0_IRQ */
#define IFX_GTM_ICM_IRQG_4_MCS0_CH0_IRQ_OFF (0u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_4_Bits.MCS0_CH1_IRQ */
#define IFX_GTM_ICM_IRQG_4_MCS0_CH1_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_4_Bits.MCS0_CH1_IRQ */
#define IFX_GTM_ICM_IRQG_4_MCS0_CH1_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_4_Bits.MCS0_CH1_IRQ */
#define IFX_GTM_ICM_IRQG_4_MCS0_CH1_IRQ_OFF (1u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_4_Bits.MCS0_CH2_IRQ */
#define IFX_GTM_ICM_IRQG_4_MCS0_CH2_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_4_Bits.MCS0_CH2_IRQ */
#define IFX_GTM_ICM_IRQG_4_MCS0_CH2_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_4_Bits.MCS0_CH2_IRQ */
#define IFX_GTM_ICM_IRQG_4_MCS0_CH2_IRQ_OFF (2u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_4_Bits.MCS0_CH3_IRQ */
#define IFX_GTM_ICM_IRQG_4_MCS0_CH3_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_4_Bits.MCS0_CH3_IRQ */
#define IFX_GTM_ICM_IRQG_4_MCS0_CH3_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_4_Bits.MCS0_CH3_IRQ */
#define IFX_GTM_ICM_IRQG_4_MCS0_CH3_IRQ_OFF (3u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_4_Bits.MCS0_CH4_IRQ */
#define IFX_GTM_ICM_IRQG_4_MCS0_CH4_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_4_Bits.MCS0_CH4_IRQ */
#define IFX_GTM_ICM_IRQG_4_MCS0_CH4_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_4_Bits.MCS0_CH4_IRQ */
#define IFX_GTM_ICM_IRQG_4_MCS0_CH4_IRQ_OFF (4u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_4_Bits.MCS0_CH5_IRQ */
#define IFX_GTM_ICM_IRQG_4_MCS0_CH5_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_4_Bits.MCS0_CH5_IRQ */
#define IFX_GTM_ICM_IRQG_4_MCS0_CH5_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_4_Bits.MCS0_CH5_IRQ */
#define IFX_GTM_ICM_IRQG_4_MCS0_CH5_IRQ_OFF (5u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_4_Bits.MCS0_CH6_IRQ */
#define IFX_GTM_ICM_IRQG_4_MCS0_CH6_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_4_Bits.MCS0_CH6_IRQ */
#define IFX_GTM_ICM_IRQG_4_MCS0_CH6_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_4_Bits.MCS0_CH6_IRQ */
#define IFX_GTM_ICM_IRQG_4_MCS0_CH6_IRQ_OFF (6u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_4_Bits.MCS0_CH7_IRQ */
#define IFX_GTM_ICM_IRQG_4_MCS0_CH7_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_4_Bits.MCS0_CH7_IRQ */
#define IFX_GTM_ICM_IRQG_4_MCS0_CH7_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_4_Bits.MCS0_CH7_IRQ */
#define IFX_GTM_ICM_IRQG_4_MCS0_CH7_IRQ_OFF (7u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_4_Bits.MCS1_CH0_IRQ */
#define IFX_GTM_ICM_IRQG_4_MCS1_CH0_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_4_Bits.MCS1_CH0_IRQ */
#define IFX_GTM_ICM_IRQG_4_MCS1_CH0_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_4_Bits.MCS1_CH0_IRQ */
#define IFX_GTM_ICM_IRQG_4_MCS1_CH0_IRQ_OFF (8u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_4_Bits.MCS1_CH1_IRQ */
#define IFX_GTM_ICM_IRQG_4_MCS1_CH1_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_4_Bits.MCS1_CH1_IRQ */
#define IFX_GTM_ICM_IRQG_4_MCS1_CH1_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_4_Bits.MCS1_CH1_IRQ */
#define IFX_GTM_ICM_IRQG_4_MCS1_CH1_IRQ_OFF (9u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_4_Bits.MCS1_CH2_IRQ */
#define IFX_GTM_ICM_IRQG_4_MCS1_CH2_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_4_Bits.MCS1_CH2_IRQ */
#define IFX_GTM_ICM_IRQG_4_MCS1_CH2_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_4_Bits.MCS1_CH2_IRQ */
#define IFX_GTM_ICM_IRQG_4_MCS1_CH2_IRQ_OFF (10u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_4_Bits.MCS1_CH3_IRQ */
#define IFX_GTM_ICM_IRQG_4_MCS1_CH3_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_4_Bits.MCS1_CH3_IRQ */
#define IFX_GTM_ICM_IRQG_4_MCS1_CH3_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_4_Bits.MCS1_CH3_IRQ */
#define IFX_GTM_ICM_IRQG_4_MCS1_CH3_IRQ_OFF (11u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_4_Bits.MCS1_CH4_IRQ */
#define IFX_GTM_ICM_IRQG_4_MCS1_CH4_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_4_Bits.MCS1_CH4_IRQ */
#define IFX_GTM_ICM_IRQG_4_MCS1_CH4_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_4_Bits.MCS1_CH4_IRQ */
#define IFX_GTM_ICM_IRQG_4_MCS1_CH4_IRQ_OFF (12u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_4_Bits.MCS1_CH5_IRQ */
#define IFX_GTM_ICM_IRQG_4_MCS1_CH5_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_4_Bits.MCS1_CH5_IRQ */
#define IFX_GTM_ICM_IRQG_4_MCS1_CH5_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_4_Bits.MCS1_CH5_IRQ */
#define IFX_GTM_ICM_IRQG_4_MCS1_CH5_IRQ_OFF (13u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_4_Bits.MCS1_CH6_IRQ */
#define IFX_GTM_ICM_IRQG_4_MCS1_CH6_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_4_Bits.MCS1_CH6_IRQ */
#define IFX_GTM_ICM_IRQG_4_MCS1_CH6_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_4_Bits.MCS1_CH6_IRQ */
#define IFX_GTM_ICM_IRQG_4_MCS1_CH6_IRQ_OFF (14u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_4_Bits.MCS1_CH7_IRQ */
#define IFX_GTM_ICM_IRQG_4_MCS1_CH7_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_4_Bits.MCS1_CH7_IRQ */
#define IFX_GTM_ICM_IRQG_4_MCS1_CH7_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_4_Bits.MCS1_CH7_IRQ */
#define IFX_GTM_ICM_IRQG_4_MCS1_CH7_IRQ_OFF (15u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_4_Bits.MCS2_CH0_IRQ */
#define IFX_GTM_ICM_IRQG_4_MCS2_CH0_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_4_Bits.MCS2_CH0_IRQ */
#define IFX_GTM_ICM_IRQG_4_MCS2_CH0_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_4_Bits.MCS2_CH0_IRQ */
#define IFX_GTM_ICM_IRQG_4_MCS2_CH0_IRQ_OFF (16u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_4_Bits.MCS2_CH1_IRQ */
#define IFX_GTM_ICM_IRQG_4_MCS2_CH1_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_4_Bits.MCS2_CH1_IRQ */
#define IFX_GTM_ICM_IRQG_4_MCS2_CH1_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_4_Bits.MCS2_CH1_IRQ */
#define IFX_GTM_ICM_IRQG_4_MCS2_CH1_IRQ_OFF (17u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_4_Bits.MCS2_CH2_IRQ */
#define IFX_GTM_ICM_IRQG_4_MCS2_CH2_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_4_Bits.MCS2_CH2_IRQ */
#define IFX_GTM_ICM_IRQG_4_MCS2_CH2_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_4_Bits.MCS2_CH2_IRQ */
#define IFX_GTM_ICM_IRQG_4_MCS2_CH2_IRQ_OFF (18u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_4_Bits.MCS2_CH3_IRQ */
#define IFX_GTM_ICM_IRQG_4_MCS2_CH3_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_4_Bits.MCS2_CH3_IRQ */
#define IFX_GTM_ICM_IRQG_4_MCS2_CH3_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_4_Bits.MCS2_CH3_IRQ */
#define IFX_GTM_ICM_IRQG_4_MCS2_CH3_IRQ_OFF (19u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_4_Bits.MCS2_CH4_IRQ */
#define IFX_GTM_ICM_IRQG_4_MCS2_CH4_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_4_Bits.MCS2_CH4_IRQ */
#define IFX_GTM_ICM_IRQG_4_MCS2_CH4_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_4_Bits.MCS2_CH4_IRQ */
#define IFX_GTM_ICM_IRQG_4_MCS2_CH4_IRQ_OFF (20u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_4_Bits.MCS2_CH5_IRQ */
#define IFX_GTM_ICM_IRQG_4_MCS2_CH5_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_4_Bits.MCS2_CH5_IRQ */
#define IFX_GTM_ICM_IRQG_4_MCS2_CH5_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_4_Bits.MCS2_CH5_IRQ */
#define IFX_GTM_ICM_IRQG_4_MCS2_CH5_IRQ_OFF (21u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_4_Bits.MCS2_CH6_IRQ */
#define IFX_GTM_ICM_IRQG_4_MCS2_CH6_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_4_Bits.MCS2_CH6_IRQ */
#define IFX_GTM_ICM_IRQG_4_MCS2_CH6_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_4_Bits.MCS2_CH6_IRQ */
#define IFX_GTM_ICM_IRQG_4_MCS2_CH6_IRQ_OFF (22u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_4_Bits.MCS2_CH7_IRQ */
#define IFX_GTM_ICM_IRQG_4_MCS2_CH7_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_4_Bits.MCS2_CH7_IRQ */
#define IFX_GTM_ICM_IRQG_4_MCS2_CH7_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_4_Bits.MCS2_CH7_IRQ */
#define IFX_GTM_ICM_IRQG_4_MCS2_CH7_IRQ_OFF (23u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH0_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM0_CH0_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH0_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM0_CH0_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH0_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM0_CH0_IRQ_OFF (0u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH10_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM0_CH10_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH10_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM0_CH10_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH10_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM0_CH10_IRQ_OFF (10u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH11_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM0_CH11_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH11_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM0_CH11_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH11_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM0_CH11_IRQ_OFF (11u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH12_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM0_CH12_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH12_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM0_CH12_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH12_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM0_CH12_IRQ_OFF (12u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH13_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM0_CH13_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH13_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM0_CH13_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH13_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM0_CH13_IRQ_OFF (13u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH14_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM0_CH14_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH14_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM0_CH14_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH14_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM0_CH14_IRQ_OFF (14u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH15_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM0_CH15_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH15_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM0_CH15_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH15_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM0_CH15_IRQ_OFF (15u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH1_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM0_CH1_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH1_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM0_CH1_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH1_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM0_CH1_IRQ_OFF (1u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH2_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM0_CH2_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH2_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM0_CH2_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH2_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM0_CH2_IRQ_OFF (2u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH3_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM0_CH3_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH3_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM0_CH3_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH3_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM0_CH3_IRQ_OFF (3u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH4_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM0_CH4_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH4_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM0_CH4_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH4_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM0_CH4_IRQ_OFF (4u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH5_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM0_CH5_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH5_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM0_CH5_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH5_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM0_CH5_IRQ_OFF (5u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH6_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM0_CH6_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH6_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM0_CH6_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH6_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM0_CH6_IRQ_OFF (6u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH7_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM0_CH7_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH7_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM0_CH7_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH7_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM0_CH7_IRQ_OFF (7u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH8_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM0_CH8_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH8_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM0_CH8_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH8_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM0_CH8_IRQ_OFF (8u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH9_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM0_CH9_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH9_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM0_CH9_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_6_Bits.TOM0_CH9_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM0_CH9_IRQ_OFF (9u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH0_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM1_CH0_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH0_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM1_CH0_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH0_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM1_CH0_IRQ_OFF (16u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH10_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM1_CH10_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH10_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM1_CH10_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH10_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM1_CH10_IRQ_OFF (26u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH11_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM1_CH11_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH11_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM1_CH11_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH11_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM1_CH11_IRQ_OFF (27u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH12_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM1_CH12_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH12_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM1_CH12_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH12_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM1_CH12_IRQ_OFF (28u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH13_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM1_CH13_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH13_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM1_CH13_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH13_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM1_CH13_IRQ_OFF (29u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH14_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM1_CH14_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH14_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM1_CH14_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH14_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM1_CH14_IRQ_OFF (30u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH15_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM1_CH15_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH15_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM1_CH15_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH15_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM1_CH15_IRQ_OFF (31u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH1_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM1_CH1_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH1_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM1_CH1_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH1_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM1_CH1_IRQ_OFF (17u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH2_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM1_CH2_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH2_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM1_CH2_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH2_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM1_CH2_IRQ_OFF (18u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH3_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM1_CH3_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH3_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM1_CH3_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH3_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM1_CH3_IRQ_OFF (19u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH4_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM1_CH4_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH4_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM1_CH4_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH4_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM1_CH4_IRQ_OFF (20u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH5_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM1_CH5_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH5_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM1_CH5_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH5_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM1_CH5_IRQ_OFF (21u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH6_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM1_CH6_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH6_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM1_CH6_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH6_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM1_CH6_IRQ_OFF (22u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH7_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM1_CH7_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH7_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM1_CH7_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH7_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM1_CH7_IRQ_OFF (23u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH8_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM1_CH8_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH8_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM1_CH8_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH8_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM1_CH8_IRQ_OFF (24u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH9_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM1_CH9_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH9_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM1_CH9_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_6_Bits.TOM1_CH9_IRQ */
#define IFX_GTM_ICM_IRQG_6_TOM1_CH9_IRQ_OFF (25u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_9_Bits.ATOM0_CH0_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM0_CH0_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_9_Bits.ATOM0_CH0_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM0_CH0_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_9_Bits.ATOM0_CH0_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM0_CH0_IRQ_OFF (0u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_9_Bits.ATOM0_CH1_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM0_CH1_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_9_Bits.ATOM0_CH1_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM0_CH1_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_9_Bits.ATOM0_CH1_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM0_CH1_IRQ_OFF (1u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_9_Bits.ATOM0_CH2_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM0_CH2_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_9_Bits.ATOM0_CH2_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM0_CH2_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_9_Bits.ATOM0_CH2_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM0_CH2_IRQ_OFF (2u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_9_Bits.ATOM0_CH3_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM0_CH3_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_9_Bits.ATOM0_CH3_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM0_CH3_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_9_Bits.ATOM0_CH3_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM0_CH3_IRQ_OFF (3u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_9_Bits.ATOM0_CH4_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM0_CH4_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_9_Bits.ATOM0_CH4_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM0_CH4_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_9_Bits.ATOM0_CH4_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM0_CH4_IRQ_OFF (4u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_9_Bits.ATOM0_CH5_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM0_CH5_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_9_Bits.ATOM0_CH5_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM0_CH5_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_9_Bits.ATOM0_CH5_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM0_CH5_IRQ_OFF (5u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_9_Bits.ATOM0_CH6_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM0_CH6_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_9_Bits.ATOM0_CH6_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM0_CH6_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_9_Bits.ATOM0_CH6_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM0_CH6_IRQ_OFF (6u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_9_Bits.ATOM0_CH7_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM0_CH7_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_9_Bits.ATOM0_CH7_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM0_CH7_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_9_Bits.ATOM0_CH7_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM0_CH7_IRQ_OFF (7u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_9_Bits.ATOM1_CH0_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM1_CH0_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_9_Bits.ATOM1_CH0_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM1_CH0_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_9_Bits.ATOM1_CH0_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM1_CH0_IRQ_OFF (8u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_9_Bits.ATOM1_CH1_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM1_CH1_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_9_Bits.ATOM1_CH1_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM1_CH1_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_9_Bits.ATOM1_CH1_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM1_CH1_IRQ_OFF (9u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_9_Bits.ATOM1_CH2_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM1_CH2_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_9_Bits.ATOM1_CH2_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM1_CH2_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_9_Bits.ATOM1_CH2_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM1_CH2_IRQ_OFF (10u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_9_Bits.ATOM1_CH3_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM1_CH3_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_9_Bits.ATOM1_CH3_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM1_CH3_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_9_Bits.ATOM1_CH3_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM1_CH3_IRQ_OFF (11u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_9_Bits.ATOM1_CH4_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM1_CH4_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_9_Bits.ATOM1_CH4_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM1_CH4_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_9_Bits.ATOM1_CH4_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM1_CH4_IRQ_OFF (12u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_9_Bits.ATOM1_CH5_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM1_CH5_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_9_Bits.ATOM1_CH5_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM1_CH5_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_9_Bits.ATOM1_CH5_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM1_CH5_IRQ_OFF (13u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_9_Bits.ATOM1_CH6_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM1_CH6_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_9_Bits.ATOM1_CH6_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM1_CH6_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_9_Bits.ATOM1_CH6_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM1_CH6_IRQ_OFF (14u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_9_Bits.ATOM1_CH7_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM1_CH7_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_9_Bits.ATOM1_CH7_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM1_CH7_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_9_Bits.ATOM1_CH7_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM1_CH7_IRQ_OFF (15u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_9_Bits.ATOM2_CH0_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM2_CH0_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_9_Bits.ATOM2_CH0_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM2_CH0_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_9_Bits.ATOM2_CH0_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM2_CH0_IRQ_OFF (16u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_9_Bits.ATOM2_CH1_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM2_CH1_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_9_Bits.ATOM2_CH1_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM2_CH1_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_9_Bits.ATOM2_CH1_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM2_CH1_IRQ_OFF (17u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_9_Bits.ATOM2_CH2_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM2_CH2_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_9_Bits.ATOM2_CH2_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM2_CH2_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_9_Bits.ATOM2_CH2_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM2_CH2_IRQ_OFF (18u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_9_Bits.ATOM2_CH3_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM2_CH3_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_9_Bits.ATOM2_CH3_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM2_CH3_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_9_Bits.ATOM2_CH3_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM2_CH3_IRQ_OFF (19u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_9_Bits.ATOM2_CH4_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM2_CH4_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_9_Bits.ATOM2_CH4_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM2_CH4_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_9_Bits.ATOM2_CH4_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM2_CH4_IRQ_OFF (20u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_9_Bits.ATOM2_CH5_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM2_CH5_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_9_Bits.ATOM2_CH5_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM2_CH5_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_9_Bits.ATOM2_CH5_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM2_CH5_IRQ_OFF (21u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_9_Bits.ATOM2_CH6_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM2_CH6_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_9_Bits.ATOM2_CH6_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM2_CH6_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_9_Bits.ATOM2_CH6_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM2_CH6_IRQ_OFF (22u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_9_Bits.ATOM2_CH7_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM2_CH7_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_9_Bits.ATOM2_CH7_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM2_CH7_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_9_Bits.ATOM2_CH7_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM2_CH7_IRQ_OFF (23u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_9_Bits.ATOM3_CH0_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM3_CH0_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_9_Bits.ATOM3_CH0_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM3_CH0_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_9_Bits.ATOM3_CH0_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM3_CH0_IRQ_OFF (24u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_9_Bits.ATOM3_CH1_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM3_CH1_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_9_Bits.ATOM3_CH1_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM3_CH1_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_9_Bits.ATOM3_CH1_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM3_CH1_IRQ_OFF (25u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_9_Bits.ATOM3_CH2_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM3_CH2_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_9_Bits.ATOM3_CH2_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM3_CH2_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_9_Bits.ATOM3_CH2_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM3_CH2_IRQ_OFF (26u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_9_Bits.ATOM3_CH3_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM3_CH3_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_9_Bits.ATOM3_CH3_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM3_CH3_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_9_Bits.ATOM3_CH3_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM3_CH3_IRQ_OFF (27u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_9_Bits.ATOM3_CH4_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM3_CH4_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_9_Bits.ATOM3_CH4_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM3_CH4_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_9_Bits.ATOM3_CH4_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM3_CH4_IRQ_OFF (28u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_9_Bits.ATOM3_CH5_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM3_CH5_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_9_Bits.ATOM3_CH5_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM3_CH5_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_9_Bits.ATOM3_CH5_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM3_CH5_IRQ_OFF (29u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_9_Bits.ATOM3_CH6_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM3_CH6_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_9_Bits.ATOM3_CH6_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM3_CH6_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_9_Bits.ATOM3_CH6_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM3_CH6_IRQ_OFF (30u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_9_Bits.ATOM3_CH7_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM3_CH7_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_9_Bits.ATOM3_CH7_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM3_CH7_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_9_Bits.ATOM3_CH7_IRQ */
#define IFX_GTM_ICM_IRQG_9_ATOM3_CH7_IRQ_OFF (31u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_CEI0_Bits.FIFO0_CH0_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI0_FIFO0_CH0_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_CEI0_Bits.FIFO0_CH0_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI0_FIFO0_CH0_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_CEI0_Bits.FIFO0_CH0_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI0_FIFO0_CH0_EIRQ_OFF (0u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_CEI0_Bits.FIFO0_CH1_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI0_FIFO0_CH1_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_CEI0_Bits.FIFO0_CH1_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI0_FIFO0_CH1_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_CEI0_Bits.FIFO0_CH1_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI0_FIFO0_CH1_EIRQ_OFF (1u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_CEI0_Bits.FIFO0_CH2_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI0_FIFO0_CH2_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_CEI0_Bits.FIFO0_CH2_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI0_FIFO0_CH2_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_CEI0_Bits.FIFO0_CH2_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI0_FIFO0_CH2_EIRQ_OFF (2u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_CEI0_Bits.FIFO0_CH3_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI0_FIFO0_CH3_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_CEI0_Bits.FIFO0_CH3_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI0_FIFO0_CH3_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_CEI0_Bits.FIFO0_CH3_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI0_FIFO0_CH3_EIRQ_OFF (3u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_CEI0_Bits.FIFO0_CH4_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI0_FIFO0_CH4_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_CEI0_Bits.FIFO0_CH4_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI0_FIFO0_CH4_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_CEI0_Bits.FIFO0_CH4_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI0_FIFO0_CH4_EIRQ_OFF (4u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_CEI0_Bits.FIFO0_CH5_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI0_FIFO0_CH5_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_CEI0_Bits.FIFO0_CH5_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI0_FIFO0_CH5_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_CEI0_Bits.FIFO0_CH5_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI0_FIFO0_CH5_EIRQ_OFF (5u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_CEI0_Bits.FIFO0_CH6_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI0_FIFO0_CH6_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_CEI0_Bits.FIFO0_CH6_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI0_FIFO0_CH6_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_CEI0_Bits.FIFO0_CH6_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI0_FIFO0_CH6_EIRQ_OFF (6u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_CEI0_Bits.FIFO0_CH7_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI0_FIFO0_CH7_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_CEI0_Bits.FIFO0_CH7_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI0_FIFO0_CH7_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_CEI0_Bits.FIFO0_CH7_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI0_FIFO0_CH7_EIRQ_OFF (7u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM0_CH0_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI1_TIM0_CH0_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM0_CH0_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI1_TIM0_CH0_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM0_CH0_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI1_TIM0_CH0_EIRQ_OFF (0u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM0_CH1_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI1_TIM0_CH1_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM0_CH1_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI1_TIM0_CH1_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM0_CH1_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI1_TIM0_CH1_EIRQ_OFF (1u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM0_CH2_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI1_TIM0_CH2_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM0_CH2_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI1_TIM0_CH2_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM0_CH2_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI1_TIM0_CH2_EIRQ_OFF (2u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM0_CH3_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI1_TIM0_CH3_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM0_CH3_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI1_TIM0_CH3_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM0_CH3_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI1_TIM0_CH3_EIRQ_OFF (3u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM0_CH4_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI1_TIM0_CH4_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM0_CH4_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI1_TIM0_CH4_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM0_CH4_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI1_TIM0_CH4_EIRQ_OFF (4u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM0_CH5_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI1_TIM0_CH5_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM0_CH5_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI1_TIM0_CH5_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM0_CH5_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI1_TIM0_CH5_EIRQ_OFF (5u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM0_CH6_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI1_TIM0_CH6_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM0_CH6_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI1_TIM0_CH6_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM0_CH6_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI1_TIM0_CH6_EIRQ_OFF (6u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM0_CH7_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI1_TIM0_CH7_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM0_CH7_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI1_TIM0_CH7_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM0_CH7_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI1_TIM0_CH7_EIRQ_OFF (7u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM1_CH0_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI1_TIM1_CH0_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM1_CH0_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI1_TIM1_CH0_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM1_CH0_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI1_TIM1_CH0_EIRQ_OFF (8u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM1_CH1_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI1_TIM1_CH1_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM1_CH1_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI1_TIM1_CH1_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM1_CH1_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI1_TIM1_CH1_EIRQ_OFF (9u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM1_CH2_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI1_TIM1_CH2_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM1_CH2_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI1_TIM1_CH2_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM1_CH2_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI1_TIM1_CH2_EIRQ_OFF (10u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM1_CH3_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI1_TIM1_CH3_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM1_CH3_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI1_TIM1_CH3_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM1_CH3_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI1_TIM1_CH3_EIRQ_OFF (11u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM1_CH4_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI1_TIM1_CH4_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM1_CH4_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI1_TIM1_CH4_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM1_CH4_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI1_TIM1_CH4_EIRQ_OFF (12u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM1_CH5_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI1_TIM1_CH5_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM1_CH5_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI1_TIM1_CH5_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM1_CH5_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI1_TIM1_CH5_EIRQ_OFF (13u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM1_CH6_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI1_TIM1_CH6_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM1_CH6_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI1_TIM1_CH6_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM1_CH6_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI1_TIM1_CH6_EIRQ_OFF (14u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM1_CH7_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI1_TIM1_CH7_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM1_CH7_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI1_TIM1_CH7_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM1_CH7_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI1_TIM1_CH7_EIRQ_OFF (15u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM2_CH0_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI1_TIM2_CH0_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM2_CH0_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI1_TIM2_CH0_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM2_CH0_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI1_TIM2_CH0_EIRQ_OFF (16u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM2_CH1_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI1_TIM2_CH1_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM2_CH1_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI1_TIM2_CH1_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM2_CH1_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI1_TIM2_CH1_EIRQ_OFF (17u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM2_CH2_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI1_TIM2_CH2_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM2_CH2_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI1_TIM2_CH2_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM2_CH2_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI1_TIM2_CH2_EIRQ_OFF (18u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM2_CH3_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI1_TIM2_CH3_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM2_CH3_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI1_TIM2_CH3_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM2_CH3_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI1_TIM2_CH3_EIRQ_OFF (19u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM2_CH4_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI1_TIM2_CH4_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM2_CH4_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI1_TIM2_CH4_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM2_CH4_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI1_TIM2_CH4_EIRQ_OFF (20u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM2_CH5_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI1_TIM2_CH5_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM2_CH5_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI1_TIM2_CH5_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM2_CH5_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI1_TIM2_CH5_EIRQ_OFF (21u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM2_CH6_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI1_TIM2_CH6_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM2_CH6_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI1_TIM2_CH6_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM2_CH6_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI1_TIM2_CH6_EIRQ_OFF (22u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM2_CH7_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI1_TIM2_CH7_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM2_CH7_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI1_TIM2_CH7_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_CEI1_Bits.TIM2_CH7_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI1_TIM2_CH7_EIRQ_OFF (23u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS0_CH0_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI3_MCS0_CH0_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS0_CH0_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI3_MCS0_CH0_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS0_CH0_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI3_MCS0_CH0_EIRQ_OFF (0u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS0_CH1_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI3_MCS0_CH1_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS0_CH1_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI3_MCS0_CH1_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS0_CH1_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI3_MCS0_CH1_EIRQ_OFF (1u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS0_CH2_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI3_MCS0_CH2_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS0_CH2_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI3_MCS0_CH2_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS0_CH2_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI3_MCS0_CH2_EIRQ_OFF (2u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS0_CH3_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI3_MCS0_CH3_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS0_CH3_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI3_MCS0_CH3_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS0_CH3_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI3_MCS0_CH3_EIRQ_OFF (3u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS0_CH4_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI3_MCS0_CH4_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS0_CH4_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI3_MCS0_CH4_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS0_CH4_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI3_MCS0_CH4_EIRQ_OFF (4u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS0_CH5_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI3_MCS0_CH5_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS0_CH5_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI3_MCS0_CH5_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS0_CH5_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI3_MCS0_CH5_EIRQ_OFF (5u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS0_CH6_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI3_MCS0_CH6_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS0_CH6_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI3_MCS0_CH6_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS0_CH6_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI3_MCS0_CH6_EIRQ_OFF (6u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS0_CH7_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI3_MCS0_CH7_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS0_CH7_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI3_MCS0_CH7_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS0_CH7_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI3_MCS0_CH7_EIRQ_OFF (7u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS1_CH0_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI3_MCS1_CH0_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS1_CH0_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI3_MCS1_CH0_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS1_CH0_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI3_MCS1_CH0_EIRQ_OFF (8u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS1_CH1_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI3_MCS1_CH1_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS1_CH1_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI3_MCS1_CH1_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS1_CH1_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI3_MCS1_CH1_EIRQ_OFF (9u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS1_CH2_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI3_MCS1_CH2_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS1_CH2_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI3_MCS1_CH2_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS1_CH2_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI3_MCS1_CH2_EIRQ_OFF (10u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS1_CH3_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI3_MCS1_CH3_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS1_CH3_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI3_MCS1_CH3_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS1_CH3_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI3_MCS1_CH3_EIRQ_OFF (11u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS1_CH4_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI3_MCS1_CH4_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS1_CH4_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI3_MCS1_CH4_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS1_CH4_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI3_MCS1_CH4_EIRQ_OFF (12u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS1_CH5_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI3_MCS1_CH5_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS1_CH5_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI3_MCS1_CH5_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS1_CH5_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI3_MCS1_CH5_EIRQ_OFF (13u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS1_CH6_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI3_MCS1_CH6_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS1_CH6_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI3_MCS1_CH6_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS1_CH6_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI3_MCS1_CH6_EIRQ_OFF (14u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS1_CH7_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI3_MCS1_CH7_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS1_CH7_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI3_MCS1_CH7_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS1_CH7_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI3_MCS1_CH7_EIRQ_OFF (15u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS2_CH0_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI3_MCS2_CH0_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS2_CH0_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI3_MCS2_CH0_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS2_CH0_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI3_MCS2_CH0_EIRQ_OFF (16u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS2_CH1_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI3_MCS2_CH1_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS2_CH1_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI3_MCS2_CH1_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS2_CH1_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI3_MCS2_CH1_EIRQ_OFF (17u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS2_CH2_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI3_MCS2_CH2_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS2_CH2_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI3_MCS2_CH2_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS2_CH2_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI3_MCS2_CH2_EIRQ_OFF (18u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS2_CH3_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI3_MCS2_CH3_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS2_CH3_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI3_MCS2_CH3_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS2_CH3_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI3_MCS2_CH3_EIRQ_OFF (19u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS2_CH4_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI3_MCS2_CH4_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS2_CH4_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI3_MCS2_CH4_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS2_CH4_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI3_MCS2_CH4_EIRQ_OFF (20u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS2_CH5_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI3_MCS2_CH5_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS2_CH5_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI3_MCS2_CH5_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS2_CH5_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI3_MCS2_CH5_EIRQ_OFF (21u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS2_CH6_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI3_MCS2_CH6_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS2_CH6_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI3_MCS2_CH6_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS2_CH6_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI3_MCS2_CH6_EIRQ_OFF (22u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS2_CH7_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI3_MCS2_CH7_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS2_CH7_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI3_MCS2_CH7_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_CEI3_Bits.MCS2_CH7_EIRQ */
#define IFX_GTM_ICM_IRQG_CEI3_MCS2_CH7_EIRQ_OFF (23u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_MEI_Bits.BRC_EIRQ */
#define IFX_GTM_ICM_IRQG_MEI_BRC_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_MEI_Bits.BRC_EIRQ */
#define IFX_GTM_ICM_IRQG_MEI_BRC_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_MEI_Bits.BRC_EIRQ */
#define IFX_GTM_ICM_IRQG_MEI_BRC_EIRQ_OFF (1u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_MEI_Bits.CMP_EIRQ */
#define IFX_GTM_ICM_IRQG_MEI_CMP_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_MEI_Bits.CMP_EIRQ */
#define IFX_GTM_ICM_IRQG_MEI_CMP_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_MEI_Bits.CMP_EIRQ */
#define IFX_GTM_ICM_IRQG_MEI_CMP_EIRQ_OFF (24u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_MEI_Bits.DPLL_EIRQ */
#define IFX_GTM_ICM_IRQG_MEI_DPLL_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_MEI_Bits.DPLL_EIRQ */
#define IFX_GTM_ICM_IRQG_MEI_DPLL_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_MEI_Bits.DPLL_EIRQ */
#define IFX_GTM_ICM_IRQG_MEI_DPLL_EIRQ_OFF (25u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_MEI_Bits.FIFO0_EIRQ */
#define IFX_GTM_ICM_IRQG_MEI_FIFO0_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_MEI_Bits.FIFO0_EIRQ */
#define IFX_GTM_ICM_IRQG_MEI_FIFO0_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_MEI_Bits.FIFO0_EIRQ */
#define IFX_GTM_ICM_IRQG_MEI_FIFO0_EIRQ_OFF (2u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_MEI_Bits.GTM_EIRQ */
#define IFX_GTM_ICM_IRQG_MEI_GTM_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_MEI_Bits.GTM_EIRQ */
#define IFX_GTM_ICM_IRQG_MEI_GTM_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_MEI_Bits.GTM_EIRQ */
#define IFX_GTM_ICM_IRQG_MEI_GTM_EIRQ_OFF (0u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_MEI_Bits.MCS0_EIRQ */
#define IFX_GTM_ICM_IRQG_MEI_MCS0_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_MEI_Bits.MCS0_EIRQ */
#define IFX_GTM_ICM_IRQG_MEI_MCS0_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_MEI_Bits.MCS0_EIRQ */
#define IFX_GTM_ICM_IRQG_MEI_MCS0_EIRQ_OFF (12u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_MEI_Bits.MCS1_EIRQ */
#define IFX_GTM_ICM_IRQG_MEI_MCS1_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_MEI_Bits.MCS1_EIRQ */
#define IFX_GTM_ICM_IRQG_MEI_MCS1_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_MEI_Bits.MCS1_EIRQ */
#define IFX_GTM_ICM_IRQG_MEI_MCS1_EIRQ_OFF (13u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_MEI_Bits.MCS2_EIRQ */
#define IFX_GTM_ICM_IRQG_MEI_MCS2_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_MEI_Bits.MCS2_EIRQ */
#define IFX_GTM_ICM_IRQG_MEI_MCS2_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_MEI_Bits.MCS2_EIRQ */
#define IFX_GTM_ICM_IRQG_MEI_MCS2_EIRQ_OFF (14u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_MEI_Bits.SPE0_EIRQ */
#define IFX_GTM_ICM_IRQG_MEI_SPE0_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_MEI_Bits.SPE0_EIRQ */
#define IFX_GTM_ICM_IRQG_MEI_SPE0_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_MEI_Bits.SPE0_EIRQ */
#define IFX_GTM_ICM_IRQG_MEI_SPE0_EIRQ_OFF (20u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_MEI_Bits.SPE1_EIRQ */
#define IFX_GTM_ICM_IRQG_MEI_SPE1_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_MEI_Bits.SPE1_EIRQ */
#define IFX_GTM_ICM_IRQG_MEI_SPE1_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_MEI_Bits.SPE1_EIRQ */
#define IFX_GTM_ICM_IRQG_MEI_SPE1_EIRQ_OFF (21u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_MEI_Bits.TIM0_EIRQ */
#define IFX_GTM_ICM_IRQG_MEI_TIM0_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_MEI_Bits.TIM0_EIRQ */
#define IFX_GTM_ICM_IRQG_MEI_TIM0_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_MEI_Bits.TIM0_EIRQ */
#define IFX_GTM_ICM_IRQG_MEI_TIM0_EIRQ_OFF (4u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_MEI_Bits.TIM1_EIRQ */
#define IFX_GTM_ICM_IRQG_MEI_TIM1_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_MEI_Bits.TIM1_EIRQ */
#define IFX_GTM_ICM_IRQG_MEI_TIM1_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_MEI_Bits.TIM1_EIRQ */
#define IFX_GTM_ICM_IRQG_MEI_TIM1_EIRQ_OFF (5u)

/** \brief  Length for Ifx_GTM_ICM_IRQG_MEI_Bits.TIM2_EIRQ */
#define IFX_GTM_ICM_IRQG_MEI_TIM2_EIRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_ICM_IRQG_MEI_Bits.TIM2_EIRQ */
#define IFX_GTM_ICM_IRQG_MEI_TIM2_EIRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ICM_IRQG_MEI_Bits.TIM2_EIRQ */
#define IFX_GTM_ICM_IRQG_MEI_TIM2_EIRQ_OFF (6u)

/** \brief  Length for Ifx_GTM_INOUTSEL_CAN_OUTSEL_Bits.SEL0 */
#define IFX_GTM_INOUTSEL_CAN_OUTSEL_SEL0_LEN (4u)

/** \brief  Mask for Ifx_GTM_INOUTSEL_CAN_OUTSEL_Bits.SEL0 */
#define IFX_GTM_INOUTSEL_CAN_OUTSEL_SEL0_MSK (0xfu)

/** \brief  Offset for Ifx_GTM_INOUTSEL_CAN_OUTSEL_Bits.SEL0 */
#define IFX_GTM_INOUTSEL_CAN_OUTSEL_SEL0_OFF (0u)

/** \brief  Length for Ifx_GTM_INOUTSEL_CAN_OUTSEL_Bits.SEL1 */
#define IFX_GTM_INOUTSEL_CAN_OUTSEL_SEL1_LEN (4u)

/** \brief  Mask for Ifx_GTM_INOUTSEL_CAN_OUTSEL_Bits.SEL1 */
#define IFX_GTM_INOUTSEL_CAN_OUTSEL_SEL1_MSK (0xfu)

/** \brief  Offset for Ifx_GTM_INOUTSEL_CAN_OUTSEL_Bits.SEL1 */
#define IFX_GTM_INOUTSEL_CAN_OUTSEL_SEL1_OFF (4u)

/** \brief  Length for Ifx_GTM_INOUTSEL_CAN_OUTSEL_Bits.SEL2 */
#define IFX_GTM_INOUTSEL_CAN_OUTSEL_SEL2_LEN (4u)

/** \brief  Mask for Ifx_GTM_INOUTSEL_CAN_OUTSEL_Bits.SEL2 */
#define IFX_GTM_INOUTSEL_CAN_OUTSEL_SEL2_MSK (0xfu)

/** \brief  Offset for Ifx_GTM_INOUTSEL_CAN_OUTSEL_Bits.SEL2 */
#define IFX_GTM_INOUTSEL_CAN_OUTSEL_SEL2_OFF (8u)

/** \brief  Length for Ifx_GTM_INOUTSEL_CAN_OUTSEL_Bits.SEL3 */
#define IFX_GTM_INOUTSEL_CAN_OUTSEL_SEL3_LEN (4u)

/** \brief  Mask for Ifx_GTM_INOUTSEL_CAN_OUTSEL_Bits.SEL3 */
#define IFX_GTM_INOUTSEL_CAN_OUTSEL_SEL3_MSK (0xfu)

/** \brief  Offset for Ifx_GTM_INOUTSEL_CAN_OUTSEL_Bits.SEL3 */
#define IFX_GTM_INOUTSEL_CAN_OUTSEL_SEL3_OFF (12u)

/** \brief  Length for Ifx_GTM_INOUTSEL_CAN_OUTSEL_Bits.SEL4 */
#define IFX_GTM_INOUTSEL_CAN_OUTSEL_SEL4_LEN (4u)

/** \brief  Mask for Ifx_GTM_INOUTSEL_CAN_OUTSEL_Bits.SEL4 */
#define IFX_GTM_INOUTSEL_CAN_OUTSEL_SEL4_MSK (0xfu)

/** \brief  Offset for Ifx_GTM_INOUTSEL_CAN_OUTSEL_Bits.SEL4 */
#define IFX_GTM_INOUTSEL_CAN_OUTSEL_SEL4_OFF (16u)

/** \brief  Length for Ifx_GTM_INOUTSEL_CAN_OUTSEL_Bits.SEL5 */
#define IFX_GTM_INOUTSEL_CAN_OUTSEL_SEL5_LEN (4u)

/** \brief  Mask for Ifx_GTM_INOUTSEL_CAN_OUTSEL_Bits.SEL5 */
#define IFX_GTM_INOUTSEL_CAN_OUTSEL_SEL5_MSK (0xfu)

/** \brief  Offset for Ifx_GTM_INOUTSEL_CAN_OUTSEL_Bits.SEL5 */
#define IFX_GTM_INOUTSEL_CAN_OUTSEL_SEL5_OFF (20u)

/** \brief  Length for Ifx_GTM_INOUTSEL_CAN_OUTSEL_Bits.SEL6 */
#define IFX_GTM_INOUTSEL_CAN_OUTSEL_SEL6_LEN (4u)

/** \brief  Mask for Ifx_GTM_INOUTSEL_CAN_OUTSEL_Bits.SEL6 */
#define IFX_GTM_INOUTSEL_CAN_OUTSEL_SEL6_MSK (0xfu)

/** \brief  Offset for Ifx_GTM_INOUTSEL_CAN_OUTSEL_Bits.SEL6 */
#define IFX_GTM_INOUTSEL_CAN_OUTSEL_SEL6_OFF (24u)

/** \brief  Length for Ifx_GTM_INOUTSEL_CAN_OUTSEL_Bits.SEL7 */
#define IFX_GTM_INOUTSEL_CAN_OUTSEL_SEL7_LEN (4u)

/** \brief  Mask for Ifx_GTM_INOUTSEL_CAN_OUTSEL_Bits.SEL7 */
#define IFX_GTM_INOUTSEL_CAN_OUTSEL_SEL7_MSK (0xfu)

/** \brief  Offset for Ifx_GTM_INOUTSEL_CAN_OUTSEL_Bits.SEL7 */
#define IFX_GTM_INOUTSEL_CAN_OUTSEL_SEL7_OFF (28u)

/** \brief  Length for Ifx_GTM_INOUTSEL_DSADC_INSEL_Bits.INSEL0 */
#define IFX_GTM_INOUTSEL_DSADC_INSEL_INSEL0_LEN (4u)

/** \brief  Mask for Ifx_GTM_INOUTSEL_DSADC_INSEL_Bits.INSEL0 */
#define IFX_GTM_INOUTSEL_DSADC_INSEL_INSEL0_MSK (0xfu)

/** \brief  Offset for Ifx_GTM_INOUTSEL_DSADC_INSEL_Bits.INSEL0 */
#define IFX_GTM_INOUTSEL_DSADC_INSEL_INSEL0_OFF (0u)

/** \brief  Length for Ifx_GTM_INOUTSEL_DSADC_INSEL_Bits.INSEL1 */
#define IFX_GTM_INOUTSEL_DSADC_INSEL_INSEL1_LEN (4u)

/** \brief  Mask for Ifx_GTM_INOUTSEL_DSADC_INSEL_Bits.INSEL1 */
#define IFX_GTM_INOUTSEL_DSADC_INSEL_INSEL1_MSK (0xfu)

/** \brief  Offset for Ifx_GTM_INOUTSEL_DSADC_INSEL_Bits.INSEL1 */
#define IFX_GTM_INOUTSEL_DSADC_INSEL_INSEL1_OFF (4u)

/** \brief  Length for Ifx_GTM_INOUTSEL_DSADC_INSEL_Bits.INSEL2 */
#define IFX_GTM_INOUTSEL_DSADC_INSEL_INSEL2_LEN (4u)

/** \brief  Mask for Ifx_GTM_INOUTSEL_DSADC_INSEL_Bits.INSEL2 */
#define IFX_GTM_INOUTSEL_DSADC_INSEL_INSEL2_MSK (0xfu)

/** \brief  Offset for Ifx_GTM_INOUTSEL_DSADC_INSEL_Bits.INSEL2 */
#define IFX_GTM_INOUTSEL_DSADC_INSEL_INSEL2_OFF (8u)

/** \brief  Length for Ifx_GTM_INOUTSEL_DSADC_INSEL_Bits.INSEL3 */
#define IFX_GTM_INOUTSEL_DSADC_INSEL_INSEL3_LEN (4u)

/** \brief  Mask for Ifx_GTM_INOUTSEL_DSADC_INSEL_Bits.INSEL3 */
#define IFX_GTM_INOUTSEL_DSADC_INSEL_INSEL3_MSK (0xfu)

/** \brief  Offset for Ifx_GTM_INOUTSEL_DSADC_INSEL_Bits.INSEL3 */
#define IFX_GTM_INOUTSEL_DSADC_INSEL_INSEL3_OFF (12u)

/** \brief  Length for Ifx_GTM_INOUTSEL_DSADC_INSEL_Bits.INSEL4 */
#define IFX_GTM_INOUTSEL_DSADC_INSEL_INSEL4_LEN (4u)

/** \brief  Mask for Ifx_GTM_INOUTSEL_DSADC_INSEL_Bits.INSEL4 */
#define IFX_GTM_INOUTSEL_DSADC_INSEL_INSEL4_MSK (0xfu)

/** \brief  Offset for Ifx_GTM_INOUTSEL_DSADC_INSEL_Bits.INSEL4 */
#define IFX_GTM_INOUTSEL_DSADC_INSEL_INSEL4_OFF (16u)

/** \brief  Length for Ifx_GTM_INOUTSEL_DSADC_INSEL_Bits.INSEL5 */
#define IFX_GTM_INOUTSEL_DSADC_INSEL_INSEL5_LEN (4u)

/** \brief  Mask for Ifx_GTM_INOUTSEL_DSADC_INSEL_Bits.INSEL5 */
#define IFX_GTM_INOUTSEL_DSADC_INSEL_INSEL5_MSK (0xfu)

/** \brief  Offset for Ifx_GTM_INOUTSEL_DSADC_INSEL_Bits.INSEL5 */
#define IFX_GTM_INOUTSEL_DSADC_INSEL_INSEL5_OFF (20u)

/** \brief  Length for Ifx_GTM_INOUTSEL_DSADC_INSEL_Bits.INSEL6 */
#define IFX_GTM_INOUTSEL_DSADC_INSEL_INSEL6_LEN (4u)

/** \brief  Mask for Ifx_GTM_INOUTSEL_DSADC_INSEL_Bits.INSEL6 */
#define IFX_GTM_INOUTSEL_DSADC_INSEL_INSEL6_MSK (0xfu)

/** \brief  Offset for Ifx_GTM_INOUTSEL_DSADC_INSEL_Bits.INSEL6 */
#define IFX_GTM_INOUTSEL_DSADC_INSEL_INSEL6_OFF (24u)

/** \brief  Length for Ifx_GTM_INOUTSEL_DSADC_INSEL_Bits.INSEL7 */
#define IFX_GTM_INOUTSEL_DSADC_INSEL_INSEL7_LEN (4u)

/** \brief  Mask for Ifx_GTM_INOUTSEL_DSADC_INSEL_Bits.INSEL7 */
#define IFX_GTM_INOUTSEL_DSADC_INSEL_INSEL7_MSK (0xfu)

/** \brief  Offset for Ifx_GTM_INOUTSEL_DSADC_INSEL_Bits.INSEL7 */
#define IFX_GTM_INOUTSEL_DSADC_INSEL_INSEL7_OFF (28u)

/** \brief  Length for Ifx_GTM_INOUTSEL_DSADC_OUTSEL_Bits.SEL0 */
#define IFX_GTM_INOUTSEL_DSADC_OUTSEL_SEL0_LEN (3u)

/** \brief  Mask for Ifx_GTM_INOUTSEL_DSADC_OUTSEL_Bits.SEL0 */
#define IFX_GTM_INOUTSEL_DSADC_OUTSEL_SEL0_MSK (0x7u)

/** \brief  Offset for Ifx_GTM_INOUTSEL_DSADC_OUTSEL_Bits.SEL0 */
#define IFX_GTM_INOUTSEL_DSADC_OUTSEL_SEL0_OFF (0u)

/** \brief  Length for Ifx_GTM_INOUTSEL_DSADC_OUTSEL_Bits.SEL2 */
#define IFX_GTM_INOUTSEL_DSADC_OUTSEL_SEL2_LEN (3u)

/** \brief  Mask for Ifx_GTM_INOUTSEL_DSADC_OUTSEL_Bits.SEL2 */
#define IFX_GTM_INOUTSEL_DSADC_OUTSEL_SEL2_MSK (0x7u)

/** \brief  Offset for Ifx_GTM_INOUTSEL_DSADC_OUTSEL_Bits.SEL2 */
#define IFX_GTM_INOUTSEL_DSADC_OUTSEL_SEL2_OFF (8u)

/** \brief  Length for Ifx_GTM_INOUTSEL_DSADC_OUTSEL_Bits.SEL3 */
#define IFX_GTM_INOUTSEL_DSADC_OUTSEL_SEL3_LEN (3u)

/** \brief  Mask for Ifx_GTM_INOUTSEL_DSADC_OUTSEL_Bits.SEL3 */
#define IFX_GTM_INOUTSEL_DSADC_OUTSEL_SEL3_MSK (0x7u)

/** \brief  Offset for Ifx_GTM_INOUTSEL_DSADC_OUTSEL_Bits.SEL3 */
#define IFX_GTM_INOUTSEL_DSADC_OUTSEL_SEL3_OFF (12u)

/** \brief  Length for Ifx_GTM_INOUTSEL_PSI5_OUTSEL0_Bits.SEL0 */
#define IFX_GTM_INOUTSEL_PSI5_OUTSEL0_SEL0_LEN (4u)

/** \brief  Mask for Ifx_GTM_INOUTSEL_PSI5_OUTSEL0_Bits.SEL0 */
#define IFX_GTM_INOUTSEL_PSI5_OUTSEL0_SEL0_MSK (0xfu)

/** \brief  Offset for Ifx_GTM_INOUTSEL_PSI5_OUTSEL0_Bits.SEL0 */
#define IFX_GTM_INOUTSEL_PSI5_OUTSEL0_SEL0_OFF (0u)

/** \brief  Length for Ifx_GTM_INOUTSEL_PSI5_OUTSEL0_Bits.SEL1 */
#define IFX_GTM_INOUTSEL_PSI5_OUTSEL0_SEL1_LEN (4u)

/** \brief  Mask for Ifx_GTM_INOUTSEL_PSI5_OUTSEL0_Bits.SEL1 */
#define IFX_GTM_INOUTSEL_PSI5_OUTSEL0_SEL1_MSK (0xfu)

/** \brief  Offset for Ifx_GTM_INOUTSEL_PSI5_OUTSEL0_Bits.SEL1 */
#define IFX_GTM_INOUTSEL_PSI5_OUTSEL0_SEL1_OFF (4u)

/** \brief  Length for Ifx_GTM_INOUTSEL_PSI5_OUTSEL0_Bits.SEL2 */
#define IFX_GTM_INOUTSEL_PSI5_OUTSEL0_SEL2_LEN (4u)

/** \brief  Mask for Ifx_GTM_INOUTSEL_PSI5_OUTSEL0_Bits.SEL2 */
#define IFX_GTM_INOUTSEL_PSI5_OUTSEL0_SEL2_MSK (0xfu)

/** \brief  Offset for Ifx_GTM_INOUTSEL_PSI5_OUTSEL0_Bits.SEL2 */
#define IFX_GTM_INOUTSEL_PSI5_OUTSEL0_SEL2_OFF (8u)

/** \brief  Length for Ifx_GTM_INOUTSEL_PSI5_OUTSEL0_Bits.SEL3 */
#define IFX_GTM_INOUTSEL_PSI5_OUTSEL0_SEL3_LEN (4u)

/** \brief  Mask for Ifx_GTM_INOUTSEL_PSI5_OUTSEL0_Bits.SEL3 */
#define IFX_GTM_INOUTSEL_PSI5_OUTSEL0_SEL3_MSK (0xfu)

/** \brief  Offset for Ifx_GTM_INOUTSEL_PSI5_OUTSEL0_Bits.SEL3 */
#define IFX_GTM_INOUTSEL_PSI5_OUTSEL0_SEL3_OFF (12u)

/** \brief  Length for Ifx_GTM_INOUTSEL_PSI5_OUTSEL0_Bits.SEL4 */
#define IFX_GTM_INOUTSEL_PSI5_OUTSEL0_SEL4_LEN (4u)

/** \brief  Mask for Ifx_GTM_INOUTSEL_PSI5_OUTSEL0_Bits.SEL4 */
#define IFX_GTM_INOUTSEL_PSI5_OUTSEL0_SEL4_MSK (0xfu)

/** \brief  Offset for Ifx_GTM_INOUTSEL_PSI5_OUTSEL0_Bits.SEL4 */
#define IFX_GTM_INOUTSEL_PSI5_OUTSEL0_SEL4_OFF (16u)

/** \brief  Length for Ifx_GTM_INOUTSEL_PSI5_OUTSEL0_Bits.SEL5 */
#define IFX_GTM_INOUTSEL_PSI5_OUTSEL0_SEL5_LEN (4u)

/** \brief  Mask for Ifx_GTM_INOUTSEL_PSI5_OUTSEL0_Bits.SEL5 */
#define IFX_GTM_INOUTSEL_PSI5_OUTSEL0_SEL5_MSK (0xfu)

/** \brief  Offset for Ifx_GTM_INOUTSEL_PSI5_OUTSEL0_Bits.SEL5 */
#define IFX_GTM_INOUTSEL_PSI5_OUTSEL0_SEL5_OFF (20u)

/** \brief  Length for Ifx_GTM_INOUTSEL_PSI5S_OUTSEL_Bits.SEL0 */
#define IFX_GTM_INOUTSEL_PSI5S_OUTSEL_SEL0_LEN (4u)

/** \brief  Mask for Ifx_GTM_INOUTSEL_PSI5S_OUTSEL_Bits.SEL0 */
#define IFX_GTM_INOUTSEL_PSI5S_OUTSEL_SEL0_MSK (0xfu)

/** \brief  Offset for Ifx_GTM_INOUTSEL_PSI5S_OUTSEL_Bits.SEL0 */
#define IFX_GTM_INOUTSEL_PSI5S_OUTSEL_SEL0_OFF (0u)

/** \brief  Length for Ifx_GTM_INOUTSEL_PSI5S_OUTSEL_Bits.SEL1 */
#define IFX_GTM_INOUTSEL_PSI5S_OUTSEL_SEL1_LEN (4u)

/** \brief  Mask for Ifx_GTM_INOUTSEL_PSI5S_OUTSEL_Bits.SEL1 */
#define IFX_GTM_INOUTSEL_PSI5S_OUTSEL_SEL1_MSK (0xfu)

/** \brief  Offset for Ifx_GTM_INOUTSEL_PSI5S_OUTSEL_Bits.SEL1 */
#define IFX_GTM_INOUTSEL_PSI5S_OUTSEL_SEL1_OFF (4u)

/** \brief  Length for Ifx_GTM_INOUTSEL_PSI5S_OUTSEL_Bits.SEL2 */
#define IFX_GTM_INOUTSEL_PSI5S_OUTSEL_SEL2_LEN (4u)

/** \brief  Mask for Ifx_GTM_INOUTSEL_PSI5S_OUTSEL_Bits.SEL2 */
#define IFX_GTM_INOUTSEL_PSI5S_OUTSEL_SEL2_MSK (0xfu)

/** \brief  Offset for Ifx_GTM_INOUTSEL_PSI5S_OUTSEL_Bits.SEL2 */
#define IFX_GTM_INOUTSEL_PSI5S_OUTSEL_SEL2_OFF (8u)

/** \brief  Length for Ifx_GTM_INOUTSEL_PSI5S_OUTSEL_Bits.SEL4 */
#define IFX_GTM_INOUTSEL_PSI5S_OUTSEL_SEL4_LEN (4u)

/** \brief  Mask for Ifx_GTM_INOUTSEL_PSI5S_OUTSEL_Bits.SEL4 */
#define IFX_GTM_INOUTSEL_PSI5S_OUTSEL_SEL4_MSK (0xfu)

/** \brief  Offset for Ifx_GTM_INOUTSEL_PSI5S_OUTSEL_Bits.SEL4 */
#define IFX_GTM_INOUTSEL_PSI5S_OUTSEL_SEL4_OFF (16u)

/** \brief  Length for Ifx_GTM_INOUTSEL_PSI5S_OUTSEL_Bits.SEL5 */
#define IFX_GTM_INOUTSEL_PSI5S_OUTSEL_SEL5_LEN (4u)

/** \brief  Mask for Ifx_GTM_INOUTSEL_PSI5S_OUTSEL_Bits.SEL5 */
#define IFX_GTM_INOUTSEL_PSI5S_OUTSEL_SEL5_MSK (0xfu)

/** \brief  Offset for Ifx_GTM_INOUTSEL_PSI5S_OUTSEL_Bits.SEL5 */
#define IFX_GTM_INOUTSEL_PSI5S_OUTSEL_SEL5_OFF (20u)

/** \brief  Length for Ifx_GTM_INOUTSEL_PSI5S_OUTSEL_Bits.SEL6 */
#define IFX_GTM_INOUTSEL_PSI5S_OUTSEL_SEL6_LEN (4u)

/** \brief  Mask for Ifx_GTM_INOUTSEL_PSI5S_OUTSEL_Bits.SEL6 */
#define IFX_GTM_INOUTSEL_PSI5S_OUTSEL_SEL6_MSK (0xfu)

/** \brief  Offset for Ifx_GTM_INOUTSEL_PSI5S_OUTSEL_Bits.SEL6 */
#define IFX_GTM_INOUTSEL_PSI5S_OUTSEL_SEL6_OFF (24u)

/** \brief  Length for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL0 */
#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL0_LEN (2u)

/** \brief  Mask for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL0 */
#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL0_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL0 */
#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL0_OFF (0u)

/** \brief  Length for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL10 */
#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL10_LEN (2u)

/** \brief  Mask for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL10 */
#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL10_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL10 */
#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL10_OFF (20u)

/** \brief  Length for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL11 */
#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL11_LEN (2u)

/** \brief  Mask for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL11 */
#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL11_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL11 */
#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL11_OFF (22u)

/** \brief  Length for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL12 */
#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL12_LEN (2u)

/** \brief  Mask for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL12 */
#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL12_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL12 */
#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL12_OFF (24u)

/** \brief  Length for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL13 */
#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL13_LEN (2u)

/** \brief  Mask for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL13 */
#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL13_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL13 */
#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL13_OFF (26u)

/** \brief  Length for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL14 */
#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL14_LEN (2u)

/** \brief  Mask for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL14 */
#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL14_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL14 */
#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL14_OFF (28u)

/** \brief  Length for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL15 */
#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL15_LEN (2u)

/** \brief  Mask for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL15 */
#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL15_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL15 */
#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL15_OFF (30u)

/** \brief  Length for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL1 */
#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL1_LEN (2u)

/** \brief  Mask for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL1 */
#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL1_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL1 */
#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL1_OFF (2u)

/** \brief  Length for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL2 */
#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL2_LEN (2u)

/** \brief  Mask for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL2 */
#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL2_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL2 */
#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL2_OFF (4u)

/** \brief  Length for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL3 */
#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL3_LEN (2u)

/** \brief  Mask for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL3 */
#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL3_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL3 */
#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL3_OFF (6u)

/** \brief  Length for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL4 */
#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL4_LEN (2u)

/** \brief  Mask for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL4 */
#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL4_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL4 */
#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL4_OFF (8u)

/** \brief  Length for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL5 */
#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL5_LEN (2u)

/** \brief  Mask for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL5 */
#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL5_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL5 */
#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL5_OFF (10u)

/** \brief  Length for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL6 */
#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL6_LEN (2u)

/** \brief  Mask for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL6 */
#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL6_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL6 */
#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL6_OFF (12u)

/** \brief  Length for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL7 */
#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL7_LEN (2u)

/** \brief  Mask for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL7 */
#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL7_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL7 */
#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL7_OFF (14u)

/** \brief  Length for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL8 */
#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL8_LEN (2u)

/** \brief  Mask for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL8 */
#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL8_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL8 */
#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL8_OFF (16u)

/** \brief  Length for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL9 */
#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL9_LEN (2u)

/** \brief  Mask for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL9 */
#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL9_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_INOUTSEL_T_OUTSEL_Bits.SEL9 */
#define IFX_GTM_INOUTSEL_T_OUTSEL_SEL9_OFF (18u)

/** \brief  Length for Ifx_GTM_INOUTSEL_TIM_INSEL_Bits.CH0SEL */
#define IFX_GTM_INOUTSEL_TIM_INSEL_CH0SEL_LEN (4u)

/** \brief  Mask for Ifx_GTM_INOUTSEL_TIM_INSEL_Bits.CH0SEL */
#define IFX_GTM_INOUTSEL_TIM_INSEL_CH0SEL_MSK (0xfu)

/** \brief  Offset for Ifx_GTM_INOUTSEL_TIM_INSEL_Bits.CH0SEL */
#define IFX_GTM_INOUTSEL_TIM_INSEL_CH0SEL_OFF (0u)

/** \brief  Length for Ifx_GTM_INOUTSEL_TIM_INSEL_Bits.CH1SEL */
#define IFX_GTM_INOUTSEL_TIM_INSEL_CH1SEL_LEN (4u)

/** \brief  Mask for Ifx_GTM_INOUTSEL_TIM_INSEL_Bits.CH1SEL */
#define IFX_GTM_INOUTSEL_TIM_INSEL_CH1SEL_MSK (0xfu)

/** \brief  Offset for Ifx_GTM_INOUTSEL_TIM_INSEL_Bits.CH1SEL */
#define IFX_GTM_INOUTSEL_TIM_INSEL_CH1SEL_OFF (4u)

/** \brief  Length for Ifx_GTM_INOUTSEL_TIM_INSEL_Bits.CH2SEL */
#define IFX_GTM_INOUTSEL_TIM_INSEL_CH2SEL_LEN (4u)

/** \brief  Mask for Ifx_GTM_INOUTSEL_TIM_INSEL_Bits.CH2SEL */
#define IFX_GTM_INOUTSEL_TIM_INSEL_CH2SEL_MSK (0xfu)

/** \brief  Offset for Ifx_GTM_INOUTSEL_TIM_INSEL_Bits.CH2SEL */
#define IFX_GTM_INOUTSEL_TIM_INSEL_CH2SEL_OFF (8u)

/** \brief  Length for Ifx_GTM_INOUTSEL_TIM_INSEL_Bits.CH3SEL */
#define IFX_GTM_INOUTSEL_TIM_INSEL_CH3SEL_LEN (4u)

/** \brief  Mask for Ifx_GTM_INOUTSEL_TIM_INSEL_Bits.CH3SEL */
#define IFX_GTM_INOUTSEL_TIM_INSEL_CH3SEL_MSK (0xfu)

/** \brief  Offset for Ifx_GTM_INOUTSEL_TIM_INSEL_Bits.CH3SEL */
#define IFX_GTM_INOUTSEL_TIM_INSEL_CH3SEL_OFF (12u)

/** \brief  Length for Ifx_GTM_INOUTSEL_TIM_INSEL_Bits.CH4SEL */
#define IFX_GTM_INOUTSEL_TIM_INSEL_CH4SEL_LEN (4u)

/** \brief  Mask for Ifx_GTM_INOUTSEL_TIM_INSEL_Bits.CH4SEL */
#define IFX_GTM_INOUTSEL_TIM_INSEL_CH4SEL_MSK (0xfu)

/** \brief  Offset for Ifx_GTM_INOUTSEL_TIM_INSEL_Bits.CH4SEL */
#define IFX_GTM_INOUTSEL_TIM_INSEL_CH4SEL_OFF (16u)

/** \brief  Length for Ifx_GTM_INOUTSEL_TIM_INSEL_Bits.CH5SEL */
#define IFX_GTM_INOUTSEL_TIM_INSEL_CH5SEL_LEN (4u)

/** \brief  Mask for Ifx_GTM_INOUTSEL_TIM_INSEL_Bits.CH5SEL */
#define IFX_GTM_INOUTSEL_TIM_INSEL_CH5SEL_MSK (0xfu)

/** \brief  Offset for Ifx_GTM_INOUTSEL_TIM_INSEL_Bits.CH5SEL */
#define IFX_GTM_INOUTSEL_TIM_INSEL_CH5SEL_OFF (20u)

/** \brief  Length for Ifx_GTM_INOUTSEL_TIM_INSEL_Bits.CH6SEL */
#define IFX_GTM_INOUTSEL_TIM_INSEL_CH6SEL_LEN (4u)

/** \brief  Mask for Ifx_GTM_INOUTSEL_TIM_INSEL_Bits.CH6SEL */
#define IFX_GTM_INOUTSEL_TIM_INSEL_CH6SEL_MSK (0xfu)

/** \brief  Offset for Ifx_GTM_INOUTSEL_TIM_INSEL_Bits.CH6SEL */
#define IFX_GTM_INOUTSEL_TIM_INSEL_CH6SEL_OFF (24u)

/** \brief  Length for Ifx_GTM_INOUTSEL_TIM_INSEL_Bits.CH7SEL */
#define IFX_GTM_INOUTSEL_TIM_INSEL_CH7SEL_LEN (4u)

/** \brief  Mask for Ifx_GTM_INOUTSEL_TIM_INSEL_Bits.CH7SEL */
#define IFX_GTM_INOUTSEL_TIM_INSEL_CH7SEL_MSK (0xfu)

/** \brief  Offset for Ifx_GTM_INOUTSEL_TIM_INSEL_Bits.CH7SEL */
#define IFX_GTM_INOUTSEL_TIM_INSEL_CH7SEL_OFF (28u)

/** \brief  Length for Ifx_GTM_IRQ_EN_Bits.AEI_IM_ADDR_IRQ_EN */
#define IFX_GTM_IRQ_EN_AEI_IM_ADDR_IRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_IRQ_EN_Bits.AEI_IM_ADDR_IRQ_EN */
#define IFX_GTM_IRQ_EN_AEI_IM_ADDR_IRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_IRQ_EN_Bits.AEI_IM_ADDR_IRQ_EN */
#define IFX_GTM_IRQ_EN_AEI_IM_ADDR_IRQ_EN_OFF (2u)

/** \brief  Length for Ifx_GTM_IRQ_EN_Bits.AEI_TO_XPT_IRQ_EN */
#define IFX_GTM_IRQ_EN_AEI_TO_XPT_IRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_IRQ_EN_Bits.AEI_TO_XPT_IRQ_EN */
#define IFX_GTM_IRQ_EN_AEI_TO_XPT_IRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_IRQ_EN_Bits.AEI_TO_XPT_IRQ_EN */
#define IFX_GTM_IRQ_EN_AEI_TO_XPT_IRQ_EN_OFF (0u)

/** \brief  Length for Ifx_GTM_IRQ_EN_Bits.AEI_USP_ADDR_IRQ_EN */
#define IFX_GTM_IRQ_EN_AEI_USP_ADDR_IRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_IRQ_EN_Bits.AEI_USP_ADDR_IRQ_EN */
#define IFX_GTM_IRQ_EN_AEI_USP_ADDR_IRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_IRQ_EN_Bits.AEI_USP_ADDR_IRQ_EN */
#define IFX_GTM_IRQ_EN_AEI_USP_ADDR_IRQ_EN_OFF (1u)

/** \brief  Length for Ifx_GTM_IRQ_EN_Bits.AEI_USP_BE_IRQ_EN */
#define IFX_GTM_IRQ_EN_AEI_USP_BE_IRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_IRQ_EN_Bits.AEI_USP_BE_IRQ_EN */
#define IFX_GTM_IRQ_EN_AEI_USP_BE_IRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_IRQ_EN_Bits.AEI_USP_BE_IRQ_EN */
#define IFX_GTM_IRQ_EN_AEI_USP_BE_IRQ_EN_OFF (3u)

/** \brief  Length for Ifx_GTM_IRQ_FORCINT_Bits.TRG_AEI_IM_ADDR */
#define IFX_GTM_IRQ_FORCINT_TRG_AEI_IM_ADDR_LEN (1u)

/** \brief  Mask for Ifx_GTM_IRQ_FORCINT_Bits.TRG_AEI_IM_ADDR */
#define IFX_GTM_IRQ_FORCINT_TRG_AEI_IM_ADDR_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_IRQ_FORCINT_Bits.TRG_AEI_IM_ADDR */
#define IFX_GTM_IRQ_FORCINT_TRG_AEI_IM_ADDR_OFF (2u)

/** \brief  Length for Ifx_GTM_IRQ_FORCINT_Bits.TRG_AEI_TO_XPT */
#define IFX_GTM_IRQ_FORCINT_TRG_AEI_TO_XPT_LEN (1u)

/** \brief  Mask for Ifx_GTM_IRQ_FORCINT_Bits.TRG_AEI_TO_XPT */
#define IFX_GTM_IRQ_FORCINT_TRG_AEI_TO_XPT_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_IRQ_FORCINT_Bits.TRG_AEI_TO_XPT */
#define IFX_GTM_IRQ_FORCINT_TRG_AEI_TO_XPT_OFF (0u)

/** \brief  Length for Ifx_GTM_IRQ_FORCINT_Bits.TRG_AEI_USP_ADDR */
#define IFX_GTM_IRQ_FORCINT_TRG_AEI_USP_ADDR_LEN (1u)

/** \brief  Mask for Ifx_GTM_IRQ_FORCINT_Bits.TRG_AEI_USP_ADDR */
#define IFX_GTM_IRQ_FORCINT_TRG_AEI_USP_ADDR_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_IRQ_FORCINT_Bits.TRG_AEI_USP_ADDR */
#define IFX_GTM_IRQ_FORCINT_TRG_AEI_USP_ADDR_OFF (1u)

/** \brief  Length for Ifx_GTM_IRQ_FORCINT_Bits.TRG_AEI_USP_BE */
#define IFX_GTM_IRQ_FORCINT_TRG_AEI_USP_BE_LEN (1u)

/** \brief  Mask for Ifx_GTM_IRQ_FORCINT_Bits.TRG_AEI_USP_BE */
#define IFX_GTM_IRQ_FORCINT_TRG_AEI_USP_BE_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_IRQ_FORCINT_Bits.TRG_AEI_USP_BE */
#define IFX_GTM_IRQ_FORCINT_TRG_AEI_USP_BE_OFF (3u)

/** \brief  Length for Ifx_GTM_IRQ_MODE_Bits.IRQ_MODE */
#define IFX_GTM_IRQ_MODE_IRQ_MODE_LEN (2u)

/** \brief  Mask for Ifx_GTM_IRQ_MODE_Bits.IRQ_MODE */
#define IFX_GTM_IRQ_MODE_IRQ_MODE_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_IRQ_MODE_Bits.IRQ_MODE */
#define IFX_GTM_IRQ_MODE_IRQ_MODE_OFF (0u)

/** \brief  Length for Ifx_GTM_IRQ_NOTIFY_Bits.AEI_IM_ADDR */
#define IFX_GTM_IRQ_NOTIFY_AEI_IM_ADDR_LEN (1u)

/** \brief  Mask for Ifx_GTM_IRQ_NOTIFY_Bits.AEI_IM_ADDR */
#define IFX_GTM_IRQ_NOTIFY_AEI_IM_ADDR_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_IRQ_NOTIFY_Bits.AEI_IM_ADDR */
#define IFX_GTM_IRQ_NOTIFY_AEI_IM_ADDR_OFF (2u)

/** \brief  Length for Ifx_GTM_IRQ_NOTIFY_Bits.AEI_TO_XPT */
#define IFX_GTM_IRQ_NOTIFY_AEI_TO_XPT_LEN (1u)

/** \brief  Mask for Ifx_GTM_IRQ_NOTIFY_Bits.AEI_TO_XPT */
#define IFX_GTM_IRQ_NOTIFY_AEI_TO_XPT_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_IRQ_NOTIFY_Bits.AEI_TO_XPT */
#define IFX_GTM_IRQ_NOTIFY_AEI_TO_XPT_OFF (0u)

/** \brief  Length for Ifx_GTM_IRQ_NOTIFY_Bits.AEI_USP_ADDR */
#define IFX_GTM_IRQ_NOTIFY_AEI_USP_ADDR_LEN (1u)

/** \brief  Mask for Ifx_GTM_IRQ_NOTIFY_Bits.AEI_USP_ADDR */
#define IFX_GTM_IRQ_NOTIFY_AEI_USP_ADDR_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_IRQ_NOTIFY_Bits.AEI_USP_ADDR */
#define IFX_GTM_IRQ_NOTIFY_AEI_USP_ADDR_OFF (1u)

/** \brief  Length for Ifx_GTM_IRQ_NOTIFY_Bits.AEI_USP_BE */
#define IFX_GTM_IRQ_NOTIFY_AEI_USP_BE_LEN (1u)

/** \brief  Mask for Ifx_GTM_IRQ_NOTIFY_Bits.AEI_USP_BE */
#define IFX_GTM_IRQ_NOTIFY_AEI_USP_BE_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_IRQ_NOTIFY_Bits.AEI_USP_BE */
#define IFX_GTM_IRQ_NOTIFY_AEI_USP_BE_OFF (3u)

/** \brief  Length for Ifx_GTM_KRST0_Bits.RST */
#define IFX_GTM_KRST0_RST_LEN (1u)

/** \brief  Mask for Ifx_GTM_KRST0_Bits.RST */
#define IFX_GTM_KRST0_RST_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_KRST0_Bits.RST */
#define IFX_GTM_KRST0_RST_OFF (0u)

/** \brief  Length for Ifx_GTM_KRST0_Bits.RSTSTAT */
#define IFX_GTM_KRST0_RSTSTAT_LEN (1u)

/** \brief  Mask for Ifx_GTM_KRST0_Bits.RSTSTAT */
#define IFX_GTM_KRST0_RSTSTAT_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_KRST0_Bits.RSTSTAT */
#define IFX_GTM_KRST0_RSTSTAT_OFF (1u)

/** \brief  Length for Ifx_GTM_KRST1_Bits.RST */
#define IFX_GTM_KRST1_RST_LEN (1u)

/** \brief  Mask for Ifx_GTM_KRST1_Bits.RST */
#define IFX_GTM_KRST1_RST_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_KRST1_Bits.RST */
#define IFX_GTM_KRST1_RST_OFF (0u)

/** \brief  Length for Ifx_GTM_KRSTCLR_Bits.CLR */
#define IFX_GTM_KRSTCLR_CLR_LEN (1u)

/** \brief  Mask for Ifx_GTM_KRSTCLR_Bits.CLR */
#define IFX_GTM_KRSTCLR_CLR_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_KRSTCLR_Bits.CLR */
#define IFX_GTM_KRSTCLR_CLR_OFF (0u)

/** \brief  Length for Ifx_GTM_MAP_CTRL_Bits.LSEL */
#define IFX_GTM_MAP_CTRL_LSEL_LEN (1u)

/** \brief  Mask for Ifx_GTM_MAP_CTRL_Bits.LSEL */
#define IFX_GTM_MAP_CTRL_LSEL_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MAP_CTRL_Bits.LSEL */
#define IFX_GTM_MAP_CTRL_LSEL_OFF (4u)

/** \brief  Length for Ifx_GTM_MAP_CTRL_Bits.SSL */
#define IFX_GTM_MAP_CTRL_SSL_LEN (3u)

/** \brief  Mask for Ifx_GTM_MAP_CTRL_Bits.SSL */
#define IFX_GTM_MAP_CTRL_SSL_MSK (0x7u)

/** \brief  Offset for Ifx_GTM_MAP_CTRL_Bits.SSL */
#define IFX_GTM_MAP_CTRL_SSL_OFF (1u)

/** \brief  Length for Ifx_GTM_MAP_CTRL_Bits.TSEL */
#define IFX_GTM_MAP_CTRL_TSEL_LEN (1u)

/** \brief  Mask for Ifx_GTM_MAP_CTRL_Bits.TSEL */
#define IFX_GTM_MAP_CTRL_TSEL_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MAP_CTRL_Bits.TSEL */
#define IFX_GTM_MAP_CTRL_TSEL_OFF (0u)

/** \brief  Length for Ifx_GTM_MAP_CTRL_Bits.TSPP0_DLD */
#define IFX_GTM_MAP_CTRL_TSPP0_DLD_LEN (1u)

/** \brief  Mask for Ifx_GTM_MAP_CTRL_Bits.TSPP0_DLD */
#define IFX_GTM_MAP_CTRL_TSPP0_DLD_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MAP_CTRL_Bits.TSPP0_DLD */
#define IFX_GTM_MAP_CTRL_TSPP0_DLD_OFF (17u)

/** \brief  Length for Ifx_GTM_MAP_CTRL_Bits.TSPP0_EN */
#define IFX_GTM_MAP_CTRL_TSPP0_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_MAP_CTRL_Bits.TSPP0_EN */
#define IFX_GTM_MAP_CTRL_TSPP0_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MAP_CTRL_Bits.TSPP0_EN */
#define IFX_GTM_MAP_CTRL_TSPP0_EN_OFF (16u)

/** \brief  Length for Ifx_GTM_MAP_CTRL_Bits.TSPP0_I0V */
#define IFX_GTM_MAP_CTRL_TSPP0_I0V_LEN (1u)

/** \brief  Mask for Ifx_GTM_MAP_CTRL_Bits.TSPP0_I0V */
#define IFX_GTM_MAP_CTRL_TSPP0_I0V_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MAP_CTRL_Bits.TSPP0_I0V */
#define IFX_GTM_MAP_CTRL_TSPP0_I0V_OFF (20u)

/** \brief  Length for Ifx_GTM_MAP_CTRL_Bits.TSPP0_I1V */
#define IFX_GTM_MAP_CTRL_TSPP0_I1V_LEN (1u)

/** \brief  Mask for Ifx_GTM_MAP_CTRL_Bits.TSPP0_I1V */
#define IFX_GTM_MAP_CTRL_TSPP0_I1V_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MAP_CTRL_Bits.TSPP0_I1V */
#define IFX_GTM_MAP_CTRL_TSPP0_I1V_OFF (21u)

/** \brief  Length for Ifx_GTM_MAP_CTRL_Bits.TSPP0_I2V */
#define IFX_GTM_MAP_CTRL_TSPP0_I2V_LEN (1u)

/** \brief  Mask for Ifx_GTM_MAP_CTRL_Bits.TSPP0_I2V */
#define IFX_GTM_MAP_CTRL_TSPP0_I2V_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MAP_CTRL_Bits.TSPP0_I2V */
#define IFX_GTM_MAP_CTRL_TSPP0_I2V_OFF (22u)

/** \brief  Length for Ifx_GTM_MAP_CTRL_Bits.TSPP1_DLD */
#define IFX_GTM_MAP_CTRL_TSPP1_DLD_LEN (1u)

/** \brief  Mask for Ifx_GTM_MAP_CTRL_Bits.TSPP1_DLD */
#define IFX_GTM_MAP_CTRL_TSPP1_DLD_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MAP_CTRL_Bits.TSPP1_DLD */
#define IFX_GTM_MAP_CTRL_TSPP1_DLD_OFF (25u)

/** \brief  Length for Ifx_GTM_MAP_CTRL_Bits.TSPP1_EN */
#define IFX_GTM_MAP_CTRL_TSPP1_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_MAP_CTRL_Bits.TSPP1_EN */
#define IFX_GTM_MAP_CTRL_TSPP1_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MAP_CTRL_Bits.TSPP1_EN */
#define IFX_GTM_MAP_CTRL_TSPP1_EN_OFF (24u)

/** \brief  Length for Ifx_GTM_MAP_CTRL_Bits.TSPP1_I0V */
#define IFX_GTM_MAP_CTRL_TSPP1_I0V_LEN (1u)

/** \brief  Mask for Ifx_GTM_MAP_CTRL_Bits.TSPP1_I0V */
#define IFX_GTM_MAP_CTRL_TSPP1_I0V_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MAP_CTRL_Bits.TSPP1_I0V */
#define IFX_GTM_MAP_CTRL_TSPP1_I0V_OFF (28u)

/** \brief  Length for Ifx_GTM_MAP_CTRL_Bits.TSPP1_I1V */
#define IFX_GTM_MAP_CTRL_TSPP1_I1V_LEN (1u)

/** \brief  Mask for Ifx_GTM_MAP_CTRL_Bits.TSPP1_I1V */
#define IFX_GTM_MAP_CTRL_TSPP1_I1V_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MAP_CTRL_Bits.TSPP1_I1V */
#define IFX_GTM_MAP_CTRL_TSPP1_I1V_OFF (29u)

/** \brief  Length for Ifx_GTM_MAP_CTRL_Bits.TSPP1_I2V */
#define IFX_GTM_MAP_CTRL_TSPP1_I2V_LEN (1u)

/** \brief  Mask for Ifx_GTM_MAP_CTRL_Bits.TSPP1_I2V */
#define IFX_GTM_MAP_CTRL_TSPP1_I2V_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MAP_CTRL_Bits.TSPP1_I2V */
#define IFX_GTM_MAP_CTRL_TSPP1_I2V_OFF (30u)

/** \brief  Length for Ifx_GTM_MCFG_CTRL_Bits.MEM0 */
#define IFX_GTM_MCFG_CTRL_MEM0_LEN (2u)

/** \brief  Mask for Ifx_GTM_MCFG_CTRL_Bits.MEM0 */
#define IFX_GTM_MCFG_CTRL_MEM0_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_MCFG_CTRL_Bits.MEM0 */
#define IFX_GTM_MCFG_CTRL_MEM0_OFF (0u)

/** \brief  Length for Ifx_GTM_MCFG_CTRL_Bits.MEM1 */
#define IFX_GTM_MCFG_CTRL_MEM1_LEN (2u)

/** \brief  Mask for Ifx_GTM_MCFG_CTRL_Bits.MEM1 */
#define IFX_GTM_MCFG_CTRL_MEM1_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_MCFG_CTRL_Bits.MEM1 */
#define IFX_GTM_MCFG_CTRL_MEM1_OFF (2u)

/** \brief  Length for Ifx_GTM_MCFG_CTRL_Bits.MEM2 */
#define IFX_GTM_MCFG_CTRL_MEM2_LEN (2u)

/** \brief  Mask for Ifx_GTM_MCFG_CTRL_Bits.MEM2 */
#define IFX_GTM_MCFG_CTRL_MEM2_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_MCFG_CTRL_Bits.MEM2 */
#define IFX_GTM_MCFG_CTRL_MEM2_OFF (4u)

/** \brief  Length for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG0 */
#define IFX_GTM_MCS_CH0_CTRG_TRG0_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG0 */
#define IFX_GTM_MCS_CH0_CTRG_TRG0_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG0 */
#define IFX_GTM_MCS_CH0_CTRG_TRG0_OFF (0u)

/** \brief  Length for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG10 */
#define IFX_GTM_MCS_CH0_CTRG_TRG10_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG10 */
#define IFX_GTM_MCS_CH0_CTRG_TRG10_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG10 */
#define IFX_GTM_MCS_CH0_CTRG_TRG10_OFF (10u)

/** \brief  Length for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG11 */
#define IFX_GTM_MCS_CH0_CTRG_TRG11_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG11 */
#define IFX_GTM_MCS_CH0_CTRG_TRG11_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG11 */
#define IFX_GTM_MCS_CH0_CTRG_TRG11_OFF (11u)

/** \brief  Length for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG12 */
#define IFX_GTM_MCS_CH0_CTRG_TRG12_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG12 */
#define IFX_GTM_MCS_CH0_CTRG_TRG12_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG12 */
#define IFX_GTM_MCS_CH0_CTRG_TRG12_OFF (12u)

/** \brief  Length for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG13 */
#define IFX_GTM_MCS_CH0_CTRG_TRG13_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG13 */
#define IFX_GTM_MCS_CH0_CTRG_TRG13_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG13 */
#define IFX_GTM_MCS_CH0_CTRG_TRG13_OFF (13u)

/** \brief  Length for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG14 */
#define IFX_GTM_MCS_CH0_CTRG_TRG14_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG14 */
#define IFX_GTM_MCS_CH0_CTRG_TRG14_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG14 */
#define IFX_GTM_MCS_CH0_CTRG_TRG14_OFF (14u)

/** \brief  Length for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG15 */
#define IFX_GTM_MCS_CH0_CTRG_TRG15_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG15 */
#define IFX_GTM_MCS_CH0_CTRG_TRG15_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG15 */
#define IFX_GTM_MCS_CH0_CTRG_TRG15_OFF (15u)

/** \brief  Length for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG1 */
#define IFX_GTM_MCS_CH0_CTRG_TRG1_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG1 */
#define IFX_GTM_MCS_CH0_CTRG_TRG1_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG1 */
#define IFX_GTM_MCS_CH0_CTRG_TRG1_OFF (1u)

/** \brief  Length for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG2 */
#define IFX_GTM_MCS_CH0_CTRG_TRG2_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG2 */
#define IFX_GTM_MCS_CH0_CTRG_TRG2_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG2 */
#define IFX_GTM_MCS_CH0_CTRG_TRG2_OFF (2u)

/** \brief  Length for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG3 */
#define IFX_GTM_MCS_CH0_CTRG_TRG3_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG3 */
#define IFX_GTM_MCS_CH0_CTRG_TRG3_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG3 */
#define IFX_GTM_MCS_CH0_CTRG_TRG3_OFF (3u)

/** \brief  Length for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG4 */
#define IFX_GTM_MCS_CH0_CTRG_TRG4_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG4 */
#define IFX_GTM_MCS_CH0_CTRG_TRG4_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG4 */
#define IFX_GTM_MCS_CH0_CTRG_TRG4_OFF (4u)

/** \brief  Length for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG5 */
#define IFX_GTM_MCS_CH0_CTRG_TRG5_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG5 */
#define IFX_GTM_MCS_CH0_CTRG_TRG5_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG5 */
#define IFX_GTM_MCS_CH0_CTRG_TRG5_OFF (5u)

/** \brief  Length for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG6 */
#define IFX_GTM_MCS_CH0_CTRG_TRG6_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG6 */
#define IFX_GTM_MCS_CH0_CTRG_TRG6_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG6 */
#define IFX_GTM_MCS_CH0_CTRG_TRG6_OFF (6u)

/** \brief  Length for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG7 */
#define IFX_GTM_MCS_CH0_CTRG_TRG7_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG7 */
#define IFX_GTM_MCS_CH0_CTRG_TRG7_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG7 */
#define IFX_GTM_MCS_CH0_CTRG_TRG7_OFF (7u)

/** \brief  Length for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG8 */
#define IFX_GTM_MCS_CH0_CTRG_TRG8_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG8 */
#define IFX_GTM_MCS_CH0_CTRG_TRG8_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG8 */
#define IFX_GTM_MCS_CH0_CTRG_TRG8_OFF (8u)

/** \brief  Length for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG9 */
#define IFX_GTM_MCS_CH0_CTRG_TRG9_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG9 */
#define IFX_GTM_MCS_CH0_CTRG_TRG9_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_CH0_CTRG_Bits.TRG9 */
#define IFX_GTM_MCS_CH0_CTRG_TRG9_OFF (9u)

/** \brief  Length for Ifx_GTM_MCS_CH0_STRG_Bits.TRG0 */
#define IFX_GTM_MCS_CH0_STRG_TRG0_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_CH0_STRG_Bits.TRG0 */
#define IFX_GTM_MCS_CH0_STRG_TRG0_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_CH0_STRG_Bits.TRG0 */
#define IFX_GTM_MCS_CH0_STRG_TRG0_OFF (0u)

/** \brief  Length for Ifx_GTM_MCS_CH0_STRG_Bits.TRG10 */
#define IFX_GTM_MCS_CH0_STRG_TRG10_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_CH0_STRG_Bits.TRG10 */
#define IFX_GTM_MCS_CH0_STRG_TRG10_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_CH0_STRG_Bits.TRG10 */
#define IFX_GTM_MCS_CH0_STRG_TRG10_OFF (10u)

/** \brief  Length for Ifx_GTM_MCS_CH0_STRG_Bits.TRG11 */
#define IFX_GTM_MCS_CH0_STRG_TRG11_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_CH0_STRG_Bits.TRG11 */
#define IFX_GTM_MCS_CH0_STRG_TRG11_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_CH0_STRG_Bits.TRG11 */
#define IFX_GTM_MCS_CH0_STRG_TRG11_OFF (11u)

/** \brief  Length for Ifx_GTM_MCS_CH0_STRG_Bits.TRG12 */
#define IFX_GTM_MCS_CH0_STRG_TRG12_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_CH0_STRG_Bits.TRG12 */
#define IFX_GTM_MCS_CH0_STRG_TRG12_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_CH0_STRG_Bits.TRG12 */
#define IFX_GTM_MCS_CH0_STRG_TRG12_OFF (12u)

/** \brief  Length for Ifx_GTM_MCS_CH0_STRG_Bits.TRG13 */
#define IFX_GTM_MCS_CH0_STRG_TRG13_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_CH0_STRG_Bits.TRG13 */
#define IFX_GTM_MCS_CH0_STRG_TRG13_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_CH0_STRG_Bits.TRG13 */
#define IFX_GTM_MCS_CH0_STRG_TRG13_OFF (13u)

/** \brief  Length for Ifx_GTM_MCS_CH0_STRG_Bits.TRG14 */
#define IFX_GTM_MCS_CH0_STRG_TRG14_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_CH0_STRG_Bits.TRG14 */
#define IFX_GTM_MCS_CH0_STRG_TRG14_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_CH0_STRG_Bits.TRG14 */
#define IFX_GTM_MCS_CH0_STRG_TRG14_OFF (14u)

/** \brief  Length for Ifx_GTM_MCS_CH0_STRG_Bits.TRG15 */
#define IFX_GTM_MCS_CH0_STRG_TRG15_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_CH0_STRG_Bits.TRG15 */
#define IFX_GTM_MCS_CH0_STRG_TRG15_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_CH0_STRG_Bits.TRG15 */
#define IFX_GTM_MCS_CH0_STRG_TRG15_OFF (15u)

/** \brief  Length for Ifx_GTM_MCS_CH0_STRG_Bits.TRG1 */
#define IFX_GTM_MCS_CH0_STRG_TRG1_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_CH0_STRG_Bits.TRG1 */
#define IFX_GTM_MCS_CH0_STRG_TRG1_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_CH0_STRG_Bits.TRG1 */
#define IFX_GTM_MCS_CH0_STRG_TRG1_OFF (1u)

/** \brief  Length for Ifx_GTM_MCS_CH0_STRG_Bits.TRG2 */
#define IFX_GTM_MCS_CH0_STRG_TRG2_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_CH0_STRG_Bits.TRG2 */
#define IFX_GTM_MCS_CH0_STRG_TRG2_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_CH0_STRG_Bits.TRG2 */
#define IFX_GTM_MCS_CH0_STRG_TRG2_OFF (2u)

/** \brief  Length for Ifx_GTM_MCS_CH0_STRG_Bits.TRG3 */
#define IFX_GTM_MCS_CH0_STRG_TRG3_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_CH0_STRG_Bits.TRG3 */
#define IFX_GTM_MCS_CH0_STRG_TRG3_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_CH0_STRG_Bits.TRG3 */
#define IFX_GTM_MCS_CH0_STRG_TRG3_OFF (3u)

/** \brief  Length for Ifx_GTM_MCS_CH0_STRG_Bits.TRG4 */
#define IFX_GTM_MCS_CH0_STRG_TRG4_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_CH0_STRG_Bits.TRG4 */
#define IFX_GTM_MCS_CH0_STRG_TRG4_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_CH0_STRG_Bits.TRG4 */
#define IFX_GTM_MCS_CH0_STRG_TRG4_OFF (4u)

/** \brief  Length for Ifx_GTM_MCS_CH0_STRG_Bits.TRG5 */
#define IFX_GTM_MCS_CH0_STRG_TRG5_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_CH0_STRG_Bits.TRG5 */
#define IFX_GTM_MCS_CH0_STRG_TRG5_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_CH0_STRG_Bits.TRG5 */
#define IFX_GTM_MCS_CH0_STRG_TRG5_OFF (5u)

/** \brief  Length for Ifx_GTM_MCS_CH0_STRG_Bits.TRG6 */
#define IFX_GTM_MCS_CH0_STRG_TRG6_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_CH0_STRG_Bits.TRG6 */
#define IFX_GTM_MCS_CH0_STRG_TRG6_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_CH0_STRG_Bits.TRG6 */
#define IFX_GTM_MCS_CH0_STRG_TRG6_OFF (6u)

/** \brief  Length for Ifx_GTM_MCS_CH0_STRG_Bits.TRG7 */
#define IFX_GTM_MCS_CH0_STRG_TRG7_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_CH0_STRG_Bits.TRG7 */
#define IFX_GTM_MCS_CH0_STRG_TRG7_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_CH0_STRG_Bits.TRG7 */
#define IFX_GTM_MCS_CH0_STRG_TRG7_OFF (7u)

/** \brief  Length for Ifx_GTM_MCS_CH0_STRG_Bits.TRG8 */
#define IFX_GTM_MCS_CH0_STRG_TRG8_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_CH0_STRG_Bits.TRG8 */
#define IFX_GTM_MCS_CH0_STRG_TRG8_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_CH0_STRG_Bits.TRG8 */
#define IFX_GTM_MCS_CH0_STRG_TRG8_OFF (8u)

/** \brief  Length for Ifx_GTM_MCS_CH0_STRG_Bits.TRG9 */
#define IFX_GTM_MCS_CH0_STRG_TRG9_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_CH0_STRG_Bits.TRG9 */
#define IFX_GTM_MCS_CH0_STRG_TRG9_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_CH0_STRG_Bits.TRG9 */
#define IFX_GTM_MCS_CH0_STRG_TRG9_OFF (9u)

/** \brief  Length for Ifx_GTM_MCS_CH_ACB_Bits.ACB0 */
#define IFX_GTM_MCS_CH_ACB_ACB0_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_CH_ACB_Bits.ACB0 */
#define IFX_GTM_MCS_CH_ACB_ACB0_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_CH_ACB_Bits.ACB0 */
#define IFX_GTM_MCS_CH_ACB_ACB0_OFF (0u)

/** \brief  Length for Ifx_GTM_MCS_CH_ACB_Bits.ACB1 */
#define IFX_GTM_MCS_CH_ACB_ACB1_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_CH_ACB_Bits.ACB1 */
#define IFX_GTM_MCS_CH_ACB_ACB1_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_CH_ACB_Bits.ACB1 */
#define IFX_GTM_MCS_CH_ACB_ACB1_OFF (1u)

/** \brief  Length for Ifx_GTM_MCS_CH_ACB_Bits.ACB2 */
#define IFX_GTM_MCS_CH_ACB_ACB2_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_CH_ACB_Bits.ACB2 */
#define IFX_GTM_MCS_CH_ACB_ACB2_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_CH_ACB_Bits.ACB2 */
#define IFX_GTM_MCS_CH_ACB_ACB2_OFF (2u)

/** \brief  Length for Ifx_GTM_MCS_CH_ACB_Bits.ACB3 */
#define IFX_GTM_MCS_CH_ACB_ACB3_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_CH_ACB_Bits.ACB3 */
#define IFX_GTM_MCS_CH_ACB_ACB3_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_CH_ACB_Bits.ACB3 */
#define IFX_GTM_MCS_CH_ACB_ACB3_OFF (3u)

/** \brief  Length for Ifx_GTM_MCS_CH_ACB_Bits.ACB4 */
#define IFX_GTM_MCS_CH_ACB_ACB4_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_CH_ACB_Bits.ACB4 */
#define IFX_GTM_MCS_CH_ACB_ACB4_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_CH_ACB_Bits.ACB4 */
#define IFX_GTM_MCS_CH_ACB_ACB4_OFF (4u)

/** \brief  Length for Ifx_GTM_MCS_CH_CTRL_Bits.CAT */
#define IFX_GTM_MCS_CH_CTRL_CAT_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_CH_CTRL_Bits.CAT */
#define IFX_GTM_MCS_CH_CTRL_CAT_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_CH_CTRL_Bits.CAT */
#define IFX_GTM_MCS_CH_CTRL_CAT_OFF (8u)

/** \brief  Length for Ifx_GTM_MCS_CH_CTRL_Bits.CWT */
#define IFX_GTM_MCS_CH_CTRL_CWT_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_CH_CTRL_Bits.CWT */
#define IFX_GTM_MCS_CH_CTRL_CWT_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_CH_CTRL_Bits.CWT */
#define IFX_GTM_MCS_CH_CTRL_CWT_OFF (9u)

/** \brief  Length for Ifx_GTM_MCS_CH_CTRL_Bits.CY */
#define IFX_GTM_MCS_CH_CTRL_CY_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_CH_CTRL_Bits.CY */
#define IFX_GTM_MCS_CH_CTRL_CY_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_CH_CTRL_Bits.CY */
#define IFX_GTM_MCS_CH_CTRL_CY_OFF (4u)

/** \brief  Length for Ifx_GTM_MCS_CH_CTRL_Bits.EN */
#define IFX_GTM_MCS_CH_CTRL_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_CH_CTRL_Bits.EN */
#define IFX_GTM_MCS_CH_CTRL_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_CH_CTRL_Bits.EN */
#define IFX_GTM_MCS_CH_CTRL_EN_OFF (0u)

/** \brief  Length for Ifx_GTM_MCS_CH_CTRL_Bits.ERR */
#define IFX_GTM_MCS_CH_CTRL_ERR_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_CH_CTRL_Bits.ERR */
#define IFX_GTM_MCS_CH_CTRL_ERR_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_CH_CTRL_Bits.ERR */
#define IFX_GTM_MCS_CH_CTRL_ERR_OFF (2u)

/** \brief  Length for Ifx_GTM_MCS_CH_CTRL_Bits.IRQ */
#define IFX_GTM_MCS_CH_CTRL_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_CH_CTRL_Bits.IRQ */
#define IFX_GTM_MCS_CH_CTRL_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_CH_CTRL_Bits.IRQ */
#define IFX_GTM_MCS_CH_CTRL_IRQ_OFF (1u)

/** \brief  Length for Ifx_GTM_MCS_CH_CTRL_Bits.N */
#define IFX_GTM_MCS_CH_CTRL_N_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_CH_CTRL_Bits.N */
#define IFX_GTM_MCS_CH_CTRL_N_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_CH_CTRL_Bits.N */
#define IFX_GTM_MCS_CH_CTRL_N_OFF (7u)

/** \brief  Length for Ifx_GTM_MCS_CH_CTRL_Bits.SP_CNT */
#define IFX_GTM_MCS_CH_CTRL_SP_CNT_LEN (3u)

/** \brief  Mask for Ifx_GTM_MCS_CH_CTRL_Bits.SP_CNT */
#define IFX_GTM_MCS_CH_CTRL_SP_CNT_MSK (0x7u)

/** \brief  Offset for Ifx_GTM_MCS_CH_CTRL_Bits.SP_CNT */
#define IFX_GTM_MCS_CH_CTRL_SP_CNT_OFF (16u)

/** \brief  Length for Ifx_GTM_MCS_CH_CTRL_Bits.V */
#define IFX_GTM_MCS_CH_CTRL_V_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_CH_CTRL_Bits.V */
#define IFX_GTM_MCS_CH_CTRL_V_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_CH_CTRL_Bits.V */
#define IFX_GTM_MCS_CH_CTRL_V_OFF (6u)

/** \brief  Length for Ifx_GTM_MCS_CH_CTRL_Bits.Z */
#define IFX_GTM_MCS_CH_CTRL_Z_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_CH_CTRL_Bits.Z */
#define IFX_GTM_MCS_CH_CTRL_Z_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_CH_CTRL_Bits.Z */
#define IFX_GTM_MCS_CH_CTRL_Z_OFF (5u)

/** \brief  Length for Ifx_GTM_MCS_CH_EIRQ_EN_Bits.MCS_EIRQ_EN */
#define IFX_GTM_MCS_CH_EIRQ_EN_MCS_EIRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_CH_EIRQ_EN_Bits.MCS_EIRQ_EN */
#define IFX_GTM_MCS_CH_EIRQ_EN_MCS_EIRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_CH_EIRQ_EN_Bits.MCS_EIRQ_EN */
#define IFX_GTM_MCS_CH_EIRQ_EN_MCS_EIRQ_EN_OFF (0u)

/** \brief  Length for Ifx_GTM_MCS_CH_EIRQ_EN_Bits.MEM_ERR_EIRQ_EN */
#define IFX_GTM_MCS_CH_EIRQ_EN_MEM_ERR_EIRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_CH_EIRQ_EN_Bits.MEM_ERR_EIRQ_EN */
#define IFX_GTM_MCS_CH_EIRQ_EN_MEM_ERR_EIRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_CH_EIRQ_EN_Bits.MEM_ERR_EIRQ_EN */
#define IFX_GTM_MCS_CH_EIRQ_EN_MEM_ERR_EIRQ_EN_OFF (2u)

/** \brief  Length for Ifx_GTM_MCS_CH_EIRQ_EN_Bits.STK_ERR_EIRQ_EN */
#define IFX_GTM_MCS_CH_EIRQ_EN_STK_ERR_EIRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_CH_EIRQ_EN_Bits.STK_ERR_EIRQ_EN */
#define IFX_GTM_MCS_CH_EIRQ_EN_STK_ERR_EIRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_CH_EIRQ_EN_Bits.STK_ERR_EIRQ_EN */
#define IFX_GTM_MCS_CH_EIRQ_EN_STK_ERR_EIRQ_EN_OFF (1u)

/** \brief  Length for Ifx_GTM_MCS_CH_IRQ_EN_Bits.MCS_IRQ_EN */
#define IFX_GTM_MCS_CH_IRQ_EN_MCS_IRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_CH_IRQ_EN_Bits.MCS_IRQ_EN */
#define IFX_GTM_MCS_CH_IRQ_EN_MCS_IRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_CH_IRQ_EN_Bits.MCS_IRQ_EN */
#define IFX_GTM_MCS_CH_IRQ_EN_MCS_IRQ_EN_OFF (0u)

/** \brief  Length for Ifx_GTM_MCS_CH_IRQ_EN_Bits.MEM_ERR_IRQ_EN */
#define IFX_GTM_MCS_CH_IRQ_EN_MEM_ERR_IRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_CH_IRQ_EN_Bits.MEM_ERR_IRQ_EN */
#define IFX_GTM_MCS_CH_IRQ_EN_MEM_ERR_IRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_CH_IRQ_EN_Bits.MEM_ERR_IRQ_EN */
#define IFX_GTM_MCS_CH_IRQ_EN_MEM_ERR_IRQ_EN_OFF (2u)

/** \brief  Length for Ifx_GTM_MCS_CH_IRQ_EN_Bits.STK_ERR_IRQ_EN */
#define IFX_GTM_MCS_CH_IRQ_EN_STK_ERR_IRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_CH_IRQ_EN_Bits.STK_ERR_IRQ_EN */
#define IFX_GTM_MCS_CH_IRQ_EN_STK_ERR_IRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_CH_IRQ_EN_Bits.STK_ERR_IRQ_EN */
#define IFX_GTM_MCS_CH_IRQ_EN_STK_ERR_IRQ_EN_OFF (1u)

/** \brief  Length for Ifx_GTM_MCS_CH_IRQ_FORCINT_Bits.TRG_MCS_IRQ */
#define IFX_GTM_MCS_CH_IRQ_FORCINT_TRG_MCS_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_CH_IRQ_FORCINT_Bits.TRG_MCS_IRQ */
#define IFX_GTM_MCS_CH_IRQ_FORCINT_TRG_MCS_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_CH_IRQ_FORCINT_Bits.TRG_MCS_IRQ */
#define IFX_GTM_MCS_CH_IRQ_FORCINT_TRG_MCS_IRQ_OFF (0u)

/** \brief  Length for Ifx_GTM_MCS_CH_IRQ_FORCINT_Bits.TRG_MEM_ERR_IRQ */
#define IFX_GTM_MCS_CH_IRQ_FORCINT_TRG_MEM_ERR_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_CH_IRQ_FORCINT_Bits.TRG_MEM_ERR_IRQ */
#define IFX_GTM_MCS_CH_IRQ_FORCINT_TRG_MEM_ERR_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_CH_IRQ_FORCINT_Bits.TRG_MEM_ERR_IRQ */
#define IFX_GTM_MCS_CH_IRQ_FORCINT_TRG_MEM_ERR_IRQ_OFF (2u)

/** \brief  Length for Ifx_GTM_MCS_CH_IRQ_FORCINT_Bits.TRG_STK_ERR_IRQ */
#define IFX_GTM_MCS_CH_IRQ_FORCINT_TRG_STK_ERR_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_CH_IRQ_FORCINT_Bits.TRG_STK_ERR_IRQ */
#define IFX_GTM_MCS_CH_IRQ_FORCINT_TRG_STK_ERR_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_CH_IRQ_FORCINT_Bits.TRG_STK_ERR_IRQ */
#define IFX_GTM_MCS_CH_IRQ_FORCINT_TRG_STK_ERR_IRQ_OFF (1u)

/** \brief  Length for Ifx_GTM_MCS_CH_IRQ_MODE_Bits.IRQ_MODE */
#define IFX_GTM_MCS_CH_IRQ_MODE_IRQ_MODE_LEN (2u)

/** \brief  Mask for Ifx_GTM_MCS_CH_IRQ_MODE_Bits.IRQ_MODE */
#define IFX_GTM_MCS_CH_IRQ_MODE_IRQ_MODE_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_MCS_CH_IRQ_MODE_Bits.IRQ_MODE */
#define IFX_GTM_MCS_CH_IRQ_MODE_IRQ_MODE_OFF (0u)

/** \brief  Length for Ifx_GTM_MCS_CH_IRQ_NOTIFY_Bits.MCS_IRQ */
#define IFX_GTM_MCS_CH_IRQ_NOTIFY_MCS_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_CH_IRQ_NOTIFY_Bits.MCS_IRQ */
#define IFX_GTM_MCS_CH_IRQ_NOTIFY_MCS_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_CH_IRQ_NOTIFY_Bits.MCS_IRQ */
#define IFX_GTM_MCS_CH_IRQ_NOTIFY_MCS_IRQ_OFF (0u)

/** \brief  Length for Ifx_GTM_MCS_CH_IRQ_NOTIFY_Bits.MEM_ERR_IRQ */
#define IFX_GTM_MCS_CH_IRQ_NOTIFY_MEM_ERR_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_CH_IRQ_NOTIFY_Bits.MEM_ERR_IRQ */
#define IFX_GTM_MCS_CH_IRQ_NOTIFY_MEM_ERR_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_CH_IRQ_NOTIFY_Bits.MEM_ERR_IRQ */
#define IFX_GTM_MCS_CH_IRQ_NOTIFY_MEM_ERR_IRQ_OFF (2u)

/** \brief  Length for Ifx_GTM_MCS_CH_IRQ_NOTIFY_Bits.STK_ERR_IRQ */
#define IFX_GTM_MCS_CH_IRQ_NOTIFY_STK_ERR_IRQ_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_CH_IRQ_NOTIFY_Bits.STK_ERR_IRQ */
#define IFX_GTM_MCS_CH_IRQ_NOTIFY_STK_ERR_IRQ_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_CH_IRQ_NOTIFY_Bits.STK_ERR_IRQ */
#define IFX_GTM_MCS_CH_IRQ_NOTIFY_STK_ERR_IRQ_OFF (1u)

/** \brief  Length for Ifx_GTM_MCS_CH_PC_Bits.PC */
#define IFX_GTM_MCS_CH_PC_PC_LEN (14u)

/** \brief  Mask for Ifx_GTM_MCS_CH_PC_Bits.PC */
#define IFX_GTM_MCS_CH_PC_PC_MSK (0x3fffu)

/** \brief  Offset for Ifx_GTM_MCS_CH_PC_Bits.PC */
#define IFX_GTM_MCS_CH_PC_PC_OFF (0u)

/** \brief  Length for Ifx_GTM_MCS_CH_R0_Bits.DATA */
#define IFX_GTM_MCS_CH_R0_DATA_LEN (24u)

/** \brief  Mask for Ifx_GTM_MCS_CH_R0_Bits.DATA */
#define IFX_GTM_MCS_CH_R0_DATA_MSK (0xffffffu)

/** \brief  Offset for Ifx_GTM_MCS_CH_R0_Bits.DATA */
#define IFX_GTM_MCS_CH_R0_DATA_OFF (0u)

/** \brief  Length for Ifx_GTM_MCS_CH_R1_Bits.DATA */
#define IFX_GTM_MCS_CH_R1_DATA_LEN (24u)

/** \brief  Mask for Ifx_GTM_MCS_CH_R1_Bits.DATA */
#define IFX_GTM_MCS_CH_R1_DATA_MSK (0xffffffu)

/** \brief  Offset for Ifx_GTM_MCS_CH_R1_Bits.DATA */
#define IFX_GTM_MCS_CH_R1_DATA_OFF (0u)

/** \brief  Length for Ifx_GTM_MCS_CH_R2_Bits.DATA */
#define IFX_GTM_MCS_CH_R2_DATA_LEN (24u)

/** \brief  Mask for Ifx_GTM_MCS_CH_R2_Bits.DATA */
#define IFX_GTM_MCS_CH_R2_DATA_MSK (0xffffffu)

/** \brief  Offset for Ifx_GTM_MCS_CH_R2_Bits.DATA */
#define IFX_GTM_MCS_CH_R2_DATA_OFF (0u)

/** \brief  Length for Ifx_GTM_MCS_CH_R3_Bits.DATA */
#define IFX_GTM_MCS_CH_R3_DATA_LEN (24u)

/** \brief  Mask for Ifx_GTM_MCS_CH_R3_Bits.DATA */
#define IFX_GTM_MCS_CH_R3_DATA_MSK (0xffffffu)

/** \brief  Offset for Ifx_GTM_MCS_CH_R3_Bits.DATA */
#define IFX_GTM_MCS_CH_R3_DATA_OFF (0u)

/** \brief  Length for Ifx_GTM_MCS_CH_R4_Bits.DATA */
#define IFX_GTM_MCS_CH_R4_DATA_LEN (24u)

/** \brief  Mask for Ifx_GTM_MCS_CH_R4_Bits.DATA */
#define IFX_GTM_MCS_CH_R4_DATA_MSK (0xffffffu)

/** \brief  Offset for Ifx_GTM_MCS_CH_R4_Bits.DATA */
#define IFX_GTM_MCS_CH_R4_DATA_OFF (0u)

/** \brief  Length for Ifx_GTM_MCS_CH_R5_Bits.DATA */
#define IFX_GTM_MCS_CH_R5_DATA_LEN (24u)

/** \brief  Mask for Ifx_GTM_MCS_CH_R5_Bits.DATA */
#define IFX_GTM_MCS_CH_R5_DATA_MSK (0xffffffu)

/** \brief  Offset for Ifx_GTM_MCS_CH_R5_Bits.DATA */
#define IFX_GTM_MCS_CH_R5_DATA_OFF (0u)

/** \brief  Length for Ifx_GTM_MCS_CH_R6_Bits.DATA */
#define IFX_GTM_MCS_CH_R6_DATA_LEN (24u)

/** \brief  Mask for Ifx_GTM_MCS_CH_R6_Bits.DATA */
#define IFX_GTM_MCS_CH_R6_DATA_MSK (0xffffffu)

/** \brief  Offset for Ifx_GTM_MCS_CH_R6_Bits.DATA */
#define IFX_GTM_MCS_CH_R6_DATA_OFF (0u)

/** \brief  Length for Ifx_GTM_MCS_CH_R7_Bits.DATA */
#define IFX_GTM_MCS_CH_R7_DATA_LEN (24u)

/** \brief  Mask for Ifx_GTM_MCS_CH_R7_Bits.DATA */
#define IFX_GTM_MCS_CH_R7_DATA_MSK (0xffffffu)

/** \brief  Offset for Ifx_GTM_MCS_CH_R7_Bits.DATA */
#define IFX_GTM_MCS_CH_R7_DATA_OFF (0u)

/** \brief  Length for Ifx_GTM_MCS_CTRL_Bits.HLT_SP_OFL */
#define IFX_GTM_MCS_CTRL_HLT_SP_OFL_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_CTRL_Bits.HLT_SP_OFL */
#define IFX_GTM_MCS_CTRL_HLT_SP_OFL_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_CTRL_Bits.HLT_SP_OFL */
#define IFX_GTM_MCS_CTRL_HLT_SP_OFL_OFF (1u)

/** \brief  Length for Ifx_GTM_MCS_CTRL_Bits.RAM_RST */
#define IFX_GTM_MCS_CTRL_RAM_RST_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_CTRL_Bits.RAM_RST */
#define IFX_GTM_MCS_CTRL_RAM_RST_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_CTRL_Bits.RAM_RST */
#define IFX_GTM_MCS_CTRL_RAM_RST_OFF (16u)

/** \brief  Length for Ifx_GTM_MCS_CTRL_Bits.SCHED */
#define IFX_GTM_MCS_CTRL_SCHED_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_CTRL_Bits.SCHED */
#define IFX_GTM_MCS_CTRL_SCHED_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_CTRL_Bits.SCHED */
#define IFX_GTM_MCS_CTRL_SCHED_OFF (0u)

/** \brief  Length for Ifx_GTM_MCS_ERR_Bits.ERR0 */
#define IFX_GTM_MCS_ERR_ERR0_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_ERR_Bits.ERR0 */
#define IFX_GTM_MCS_ERR_ERR0_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_ERR_Bits.ERR0 */
#define IFX_GTM_MCS_ERR_ERR0_OFF (0u)

/** \brief  Length for Ifx_GTM_MCS_ERR_Bits.ERR1 */
#define IFX_GTM_MCS_ERR_ERR1_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_ERR_Bits.ERR1 */
#define IFX_GTM_MCS_ERR_ERR1_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_ERR_Bits.ERR1 */
#define IFX_GTM_MCS_ERR_ERR1_OFF (1u)

/** \brief  Length for Ifx_GTM_MCS_ERR_Bits.ERR2 */
#define IFX_GTM_MCS_ERR_ERR2_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_ERR_Bits.ERR2 */
#define IFX_GTM_MCS_ERR_ERR2_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_ERR_Bits.ERR2 */
#define IFX_GTM_MCS_ERR_ERR2_OFF (2u)

/** \brief  Length for Ifx_GTM_MCS_ERR_Bits.ERR3 */
#define IFX_GTM_MCS_ERR_ERR3_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_ERR_Bits.ERR3 */
#define IFX_GTM_MCS_ERR_ERR3_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_ERR_Bits.ERR3 */
#define IFX_GTM_MCS_ERR_ERR3_OFF (3u)

/** \brief  Length for Ifx_GTM_MCS_ERR_Bits.ERR4 */
#define IFX_GTM_MCS_ERR_ERR4_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_ERR_Bits.ERR4 */
#define IFX_GTM_MCS_ERR_ERR4_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_ERR_Bits.ERR4 */
#define IFX_GTM_MCS_ERR_ERR4_OFF (4u)

/** \brief  Length for Ifx_GTM_MCS_ERR_Bits.ERR5 */
#define IFX_GTM_MCS_ERR_ERR5_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_ERR_Bits.ERR5 */
#define IFX_GTM_MCS_ERR_ERR5_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_ERR_Bits.ERR5 */
#define IFX_GTM_MCS_ERR_ERR5_OFF (5u)

/** \brief  Length for Ifx_GTM_MCS_ERR_Bits.ERR6 */
#define IFX_GTM_MCS_ERR_ERR6_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_ERR_Bits.ERR6 */
#define IFX_GTM_MCS_ERR_ERR6_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_ERR_Bits.ERR6 */
#define IFX_GTM_MCS_ERR_ERR6_OFF (6u)

/** \brief  Length for Ifx_GTM_MCS_ERR_Bits.ERR7 */
#define IFX_GTM_MCS_ERR_ERR7_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_ERR_Bits.ERR7 */
#define IFX_GTM_MCS_ERR_ERR7_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_ERR_Bits.ERR7 */
#define IFX_GTM_MCS_ERR_ERR7_OFF (7u)

/** \brief  Length for Ifx_GTM_MCS_RST_Bits.CAT0 */
#define IFX_GTM_MCS_RST_CAT0_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_RST_Bits.CAT0 */
#define IFX_GTM_MCS_RST_CAT0_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_RST_Bits.CAT0 */
#define IFX_GTM_MCS_RST_CAT0_OFF (8u)

/** \brief  Length for Ifx_GTM_MCS_RST_Bits.CAT1 */
#define IFX_GTM_MCS_RST_CAT1_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_RST_Bits.CAT1 */
#define IFX_GTM_MCS_RST_CAT1_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_RST_Bits.CAT1 */
#define IFX_GTM_MCS_RST_CAT1_OFF (9u)

/** \brief  Length for Ifx_GTM_MCS_RST_Bits.CAT2 */
#define IFX_GTM_MCS_RST_CAT2_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_RST_Bits.CAT2 */
#define IFX_GTM_MCS_RST_CAT2_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_RST_Bits.CAT2 */
#define IFX_GTM_MCS_RST_CAT2_OFF (10u)

/** \brief  Length for Ifx_GTM_MCS_RST_Bits.CAT3 */
#define IFX_GTM_MCS_RST_CAT3_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_RST_Bits.CAT3 */
#define IFX_GTM_MCS_RST_CAT3_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_RST_Bits.CAT3 */
#define IFX_GTM_MCS_RST_CAT3_OFF (11u)

/** \brief  Length for Ifx_GTM_MCS_RST_Bits.CAT4 */
#define IFX_GTM_MCS_RST_CAT4_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_RST_Bits.CAT4 */
#define IFX_GTM_MCS_RST_CAT4_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_RST_Bits.CAT4 */
#define IFX_GTM_MCS_RST_CAT4_OFF (12u)

/** \brief  Length for Ifx_GTM_MCS_RST_Bits.CAT5 */
#define IFX_GTM_MCS_RST_CAT5_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_RST_Bits.CAT5 */
#define IFX_GTM_MCS_RST_CAT5_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_RST_Bits.CAT5 */
#define IFX_GTM_MCS_RST_CAT5_OFF (13u)

/** \brief  Length for Ifx_GTM_MCS_RST_Bits.CAT6 */
#define IFX_GTM_MCS_RST_CAT6_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_RST_Bits.CAT6 */
#define IFX_GTM_MCS_RST_CAT6_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_RST_Bits.CAT6 */
#define IFX_GTM_MCS_RST_CAT6_OFF (14u)

/** \brief  Length for Ifx_GTM_MCS_RST_Bits.CAT7 */
#define IFX_GTM_MCS_RST_CAT7_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_RST_Bits.CAT7 */
#define IFX_GTM_MCS_RST_CAT7_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_RST_Bits.CAT7 */
#define IFX_GTM_MCS_RST_CAT7_OFF (15u)

/** \brief  Length for Ifx_GTM_MCS_RST_Bits.CWT0 */
#define IFX_GTM_MCS_RST_CWT0_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_RST_Bits.CWT0 */
#define IFX_GTM_MCS_RST_CWT0_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_RST_Bits.CWT0 */
#define IFX_GTM_MCS_RST_CWT0_OFF (16u)

/** \brief  Length for Ifx_GTM_MCS_RST_Bits.CWT1 */
#define IFX_GTM_MCS_RST_CWT1_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_RST_Bits.CWT1 */
#define IFX_GTM_MCS_RST_CWT1_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_RST_Bits.CWT1 */
#define IFX_GTM_MCS_RST_CWT1_OFF (17u)

/** \brief  Length for Ifx_GTM_MCS_RST_Bits.CWT2 */
#define IFX_GTM_MCS_RST_CWT2_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_RST_Bits.CWT2 */
#define IFX_GTM_MCS_RST_CWT2_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_RST_Bits.CWT2 */
#define IFX_GTM_MCS_RST_CWT2_OFF (18u)

/** \brief  Length for Ifx_GTM_MCS_RST_Bits.CWT3 */
#define IFX_GTM_MCS_RST_CWT3_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_RST_Bits.CWT3 */
#define IFX_GTM_MCS_RST_CWT3_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_RST_Bits.CWT3 */
#define IFX_GTM_MCS_RST_CWT3_OFF (19u)

/** \brief  Length for Ifx_GTM_MCS_RST_Bits.CWT4 */
#define IFX_GTM_MCS_RST_CWT4_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_RST_Bits.CWT4 */
#define IFX_GTM_MCS_RST_CWT4_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_RST_Bits.CWT4 */
#define IFX_GTM_MCS_RST_CWT4_OFF (20u)

/** \brief  Length for Ifx_GTM_MCS_RST_Bits.CWT5 */
#define IFX_GTM_MCS_RST_CWT5_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_RST_Bits.CWT5 */
#define IFX_GTM_MCS_RST_CWT5_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_RST_Bits.CWT5 */
#define IFX_GTM_MCS_RST_CWT5_OFF (21u)

/** \brief  Length for Ifx_GTM_MCS_RST_Bits.CWT6 */
#define IFX_GTM_MCS_RST_CWT6_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_RST_Bits.CWT6 */
#define IFX_GTM_MCS_RST_CWT6_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_RST_Bits.CWT6 */
#define IFX_GTM_MCS_RST_CWT6_OFF (22u)

/** \brief  Length for Ifx_GTM_MCS_RST_Bits.CWT7 */
#define IFX_GTM_MCS_RST_CWT7_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_RST_Bits.CWT7 */
#define IFX_GTM_MCS_RST_CWT7_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_RST_Bits.CWT7 */
#define IFX_GTM_MCS_RST_CWT7_OFF (23u)

/** \brief  Length for Ifx_GTM_MCS_RST_Bits.RST0 */
#define IFX_GTM_MCS_RST_RST0_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_RST_Bits.RST0 */
#define IFX_GTM_MCS_RST_RST0_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_RST_Bits.RST0 */
#define IFX_GTM_MCS_RST_RST0_OFF (0u)

/** \brief  Length for Ifx_GTM_MCS_RST_Bits.RST1 */
#define IFX_GTM_MCS_RST_RST1_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_RST_Bits.RST1 */
#define IFX_GTM_MCS_RST_RST1_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_RST_Bits.RST1 */
#define IFX_GTM_MCS_RST_RST1_OFF (1u)

/** \brief  Length for Ifx_GTM_MCS_RST_Bits.RST2 */
#define IFX_GTM_MCS_RST_RST2_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_RST_Bits.RST2 */
#define IFX_GTM_MCS_RST_RST2_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_RST_Bits.RST2 */
#define IFX_GTM_MCS_RST_RST2_OFF (2u)

/** \brief  Length for Ifx_GTM_MCS_RST_Bits.RST3 */
#define IFX_GTM_MCS_RST_RST3_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_RST_Bits.RST3 */
#define IFX_GTM_MCS_RST_RST3_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_RST_Bits.RST3 */
#define IFX_GTM_MCS_RST_RST3_OFF (3u)

/** \brief  Length for Ifx_GTM_MCS_RST_Bits.RST4 */
#define IFX_GTM_MCS_RST_RST4_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_RST_Bits.RST4 */
#define IFX_GTM_MCS_RST_RST4_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_RST_Bits.RST4 */
#define IFX_GTM_MCS_RST_RST4_OFF (4u)

/** \brief  Length for Ifx_GTM_MCS_RST_Bits.RST5 */
#define IFX_GTM_MCS_RST_RST5_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_RST_Bits.RST5 */
#define IFX_GTM_MCS_RST_RST5_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_RST_Bits.RST5 */
#define IFX_GTM_MCS_RST_RST5_OFF (5u)

/** \brief  Length for Ifx_GTM_MCS_RST_Bits.RST6 */
#define IFX_GTM_MCS_RST_RST6_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_RST_Bits.RST6 */
#define IFX_GTM_MCS_RST_RST6_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_RST_Bits.RST6 */
#define IFX_GTM_MCS_RST_RST6_OFF (6u)

/** \brief  Length for Ifx_GTM_MCS_RST_Bits.RST7 */
#define IFX_GTM_MCS_RST_RST7_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCS_RST_Bits.RST7 */
#define IFX_GTM_MCS_RST_RST7_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCS_RST_Bits.RST7 */
#define IFX_GTM_MCS_RST_RST7_OFF (7u)

/** \brief  Length for Ifx_GTM_MCSINTCLR_Bits.MCS000 */
#define IFX_GTM_MCSINTCLR_MCS000_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCSINTCLR_Bits.MCS000 */
#define IFX_GTM_MCSINTCLR_MCS000_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCSINTCLR_Bits.MCS000 */
#define IFX_GTM_MCSINTCLR_MCS000_OFF (0u)

/** \brief  Length for Ifx_GTM_MCSINTCLR_Bits.MCS001 */
#define IFX_GTM_MCSINTCLR_MCS001_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCSINTCLR_Bits.MCS001 */
#define IFX_GTM_MCSINTCLR_MCS001_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCSINTCLR_Bits.MCS001 */
#define IFX_GTM_MCSINTCLR_MCS001_OFF (1u)

/** \brief  Length for Ifx_GTM_MCSINTCLR_Bits.MCS010 */
#define IFX_GTM_MCSINTCLR_MCS010_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCSINTCLR_Bits.MCS010 */
#define IFX_GTM_MCSINTCLR_MCS010_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCSINTCLR_Bits.MCS010 */
#define IFX_GTM_MCSINTCLR_MCS010_OFF (2u)

/** \brief  Length for Ifx_GTM_MCSINTCLR_Bits.MCS011 */
#define IFX_GTM_MCSINTCLR_MCS011_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCSINTCLR_Bits.MCS011 */
#define IFX_GTM_MCSINTCLR_MCS011_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCSINTCLR_Bits.MCS011 */
#define IFX_GTM_MCSINTCLR_MCS011_OFF (3u)

/** \brief  Length for Ifx_GTM_MCSINTCLR_Bits.MCS100 */
#define IFX_GTM_MCSINTCLR_MCS100_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCSINTCLR_Bits.MCS100 */
#define IFX_GTM_MCSINTCLR_MCS100_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCSINTCLR_Bits.MCS100 */
#define IFX_GTM_MCSINTCLR_MCS100_OFF (4u)

/** \brief  Length for Ifx_GTM_MCSINTCLR_Bits.MCS101 */
#define IFX_GTM_MCSINTCLR_MCS101_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCSINTCLR_Bits.MCS101 */
#define IFX_GTM_MCSINTCLR_MCS101_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCSINTCLR_Bits.MCS101 */
#define IFX_GTM_MCSINTCLR_MCS101_OFF (5u)

/** \brief  Length for Ifx_GTM_MCSINTCLR_Bits.MCS110 */
#define IFX_GTM_MCSINTCLR_MCS110_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCSINTCLR_Bits.MCS110 */
#define IFX_GTM_MCSINTCLR_MCS110_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCSINTCLR_Bits.MCS110 */
#define IFX_GTM_MCSINTCLR_MCS110_OFF (6u)

/** \brief  Length for Ifx_GTM_MCSINTCLR_Bits.MCS111 */
#define IFX_GTM_MCSINTCLR_MCS111_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCSINTCLR_Bits.MCS111 */
#define IFX_GTM_MCSINTCLR_MCS111_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCSINTCLR_Bits.MCS111 */
#define IFX_GTM_MCSINTCLR_MCS111_OFF (7u)

/** \brief  Length for Ifx_GTM_MCSINTCLR_Bits.MCS200 */
#define IFX_GTM_MCSINTCLR_MCS200_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCSINTCLR_Bits.MCS200 */
#define IFX_GTM_MCSINTCLR_MCS200_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCSINTCLR_Bits.MCS200 */
#define IFX_GTM_MCSINTCLR_MCS200_OFF (8u)

/** \brief  Length for Ifx_GTM_MCSINTCLR_Bits.MCS201 */
#define IFX_GTM_MCSINTCLR_MCS201_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCSINTCLR_Bits.MCS201 */
#define IFX_GTM_MCSINTCLR_MCS201_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCSINTCLR_Bits.MCS201 */
#define IFX_GTM_MCSINTCLR_MCS201_OFF (9u)

/** \brief  Length for Ifx_GTM_MCSINTCLR_Bits.MCS210 */
#define IFX_GTM_MCSINTCLR_MCS210_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCSINTCLR_Bits.MCS210 */
#define IFX_GTM_MCSINTCLR_MCS210_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCSINTCLR_Bits.MCS210 */
#define IFX_GTM_MCSINTCLR_MCS210_OFF (10u)

/** \brief  Length for Ifx_GTM_MCSINTCLR_Bits.MCS211 */
#define IFX_GTM_MCSINTCLR_MCS211_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCSINTCLR_Bits.MCS211 */
#define IFX_GTM_MCSINTCLR_MCS211_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCSINTCLR_Bits.MCS211 */
#define IFX_GTM_MCSINTCLR_MCS211_OFF (11u)

/** \brief  Length for Ifx_GTM_MCSINTSTAT_Bits.MCS000 */
#define IFX_GTM_MCSINTSTAT_MCS000_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCSINTSTAT_Bits.MCS000 */
#define IFX_GTM_MCSINTSTAT_MCS000_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCSINTSTAT_Bits.MCS000 */
#define IFX_GTM_MCSINTSTAT_MCS000_OFF (0u)

/** \brief  Length for Ifx_GTM_MCSINTSTAT_Bits.MCS001 */
#define IFX_GTM_MCSINTSTAT_MCS001_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCSINTSTAT_Bits.MCS001 */
#define IFX_GTM_MCSINTSTAT_MCS001_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCSINTSTAT_Bits.MCS001 */
#define IFX_GTM_MCSINTSTAT_MCS001_OFF (1u)

/** \brief  Length for Ifx_GTM_MCSINTSTAT_Bits.MCS010 */
#define IFX_GTM_MCSINTSTAT_MCS010_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCSINTSTAT_Bits.MCS010 */
#define IFX_GTM_MCSINTSTAT_MCS010_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCSINTSTAT_Bits.MCS010 */
#define IFX_GTM_MCSINTSTAT_MCS010_OFF (2u)

/** \brief  Length for Ifx_GTM_MCSINTSTAT_Bits.MCS011 */
#define IFX_GTM_MCSINTSTAT_MCS011_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCSINTSTAT_Bits.MCS011 */
#define IFX_GTM_MCSINTSTAT_MCS011_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCSINTSTAT_Bits.MCS011 */
#define IFX_GTM_MCSINTSTAT_MCS011_OFF (3u)

/** \brief  Length for Ifx_GTM_MCSINTSTAT_Bits.MCS100 */
#define IFX_GTM_MCSINTSTAT_MCS100_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCSINTSTAT_Bits.MCS100 */
#define IFX_GTM_MCSINTSTAT_MCS100_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCSINTSTAT_Bits.MCS100 */
#define IFX_GTM_MCSINTSTAT_MCS100_OFF (4u)

/** \brief  Length for Ifx_GTM_MCSINTSTAT_Bits.MCS101 */
#define IFX_GTM_MCSINTSTAT_MCS101_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCSINTSTAT_Bits.MCS101 */
#define IFX_GTM_MCSINTSTAT_MCS101_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCSINTSTAT_Bits.MCS101 */
#define IFX_GTM_MCSINTSTAT_MCS101_OFF (5u)

/** \brief  Length for Ifx_GTM_MCSINTSTAT_Bits.MCS110 */
#define IFX_GTM_MCSINTSTAT_MCS110_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCSINTSTAT_Bits.MCS110 */
#define IFX_GTM_MCSINTSTAT_MCS110_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCSINTSTAT_Bits.MCS110 */
#define IFX_GTM_MCSINTSTAT_MCS110_OFF (6u)

/** \brief  Length for Ifx_GTM_MCSINTSTAT_Bits.MCS111 */
#define IFX_GTM_MCSINTSTAT_MCS111_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCSINTSTAT_Bits.MCS111 */
#define IFX_GTM_MCSINTSTAT_MCS111_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCSINTSTAT_Bits.MCS111 */
#define IFX_GTM_MCSINTSTAT_MCS111_OFF (7u)

/** \brief  Length for Ifx_GTM_MCSINTSTAT_Bits.MCS200 */
#define IFX_GTM_MCSINTSTAT_MCS200_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCSINTSTAT_Bits.MCS200 */
#define IFX_GTM_MCSINTSTAT_MCS200_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCSINTSTAT_Bits.MCS200 */
#define IFX_GTM_MCSINTSTAT_MCS200_OFF (8u)

/** \brief  Length for Ifx_GTM_MCSINTSTAT_Bits.MCS201 */
#define IFX_GTM_MCSINTSTAT_MCS201_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCSINTSTAT_Bits.MCS201 */
#define IFX_GTM_MCSINTSTAT_MCS201_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCSINTSTAT_Bits.MCS201 */
#define IFX_GTM_MCSINTSTAT_MCS201_OFF (9u)

/** \brief  Length for Ifx_GTM_MCSINTSTAT_Bits.MCS210 */
#define IFX_GTM_MCSINTSTAT_MCS210_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCSINTSTAT_Bits.MCS210 */
#define IFX_GTM_MCSINTSTAT_MCS210_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCSINTSTAT_Bits.MCS210 */
#define IFX_GTM_MCSINTSTAT_MCS210_OFF (10u)

/** \brief  Length for Ifx_GTM_MCSINTSTAT_Bits.MCS211 */
#define IFX_GTM_MCSINTSTAT_MCS211_LEN (1u)

/** \brief  Mask for Ifx_GTM_MCSINTSTAT_Bits.MCS211 */
#define IFX_GTM_MCSINTSTAT_MCS211_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MCSINTSTAT_Bits.MCS211 */
#define IFX_GTM_MCSINTSTAT_MCS211_OFF (11u)

/** \brief  Length for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_0_0 */
#define IFX_GTM_MON_ACTIVITY_0_MCA_0_0_LEN (1u)

/** \brief  Mask for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_0_0 */
#define IFX_GTM_MON_ACTIVITY_0_MCA_0_0_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_0_0 */
#define IFX_GTM_MON_ACTIVITY_0_MCA_0_0_OFF (0u)

/** \brief  Length for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_0_1 */
#define IFX_GTM_MON_ACTIVITY_0_MCA_0_1_LEN (1u)

/** \brief  Mask for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_0_1 */
#define IFX_GTM_MON_ACTIVITY_0_MCA_0_1_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_0_1 */
#define IFX_GTM_MON_ACTIVITY_0_MCA_0_1_OFF (1u)

/** \brief  Length for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_0_2 */
#define IFX_GTM_MON_ACTIVITY_0_MCA_0_2_LEN (1u)

/** \brief  Mask for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_0_2 */
#define IFX_GTM_MON_ACTIVITY_0_MCA_0_2_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_0_2 */
#define IFX_GTM_MON_ACTIVITY_0_MCA_0_2_OFF (2u)

/** \brief  Length for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_0_3 */
#define IFX_GTM_MON_ACTIVITY_0_MCA_0_3_LEN (1u)

/** \brief  Mask for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_0_3 */
#define IFX_GTM_MON_ACTIVITY_0_MCA_0_3_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_0_3 */
#define IFX_GTM_MON_ACTIVITY_0_MCA_0_3_OFF (3u)

/** \brief  Length for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_0_4 */
#define IFX_GTM_MON_ACTIVITY_0_MCA_0_4_LEN (1u)

/** \brief  Mask for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_0_4 */
#define IFX_GTM_MON_ACTIVITY_0_MCA_0_4_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_0_4 */
#define IFX_GTM_MON_ACTIVITY_0_MCA_0_4_OFF (4u)

/** \brief  Length for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_0_5 */
#define IFX_GTM_MON_ACTIVITY_0_MCA_0_5_LEN (1u)

/** \brief  Mask for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_0_5 */
#define IFX_GTM_MON_ACTIVITY_0_MCA_0_5_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_0_5 */
#define IFX_GTM_MON_ACTIVITY_0_MCA_0_5_OFF (5u)

/** \brief  Length for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_0_6 */
#define IFX_GTM_MON_ACTIVITY_0_MCA_0_6_LEN (1u)

/** \brief  Mask for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_0_6 */
#define IFX_GTM_MON_ACTIVITY_0_MCA_0_6_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_0_6 */
#define IFX_GTM_MON_ACTIVITY_0_MCA_0_6_OFF (6u)

/** \brief  Length for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_0_7 */
#define IFX_GTM_MON_ACTIVITY_0_MCA_0_7_LEN (1u)

/** \brief  Mask for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_0_7 */
#define IFX_GTM_MON_ACTIVITY_0_MCA_0_7_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_0_7 */
#define IFX_GTM_MON_ACTIVITY_0_MCA_0_7_OFF (7u)

/** \brief  Length for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_1_0 */
#define IFX_GTM_MON_ACTIVITY_0_MCA_1_0_LEN (1u)

/** \brief  Mask for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_1_0 */
#define IFX_GTM_MON_ACTIVITY_0_MCA_1_0_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_1_0 */
#define IFX_GTM_MON_ACTIVITY_0_MCA_1_0_OFF (8u)

/** \brief  Length for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_1_1 */
#define IFX_GTM_MON_ACTIVITY_0_MCA_1_1_LEN (1u)

/** \brief  Mask for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_1_1 */
#define IFX_GTM_MON_ACTIVITY_0_MCA_1_1_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_1_1 */
#define IFX_GTM_MON_ACTIVITY_0_MCA_1_1_OFF (9u)

/** \brief  Length for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_1_2 */
#define IFX_GTM_MON_ACTIVITY_0_MCA_1_2_LEN (1u)

/** \brief  Mask for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_1_2 */
#define IFX_GTM_MON_ACTIVITY_0_MCA_1_2_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_1_2 */
#define IFX_GTM_MON_ACTIVITY_0_MCA_1_2_OFF (10u)

/** \brief  Length for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_1_3 */
#define IFX_GTM_MON_ACTIVITY_0_MCA_1_3_LEN (1u)

/** \brief  Mask for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_1_3 */
#define IFX_GTM_MON_ACTIVITY_0_MCA_1_3_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_1_3 */
#define IFX_GTM_MON_ACTIVITY_0_MCA_1_3_OFF (11u)

/** \brief  Length for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_1_4 */
#define IFX_GTM_MON_ACTIVITY_0_MCA_1_4_LEN (1u)

/** \brief  Mask for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_1_4 */
#define IFX_GTM_MON_ACTIVITY_0_MCA_1_4_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_1_4 */
#define IFX_GTM_MON_ACTIVITY_0_MCA_1_4_OFF (12u)

/** \brief  Length for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_1_5 */
#define IFX_GTM_MON_ACTIVITY_0_MCA_1_5_LEN (1u)

/** \brief  Mask for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_1_5 */
#define IFX_GTM_MON_ACTIVITY_0_MCA_1_5_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_1_5 */
#define IFX_GTM_MON_ACTIVITY_0_MCA_1_5_OFF (13u)

/** \brief  Length for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_1_6 */
#define IFX_GTM_MON_ACTIVITY_0_MCA_1_6_LEN (1u)

/** \brief  Mask for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_1_6 */
#define IFX_GTM_MON_ACTIVITY_0_MCA_1_6_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_1_6 */
#define IFX_GTM_MON_ACTIVITY_0_MCA_1_6_OFF (14u)

/** \brief  Length for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_1_7 */
#define IFX_GTM_MON_ACTIVITY_0_MCA_1_7_LEN (1u)

/** \brief  Mask for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_1_7 */
#define IFX_GTM_MON_ACTIVITY_0_MCA_1_7_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_1_7 */
#define IFX_GTM_MON_ACTIVITY_0_MCA_1_7_OFF (15u)

/** \brief  Length for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_2_0 */
#define IFX_GTM_MON_ACTIVITY_0_MCA_2_0_LEN (1u)

/** \brief  Mask for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_2_0 */
#define IFX_GTM_MON_ACTIVITY_0_MCA_2_0_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_2_0 */
#define IFX_GTM_MON_ACTIVITY_0_MCA_2_0_OFF (16u)

/** \brief  Length for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_2_1 */
#define IFX_GTM_MON_ACTIVITY_0_MCA_2_1_LEN (1u)

/** \brief  Mask for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_2_1 */
#define IFX_GTM_MON_ACTIVITY_0_MCA_2_1_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_2_1 */
#define IFX_GTM_MON_ACTIVITY_0_MCA_2_1_OFF (17u)

/** \brief  Length for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_2_2 */
#define IFX_GTM_MON_ACTIVITY_0_MCA_2_2_LEN (1u)

/** \brief  Mask for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_2_2 */
#define IFX_GTM_MON_ACTIVITY_0_MCA_2_2_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_2_2 */
#define IFX_GTM_MON_ACTIVITY_0_MCA_2_2_OFF (18u)

/** \brief  Length for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_2_3 */
#define IFX_GTM_MON_ACTIVITY_0_MCA_2_3_LEN (1u)

/** \brief  Mask for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_2_3 */
#define IFX_GTM_MON_ACTIVITY_0_MCA_2_3_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_2_3 */
#define IFX_GTM_MON_ACTIVITY_0_MCA_2_3_OFF (19u)

/** \brief  Length for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_2_4 */
#define IFX_GTM_MON_ACTIVITY_0_MCA_2_4_LEN (1u)

/** \brief  Mask for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_2_4 */
#define IFX_GTM_MON_ACTIVITY_0_MCA_2_4_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_2_4 */
#define IFX_GTM_MON_ACTIVITY_0_MCA_2_4_OFF (20u)

/** \brief  Length for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_2_5 */
#define IFX_GTM_MON_ACTIVITY_0_MCA_2_5_LEN (1u)

/** \brief  Mask for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_2_5 */
#define IFX_GTM_MON_ACTIVITY_0_MCA_2_5_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_2_5 */
#define IFX_GTM_MON_ACTIVITY_0_MCA_2_5_OFF (21u)

/** \brief  Length for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_2_6 */
#define IFX_GTM_MON_ACTIVITY_0_MCA_2_6_LEN (1u)

/** \brief  Mask for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_2_6 */
#define IFX_GTM_MON_ACTIVITY_0_MCA_2_6_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_2_6 */
#define IFX_GTM_MON_ACTIVITY_0_MCA_2_6_OFF (22u)

/** \brief  Length for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_2_7 */
#define IFX_GTM_MON_ACTIVITY_0_MCA_2_7_LEN (1u)

/** \brief  Mask for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_2_7 */
#define IFX_GTM_MON_ACTIVITY_0_MCA_2_7_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MON_ACTIVITY_0_Bits.MCA_2_7 */
#define IFX_GTM_MON_ACTIVITY_0_MCA_2_7_OFF (23u)

/** \brief  Length for Ifx_GTM_MON_STATUS_Bits.ACT_CMU0 */
#define IFX_GTM_MON_STATUS_ACT_CMU0_LEN (1u)

/** \brief  Mask for Ifx_GTM_MON_STATUS_Bits.ACT_CMU0 */
#define IFX_GTM_MON_STATUS_ACT_CMU0_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MON_STATUS_Bits.ACT_CMU0 */
#define IFX_GTM_MON_STATUS_ACT_CMU0_OFF (0u)

/** \brief  Length for Ifx_GTM_MON_STATUS_Bits.ACT_CMU1 */
#define IFX_GTM_MON_STATUS_ACT_CMU1_LEN (1u)

/** \brief  Mask for Ifx_GTM_MON_STATUS_Bits.ACT_CMU1 */
#define IFX_GTM_MON_STATUS_ACT_CMU1_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MON_STATUS_Bits.ACT_CMU1 */
#define IFX_GTM_MON_STATUS_ACT_CMU1_OFF (1u)

/** \brief  Length for Ifx_GTM_MON_STATUS_Bits.ACT_CMU2 */
#define IFX_GTM_MON_STATUS_ACT_CMU2_LEN (1u)

/** \brief  Mask for Ifx_GTM_MON_STATUS_Bits.ACT_CMU2 */
#define IFX_GTM_MON_STATUS_ACT_CMU2_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MON_STATUS_Bits.ACT_CMU2 */
#define IFX_GTM_MON_STATUS_ACT_CMU2_OFF (2u)

/** \brief  Length for Ifx_GTM_MON_STATUS_Bits.ACT_CMU3 */
#define IFX_GTM_MON_STATUS_ACT_CMU3_LEN (1u)

/** \brief  Mask for Ifx_GTM_MON_STATUS_Bits.ACT_CMU3 */
#define IFX_GTM_MON_STATUS_ACT_CMU3_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MON_STATUS_Bits.ACT_CMU3 */
#define IFX_GTM_MON_STATUS_ACT_CMU3_OFF (3u)

/** \brief  Length for Ifx_GTM_MON_STATUS_Bits.ACT_CMU4 */
#define IFX_GTM_MON_STATUS_ACT_CMU4_LEN (1u)

/** \brief  Mask for Ifx_GTM_MON_STATUS_Bits.ACT_CMU4 */
#define IFX_GTM_MON_STATUS_ACT_CMU4_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MON_STATUS_Bits.ACT_CMU4 */
#define IFX_GTM_MON_STATUS_ACT_CMU4_OFF (4u)

/** \brief  Length for Ifx_GTM_MON_STATUS_Bits.ACT_CMU5 */
#define IFX_GTM_MON_STATUS_ACT_CMU5_LEN (1u)

/** \brief  Mask for Ifx_GTM_MON_STATUS_Bits.ACT_CMU5 */
#define IFX_GTM_MON_STATUS_ACT_CMU5_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MON_STATUS_Bits.ACT_CMU5 */
#define IFX_GTM_MON_STATUS_ACT_CMU5_OFF (5u)

/** \brief  Length for Ifx_GTM_MON_STATUS_Bits.ACT_CMU6 */
#define IFX_GTM_MON_STATUS_ACT_CMU6_LEN (1u)

/** \brief  Mask for Ifx_GTM_MON_STATUS_Bits.ACT_CMU6 */
#define IFX_GTM_MON_STATUS_ACT_CMU6_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MON_STATUS_Bits.ACT_CMU6 */
#define IFX_GTM_MON_STATUS_ACT_CMU6_OFF (6u)

/** \brief  Length for Ifx_GTM_MON_STATUS_Bits.ACT_CMU7 */
#define IFX_GTM_MON_STATUS_ACT_CMU7_LEN (1u)

/** \brief  Mask for Ifx_GTM_MON_STATUS_Bits.ACT_CMU7 */
#define IFX_GTM_MON_STATUS_ACT_CMU7_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MON_STATUS_Bits.ACT_CMU7 */
#define IFX_GTM_MON_STATUS_ACT_CMU7_OFF (7u)

/** \brief  Length for Ifx_GTM_MON_STATUS_Bits.ACT_CMUFX0 */
#define IFX_GTM_MON_STATUS_ACT_CMUFX0_LEN (1u)

/** \brief  Mask for Ifx_GTM_MON_STATUS_Bits.ACT_CMUFX0 */
#define IFX_GTM_MON_STATUS_ACT_CMUFX0_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MON_STATUS_Bits.ACT_CMUFX0 */
#define IFX_GTM_MON_STATUS_ACT_CMUFX0_OFF (8u)

/** \brief  Length for Ifx_GTM_MON_STATUS_Bits.ACT_CMUFX1 */
#define IFX_GTM_MON_STATUS_ACT_CMUFX1_LEN (1u)

/** \brief  Mask for Ifx_GTM_MON_STATUS_Bits.ACT_CMUFX1 */
#define IFX_GTM_MON_STATUS_ACT_CMUFX1_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MON_STATUS_Bits.ACT_CMUFX1 */
#define IFX_GTM_MON_STATUS_ACT_CMUFX1_OFF (9u)

/** \brief  Length for Ifx_GTM_MON_STATUS_Bits.ACT_CMUFX2 */
#define IFX_GTM_MON_STATUS_ACT_CMUFX2_LEN (1u)

/** \brief  Mask for Ifx_GTM_MON_STATUS_Bits.ACT_CMUFX2 */
#define IFX_GTM_MON_STATUS_ACT_CMUFX2_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MON_STATUS_Bits.ACT_CMUFX2 */
#define IFX_GTM_MON_STATUS_ACT_CMUFX2_OFF (10u)

/** \brief  Length for Ifx_GTM_MON_STATUS_Bits.ACT_CMUFX3 */
#define IFX_GTM_MON_STATUS_ACT_CMUFX3_LEN (1u)

/** \brief  Mask for Ifx_GTM_MON_STATUS_Bits.ACT_CMUFX3 */
#define IFX_GTM_MON_STATUS_ACT_CMUFX3_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MON_STATUS_Bits.ACT_CMUFX3 */
#define IFX_GTM_MON_STATUS_ACT_CMUFX3_OFF (11u)

/** \brief  Length for Ifx_GTM_MON_STATUS_Bits.ACT_CMUFX4 */
#define IFX_GTM_MON_STATUS_ACT_CMUFX4_LEN (1u)

/** \brief  Mask for Ifx_GTM_MON_STATUS_Bits.ACT_CMUFX4 */
#define IFX_GTM_MON_STATUS_ACT_CMUFX4_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MON_STATUS_Bits.ACT_CMUFX4 */
#define IFX_GTM_MON_STATUS_ACT_CMUFX4_OFF (12u)

/** \brief  Length for Ifx_GTM_MON_STATUS_Bits.CMP_ERR */
#define IFX_GTM_MON_STATUS_CMP_ERR_LEN (1u)

/** \brief  Mask for Ifx_GTM_MON_STATUS_Bits.CMP_ERR */
#define IFX_GTM_MON_STATUS_CMP_ERR_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MON_STATUS_Bits.CMP_ERR */
#define IFX_GTM_MON_STATUS_CMP_ERR_OFF (16u)

/** \brief  Length for Ifx_GTM_MON_STATUS_Bits.MCS0_ERR */
#define IFX_GTM_MON_STATUS_MCS0_ERR_LEN (1u)

/** \brief  Mask for Ifx_GTM_MON_STATUS_Bits.MCS0_ERR */
#define IFX_GTM_MON_STATUS_MCS0_ERR_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MON_STATUS_Bits.MCS0_ERR */
#define IFX_GTM_MON_STATUS_MCS0_ERR_OFF (20u)

/** \brief  Length for Ifx_GTM_MON_STATUS_Bits.MCS1_ERR */
#define IFX_GTM_MON_STATUS_MCS1_ERR_LEN (1u)

/** \brief  Mask for Ifx_GTM_MON_STATUS_Bits.MCS1_ERR */
#define IFX_GTM_MON_STATUS_MCS1_ERR_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MON_STATUS_Bits.MCS1_ERR */
#define IFX_GTM_MON_STATUS_MCS1_ERR_OFF (21u)

/** \brief  Length for Ifx_GTM_MON_STATUS_Bits.MCS2_ERR */
#define IFX_GTM_MON_STATUS_MCS2_ERR_LEN (1u)

/** \brief  Mask for Ifx_GTM_MON_STATUS_Bits.MCS2_ERR */
#define IFX_GTM_MON_STATUS_MCS2_ERR_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_MON_STATUS_Bits.MCS2_ERR */
#define IFX_GTM_MON_STATUS_MCS2_ERR_OFF (22u)

/** \brief  Length for Ifx_GTM_MSC0INLEXTCON_Bits.SEL0 */
#define IFX_GTM_MSC0INLEXTCON_SEL0_LEN (2u)

/** \brief  Mask for Ifx_GTM_MSC0INLEXTCON_Bits.SEL0 */
#define IFX_GTM_MSC0INLEXTCON_SEL0_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_MSC0INLEXTCON_Bits.SEL0 */
#define IFX_GTM_MSC0INLEXTCON_SEL0_OFF (0u)

/** \brief  Length for Ifx_GTM_MSC0INLEXTCON_Bits.SEL10 */
#define IFX_GTM_MSC0INLEXTCON_SEL10_LEN (2u)

/** \brief  Mask for Ifx_GTM_MSC0INLEXTCON_Bits.SEL10 */
#define IFX_GTM_MSC0INLEXTCON_SEL10_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_MSC0INLEXTCON_Bits.SEL10 */
#define IFX_GTM_MSC0INLEXTCON_SEL10_OFF (20u)

/** \brief  Length for Ifx_GTM_MSC0INLEXTCON_Bits.SEL11 */
#define IFX_GTM_MSC0INLEXTCON_SEL11_LEN (2u)

/** \brief  Mask for Ifx_GTM_MSC0INLEXTCON_Bits.SEL11 */
#define IFX_GTM_MSC0INLEXTCON_SEL11_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_MSC0INLEXTCON_Bits.SEL11 */
#define IFX_GTM_MSC0INLEXTCON_SEL11_OFF (22u)

/** \brief  Length for Ifx_GTM_MSC0INLEXTCON_Bits.SEL12 */
#define IFX_GTM_MSC0INLEXTCON_SEL12_LEN (2u)

/** \brief  Mask for Ifx_GTM_MSC0INLEXTCON_Bits.SEL12 */
#define IFX_GTM_MSC0INLEXTCON_SEL12_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_MSC0INLEXTCON_Bits.SEL12 */
#define IFX_GTM_MSC0INLEXTCON_SEL12_OFF (24u)

/** \brief  Length for Ifx_GTM_MSC0INLEXTCON_Bits.SEL13 */
#define IFX_GTM_MSC0INLEXTCON_SEL13_LEN (2u)

/** \brief  Mask for Ifx_GTM_MSC0INLEXTCON_Bits.SEL13 */
#define IFX_GTM_MSC0INLEXTCON_SEL13_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_MSC0INLEXTCON_Bits.SEL13 */
#define IFX_GTM_MSC0INLEXTCON_SEL13_OFF (26u)

/** \brief  Length for Ifx_GTM_MSC0INLEXTCON_Bits.SEL14 */
#define IFX_GTM_MSC0INLEXTCON_SEL14_LEN (2u)

/** \brief  Mask for Ifx_GTM_MSC0INLEXTCON_Bits.SEL14 */
#define IFX_GTM_MSC0INLEXTCON_SEL14_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_MSC0INLEXTCON_Bits.SEL14 */
#define IFX_GTM_MSC0INLEXTCON_SEL14_OFF (28u)

/** \brief  Length for Ifx_GTM_MSC0INLEXTCON_Bits.SEL15 */
#define IFX_GTM_MSC0INLEXTCON_SEL15_LEN (2u)

/** \brief  Mask for Ifx_GTM_MSC0INLEXTCON_Bits.SEL15 */
#define IFX_GTM_MSC0INLEXTCON_SEL15_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_MSC0INLEXTCON_Bits.SEL15 */
#define IFX_GTM_MSC0INLEXTCON_SEL15_OFF (30u)

/** \brief  Length for Ifx_GTM_MSC0INLEXTCON_Bits.SEL1 */
#define IFX_GTM_MSC0INLEXTCON_SEL1_LEN (2u)

/** \brief  Mask for Ifx_GTM_MSC0INLEXTCON_Bits.SEL1 */
#define IFX_GTM_MSC0INLEXTCON_SEL1_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_MSC0INLEXTCON_Bits.SEL1 */
#define IFX_GTM_MSC0INLEXTCON_SEL1_OFF (2u)

/** \brief  Length for Ifx_GTM_MSC0INLEXTCON_Bits.SEL2 */
#define IFX_GTM_MSC0INLEXTCON_SEL2_LEN (2u)

/** \brief  Mask for Ifx_GTM_MSC0INLEXTCON_Bits.SEL2 */
#define IFX_GTM_MSC0INLEXTCON_SEL2_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_MSC0INLEXTCON_Bits.SEL2 */
#define IFX_GTM_MSC0INLEXTCON_SEL2_OFF (4u)

/** \brief  Length for Ifx_GTM_MSC0INLEXTCON_Bits.SEL3 */
#define IFX_GTM_MSC0INLEXTCON_SEL3_LEN (2u)

/** \brief  Mask for Ifx_GTM_MSC0INLEXTCON_Bits.SEL3 */
#define IFX_GTM_MSC0INLEXTCON_SEL3_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_MSC0INLEXTCON_Bits.SEL3 */
#define IFX_GTM_MSC0INLEXTCON_SEL3_OFF (6u)

/** \brief  Length for Ifx_GTM_MSC0INLEXTCON_Bits.SEL4 */
#define IFX_GTM_MSC0INLEXTCON_SEL4_LEN (2u)

/** \brief  Mask for Ifx_GTM_MSC0INLEXTCON_Bits.SEL4 */
#define IFX_GTM_MSC0INLEXTCON_SEL4_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_MSC0INLEXTCON_Bits.SEL4 */
#define IFX_GTM_MSC0INLEXTCON_SEL4_OFF (8u)

/** \brief  Length for Ifx_GTM_MSC0INLEXTCON_Bits.SEL5 */
#define IFX_GTM_MSC0INLEXTCON_SEL5_LEN (2u)

/** \brief  Mask for Ifx_GTM_MSC0INLEXTCON_Bits.SEL5 */
#define IFX_GTM_MSC0INLEXTCON_SEL5_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_MSC0INLEXTCON_Bits.SEL5 */
#define IFX_GTM_MSC0INLEXTCON_SEL5_OFF (10u)

/** \brief  Length for Ifx_GTM_MSC0INLEXTCON_Bits.SEL6 */
#define IFX_GTM_MSC0INLEXTCON_SEL6_LEN (2u)

/** \brief  Mask for Ifx_GTM_MSC0INLEXTCON_Bits.SEL6 */
#define IFX_GTM_MSC0INLEXTCON_SEL6_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_MSC0INLEXTCON_Bits.SEL6 */
#define IFX_GTM_MSC0INLEXTCON_SEL6_OFF (12u)

/** \brief  Length for Ifx_GTM_MSC0INLEXTCON_Bits.SEL7 */
#define IFX_GTM_MSC0INLEXTCON_SEL7_LEN (2u)

/** \brief  Mask for Ifx_GTM_MSC0INLEXTCON_Bits.SEL7 */
#define IFX_GTM_MSC0INLEXTCON_SEL7_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_MSC0INLEXTCON_Bits.SEL7 */
#define IFX_GTM_MSC0INLEXTCON_SEL7_OFF (14u)

/** \brief  Length for Ifx_GTM_MSC0INLEXTCON_Bits.SEL8 */
#define IFX_GTM_MSC0INLEXTCON_SEL8_LEN (2u)

/** \brief  Mask for Ifx_GTM_MSC0INLEXTCON_Bits.SEL8 */
#define IFX_GTM_MSC0INLEXTCON_SEL8_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_MSC0INLEXTCON_Bits.SEL8 */
#define IFX_GTM_MSC0INLEXTCON_SEL8_OFF (16u)

/** \brief  Length for Ifx_GTM_MSC0INLEXTCON_Bits.SEL9 */
#define IFX_GTM_MSC0INLEXTCON_SEL9_LEN (2u)

/** \brief  Mask for Ifx_GTM_MSC0INLEXTCON_Bits.SEL9 */
#define IFX_GTM_MSC0INLEXTCON_SEL9_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_MSC0INLEXTCON_Bits.SEL9 */
#define IFX_GTM_MSC0INLEXTCON_SEL9_OFF (18u)

/** \brief  Length for Ifx_GTM_MSCIN_INHCON_Bits.SEL0 */
#define IFX_GTM_MSCIN_INHCON_SEL0_LEN (2u)

/** \brief  Mask for Ifx_GTM_MSCIN_INHCON_Bits.SEL0 */
#define IFX_GTM_MSCIN_INHCON_SEL0_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_MSCIN_INHCON_Bits.SEL0 */
#define IFX_GTM_MSCIN_INHCON_SEL0_OFF (0u)

/** \brief  Length for Ifx_GTM_MSCIN_INHCON_Bits.SEL10 */
#define IFX_GTM_MSCIN_INHCON_SEL10_LEN (2u)

/** \brief  Mask for Ifx_GTM_MSCIN_INHCON_Bits.SEL10 */
#define IFX_GTM_MSCIN_INHCON_SEL10_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_MSCIN_INHCON_Bits.SEL10 */
#define IFX_GTM_MSCIN_INHCON_SEL10_OFF (20u)

/** \brief  Length for Ifx_GTM_MSCIN_INHCON_Bits.SEL11 */
#define IFX_GTM_MSCIN_INHCON_SEL11_LEN (2u)

/** \brief  Mask for Ifx_GTM_MSCIN_INHCON_Bits.SEL11 */
#define IFX_GTM_MSCIN_INHCON_SEL11_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_MSCIN_INHCON_Bits.SEL11 */
#define IFX_GTM_MSCIN_INHCON_SEL11_OFF (22u)

/** \brief  Length for Ifx_GTM_MSCIN_INHCON_Bits.SEL12 */
#define IFX_GTM_MSCIN_INHCON_SEL12_LEN (2u)

/** \brief  Mask for Ifx_GTM_MSCIN_INHCON_Bits.SEL12 */
#define IFX_GTM_MSCIN_INHCON_SEL12_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_MSCIN_INHCON_Bits.SEL12 */
#define IFX_GTM_MSCIN_INHCON_SEL12_OFF (24u)

/** \brief  Length for Ifx_GTM_MSCIN_INHCON_Bits.SEL13 */
#define IFX_GTM_MSCIN_INHCON_SEL13_LEN (2u)

/** \brief  Mask for Ifx_GTM_MSCIN_INHCON_Bits.SEL13 */
#define IFX_GTM_MSCIN_INHCON_SEL13_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_MSCIN_INHCON_Bits.SEL13 */
#define IFX_GTM_MSCIN_INHCON_SEL13_OFF (26u)

/** \brief  Length for Ifx_GTM_MSCIN_INHCON_Bits.SEL14 */
#define IFX_GTM_MSCIN_INHCON_SEL14_LEN (2u)

/** \brief  Mask for Ifx_GTM_MSCIN_INHCON_Bits.SEL14 */
#define IFX_GTM_MSCIN_INHCON_SEL14_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_MSCIN_INHCON_Bits.SEL14 */
#define IFX_GTM_MSCIN_INHCON_SEL14_OFF (28u)

/** \brief  Length for Ifx_GTM_MSCIN_INHCON_Bits.SEL15 */
#define IFX_GTM_MSCIN_INHCON_SEL15_LEN (2u)

/** \brief  Mask for Ifx_GTM_MSCIN_INHCON_Bits.SEL15 */
#define IFX_GTM_MSCIN_INHCON_SEL15_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_MSCIN_INHCON_Bits.SEL15 */
#define IFX_GTM_MSCIN_INHCON_SEL15_OFF (30u)

/** \brief  Length for Ifx_GTM_MSCIN_INHCON_Bits.SEL1 */
#define IFX_GTM_MSCIN_INHCON_SEL1_LEN (2u)

/** \brief  Mask for Ifx_GTM_MSCIN_INHCON_Bits.SEL1 */
#define IFX_GTM_MSCIN_INHCON_SEL1_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_MSCIN_INHCON_Bits.SEL1 */
#define IFX_GTM_MSCIN_INHCON_SEL1_OFF (2u)

/** \brief  Length for Ifx_GTM_MSCIN_INHCON_Bits.SEL2 */
#define IFX_GTM_MSCIN_INHCON_SEL2_LEN (2u)

/** \brief  Mask for Ifx_GTM_MSCIN_INHCON_Bits.SEL2 */
#define IFX_GTM_MSCIN_INHCON_SEL2_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_MSCIN_INHCON_Bits.SEL2 */
#define IFX_GTM_MSCIN_INHCON_SEL2_OFF (4u)

/** \brief  Length for Ifx_GTM_MSCIN_INHCON_Bits.SEL3 */
#define IFX_GTM_MSCIN_INHCON_SEL3_LEN (2u)

/** \brief  Mask for Ifx_GTM_MSCIN_INHCON_Bits.SEL3 */
#define IFX_GTM_MSCIN_INHCON_SEL3_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_MSCIN_INHCON_Bits.SEL3 */
#define IFX_GTM_MSCIN_INHCON_SEL3_OFF (6u)

/** \brief  Length for Ifx_GTM_MSCIN_INHCON_Bits.SEL4 */
#define IFX_GTM_MSCIN_INHCON_SEL4_LEN (2u)

/** \brief  Mask for Ifx_GTM_MSCIN_INHCON_Bits.SEL4 */
#define IFX_GTM_MSCIN_INHCON_SEL4_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_MSCIN_INHCON_Bits.SEL4 */
#define IFX_GTM_MSCIN_INHCON_SEL4_OFF (8u)

/** \brief  Length for Ifx_GTM_MSCIN_INHCON_Bits.SEL5 */
#define IFX_GTM_MSCIN_INHCON_SEL5_LEN (2u)

/** \brief  Mask for Ifx_GTM_MSCIN_INHCON_Bits.SEL5 */
#define IFX_GTM_MSCIN_INHCON_SEL5_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_MSCIN_INHCON_Bits.SEL5 */
#define IFX_GTM_MSCIN_INHCON_SEL5_OFF (10u)

/** \brief  Length for Ifx_GTM_MSCIN_INHCON_Bits.SEL6 */
#define IFX_GTM_MSCIN_INHCON_SEL6_LEN (2u)

/** \brief  Mask for Ifx_GTM_MSCIN_INHCON_Bits.SEL6 */
#define IFX_GTM_MSCIN_INHCON_SEL6_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_MSCIN_INHCON_Bits.SEL6 */
#define IFX_GTM_MSCIN_INHCON_SEL6_OFF (12u)

/** \brief  Length for Ifx_GTM_MSCIN_INHCON_Bits.SEL7 */
#define IFX_GTM_MSCIN_INHCON_SEL7_LEN (2u)

/** \brief  Mask for Ifx_GTM_MSCIN_INHCON_Bits.SEL7 */
#define IFX_GTM_MSCIN_INHCON_SEL7_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_MSCIN_INHCON_Bits.SEL7 */
#define IFX_GTM_MSCIN_INHCON_SEL7_OFF (14u)

/** \brief  Length for Ifx_GTM_MSCIN_INHCON_Bits.SEL8 */
#define IFX_GTM_MSCIN_INHCON_SEL8_LEN (2u)

/** \brief  Mask for Ifx_GTM_MSCIN_INHCON_Bits.SEL8 */
#define IFX_GTM_MSCIN_INHCON_SEL8_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_MSCIN_INHCON_Bits.SEL8 */
#define IFX_GTM_MSCIN_INHCON_SEL8_OFF (16u)

/** \brief  Length for Ifx_GTM_MSCIN_INHCON_Bits.SEL9 */
#define IFX_GTM_MSCIN_INHCON_SEL9_LEN (2u)

/** \brief  Mask for Ifx_GTM_MSCIN_INHCON_Bits.SEL9 */
#define IFX_GTM_MSCIN_INHCON_SEL9_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_MSCIN_INHCON_Bits.SEL9 */
#define IFX_GTM_MSCIN_INHCON_SEL9_OFF (18u)

/** \brief  Length for Ifx_GTM_MSCIN_INLCON_Bits.SEL0 */
#define IFX_GTM_MSCIN_INLCON_SEL0_LEN (2u)

/** \brief  Mask for Ifx_GTM_MSCIN_INLCON_Bits.SEL0 */
#define IFX_GTM_MSCIN_INLCON_SEL0_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_MSCIN_INLCON_Bits.SEL0 */
#define IFX_GTM_MSCIN_INLCON_SEL0_OFF (0u)

/** \brief  Length for Ifx_GTM_MSCIN_INLCON_Bits.SEL10 */
#define IFX_GTM_MSCIN_INLCON_SEL10_LEN (2u)

/** \brief  Mask for Ifx_GTM_MSCIN_INLCON_Bits.SEL10 */
#define IFX_GTM_MSCIN_INLCON_SEL10_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_MSCIN_INLCON_Bits.SEL10 */
#define IFX_GTM_MSCIN_INLCON_SEL10_OFF (20u)

/** \brief  Length for Ifx_GTM_MSCIN_INLCON_Bits.SEL11 */
#define IFX_GTM_MSCIN_INLCON_SEL11_LEN (2u)

/** \brief  Mask for Ifx_GTM_MSCIN_INLCON_Bits.SEL11 */
#define IFX_GTM_MSCIN_INLCON_SEL11_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_MSCIN_INLCON_Bits.SEL11 */
#define IFX_GTM_MSCIN_INLCON_SEL11_OFF (22u)

/** \brief  Length for Ifx_GTM_MSCIN_INLCON_Bits.SEL12 */
#define IFX_GTM_MSCIN_INLCON_SEL12_LEN (2u)

/** \brief  Mask for Ifx_GTM_MSCIN_INLCON_Bits.SEL12 */
#define IFX_GTM_MSCIN_INLCON_SEL12_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_MSCIN_INLCON_Bits.SEL12 */
#define IFX_GTM_MSCIN_INLCON_SEL12_OFF (24u)

/** \brief  Length for Ifx_GTM_MSCIN_INLCON_Bits.SEL13 */
#define IFX_GTM_MSCIN_INLCON_SEL13_LEN (2u)

/** \brief  Mask for Ifx_GTM_MSCIN_INLCON_Bits.SEL13 */
#define IFX_GTM_MSCIN_INLCON_SEL13_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_MSCIN_INLCON_Bits.SEL13 */
#define IFX_GTM_MSCIN_INLCON_SEL13_OFF (26u)

/** \brief  Length for Ifx_GTM_MSCIN_INLCON_Bits.SEL14 */
#define IFX_GTM_MSCIN_INLCON_SEL14_LEN (2u)

/** \brief  Mask for Ifx_GTM_MSCIN_INLCON_Bits.SEL14 */
#define IFX_GTM_MSCIN_INLCON_SEL14_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_MSCIN_INLCON_Bits.SEL14 */
#define IFX_GTM_MSCIN_INLCON_SEL14_OFF (28u)

/** \brief  Length for Ifx_GTM_MSCIN_INLCON_Bits.SEL15 */
#define IFX_GTM_MSCIN_INLCON_SEL15_LEN (2u)

/** \brief  Mask for Ifx_GTM_MSCIN_INLCON_Bits.SEL15 */
#define IFX_GTM_MSCIN_INLCON_SEL15_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_MSCIN_INLCON_Bits.SEL15 */
#define IFX_GTM_MSCIN_INLCON_SEL15_OFF (30u)

/** \brief  Length for Ifx_GTM_MSCIN_INLCON_Bits.SEL1 */
#define IFX_GTM_MSCIN_INLCON_SEL1_LEN (2u)

/** \brief  Mask for Ifx_GTM_MSCIN_INLCON_Bits.SEL1 */
#define IFX_GTM_MSCIN_INLCON_SEL1_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_MSCIN_INLCON_Bits.SEL1 */
#define IFX_GTM_MSCIN_INLCON_SEL1_OFF (2u)

/** \brief  Length for Ifx_GTM_MSCIN_INLCON_Bits.SEL2 */
#define IFX_GTM_MSCIN_INLCON_SEL2_LEN (2u)

/** \brief  Mask for Ifx_GTM_MSCIN_INLCON_Bits.SEL2 */
#define IFX_GTM_MSCIN_INLCON_SEL2_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_MSCIN_INLCON_Bits.SEL2 */
#define IFX_GTM_MSCIN_INLCON_SEL2_OFF (4u)

/** \brief  Length for Ifx_GTM_MSCIN_INLCON_Bits.SEL3 */
#define IFX_GTM_MSCIN_INLCON_SEL3_LEN (2u)

/** \brief  Mask for Ifx_GTM_MSCIN_INLCON_Bits.SEL3 */
#define IFX_GTM_MSCIN_INLCON_SEL3_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_MSCIN_INLCON_Bits.SEL3 */
#define IFX_GTM_MSCIN_INLCON_SEL3_OFF (6u)

/** \brief  Length for Ifx_GTM_MSCIN_INLCON_Bits.SEL4 */
#define IFX_GTM_MSCIN_INLCON_SEL4_LEN (2u)

/** \brief  Mask for Ifx_GTM_MSCIN_INLCON_Bits.SEL4 */
#define IFX_GTM_MSCIN_INLCON_SEL4_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_MSCIN_INLCON_Bits.SEL4 */
#define IFX_GTM_MSCIN_INLCON_SEL4_OFF (8u)

/** \brief  Length for Ifx_GTM_MSCIN_INLCON_Bits.SEL5 */
#define IFX_GTM_MSCIN_INLCON_SEL5_LEN (2u)

/** \brief  Mask for Ifx_GTM_MSCIN_INLCON_Bits.SEL5 */
#define IFX_GTM_MSCIN_INLCON_SEL5_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_MSCIN_INLCON_Bits.SEL5 */
#define IFX_GTM_MSCIN_INLCON_SEL5_OFF (10u)

/** \brief  Length for Ifx_GTM_MSCIN_INLCON_Bits.SEL6 */
#define IFX_GTM_MSCIN_INLCON_SEL6_LEN (2u)

/** \brief  Mask for Ifx_GTM_MSCIN_INLCON_Bits.SEL6 */
#define IFX_GTM_MSCIN_INLCON_SEL6_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_MSCIN_INLCON_Bits.SEL6 */
#define IFX_GTM_MSCIN_INLCON_SEL6_OFF (12u)

/** \brief  Length for Ifx_GTM_MSCIN_INLCON_Bits.SEL7 */
#define IFX_GTM_MSCIN_INLCON_SEL7_LEN (2u)

/** \brief  Mask for Ifx_GTM_MSCIN_INLCON_Bits.SEL7 */
#define IFX_GTM_MSCIN_INLCON_SEL7_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_MSCIN_INLCON_Bits.SEL7 */
#define IFX_GTM_MSCIN_INLCON_SEL7_OFF (14u)

/** \brief  Length for Ifx_GTM_MSCIN_INLCON_Bits.SEL8 */
#define IFX_GTM_MSCIN_INLCON_SEL8_LEN (2u)

/** \brief  Mask for Ifx_GTM_MSCIN_INLCON_Bits.SEL8 */
#define IFX_GTM_MSCIN_INLCON_SEL8_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_MSCIN_INLCON_Bits.SEL8 */
#define IFX_GTM_MSCIN_INLCON_SEL8_OFF (16u)

/** \brief  Length for Ifx_GTM_MSCIN_INLCON_Bits.SEL9 */
#define IFX_GTM_MSCIN_INLCON_SEL9_LEN (2u)

/** \brief  Mask for Ifx_GTM_MSCIN_INLCON_Bits.SEL9 */
#define IFX_GTM_MSCIN_INLCON_SEL9_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_MSCIN_INLCON_Bits.SEL9 */
#define IFX_GTM_MSCIN_INLCON_SEL9_OFF (18u)

/** \brief  Length for Ifx_GTM_MSCSET_CON0_Bits.SEL0 */
#define IFX_GTM_MSCSET_CON0_SEL0_LEN (5u)

/** \brief  Mask for Ifx_GTM_MSCSET_CON0_Bits.SEL0 */
#define IFX_GTM_MSCSET_CON0_SEL0_MSK (0x1fu)

/** \brief  Offset for Ifx_GTM_MSCSET_CON0_Bits.SEL0 */
#define IFX_GTM_MSCSET_CON0_SEL0_OFF (0u)

/** \brief  Length for Ifx_GTM_MSCSET_CON0_Bits.SEL1 */
#define IFX_GTM_MSCSET_CON0_SEL1_LEN (5u)

/** \brief  Mask for Ifx_GTM_MSCSET_CON0_Bits.SEL1 */
#define IFX_GTM_MSCSET_CON0_SEL1_MSK (0x1fu)

/** \brief  Offset for Ifx_GTM_MSCSET_CON0_Bits.SEL1 */
#define IFX_GTM_MSCSET_CON0_SEL1_OFF (8u)

/** \brief  Length for Ifx_GTM_MSCSET_CON0_Bits.SEL2 */
#define IFX_GTM_MSCSET_CON0_SEL2_LEN (5u)

/** \brief  Mask for Ifx_GTM_MSCSET_CON0_Bits.SEL2 */
#define IFX_GTM_MSCSET_CON0_SEL2_MSK (0x1fu)

/** \brief  Offset for Ifx_GTM_MSCSET_CON0_Bits.SEL2 */
#define IFX_GTM_MSCSET_CON0_SEL2_OFF (16u)

/** \brief  Length for Ifx_GTM_MSCSET_CON0_Bits.SEL3 */
#define IFX_GTM_MSCSET_CON0_SEL3_LEN (5u)

/** \brief  Mask for Ifx_GTM_MSCSET_CON0_Bits.SEL3 */
#define IFX_GTM_MSCSET_CON0_SEL3_MSK (0x1fu)

/** \brief  Offset for Ifx_GTM_MSCSET_CON0_Bits.SEL3 */
#define IFX_GTM_MSCSET_CON0_SEL3_OFF (24u)

/** \brief  Length for Ifx_GTM_MSCSET_CON1_Bits.SEL4 */
#define IFX_GTM_MSCSET_CON1_SEL4_LEN (5u)

/** \brief  Mask for Ifx_GTM_MSCSET_CON1_Bits.SEL4 */
#define IFX_GTM_MSCSET_CON1_SEL4_MSK (0x1fu)

/** \brief  Offset for Ifx_GTM_MSCSET_CON1_Bits.SEL4 */
#define IFX_GTM_MSCSET_CON1_SEL4_OFF (0u)

/** \brief  Length for Ifx_GTM_MSCSET_CON1_Bits.SEL5 */
#define IFX_GTM_MSCSET_CON1_SEL5_LEN (5u)

/** \brief  Mask for Ifx_GTM_MSCSET_CON1_Bits.SEL5 */
#define IFX_GTM_MSCSET_CON1_SEL5_MSK (0x1fu)

/** \brief  Offset for Ifx_GTM_MSCSET_CON1_Bits.SEL5 */
#define IFX_GTM_MSCSET_CON1_SEL5_OFF (8u)

/** \brief  Length for Ifx_GTM_MSCSET_CON1_Bits.SEL6 */
#define IFX_GTM_MSCSET_CON1_SEL6_LEN (5u)

/** \brief  Mask for Ifx_GTM_MSCSET_CON1_Bits.SEL6 */
#define IFX_GTM_MSCSET_CON1_SEL6_MSK (0x1fu)

/** \brief  Offset for Ifx_GTM_MSCSET_CON1_Bits.SEL6 */
#define IFX_GTM_MSCSET_CON1_SEL6_OFF (16u)

/** \brief  Length for Ifx_GTM_MSCSET_CON1_Bits.SEL7 */
#define IFX_GTM_MSCSET_CON1_SEL7_LEN (5u)

/** \brief  Mask for Ifx_GTM_MSCSET_CON1_Bits.SEL7 */
#define IFX_GTM_MSCSET_CON1_SEL7_MSK (0x1fu)

/** \brief  Offset for Ifx_GTM_MSCSET_CON1_Bits.SEL7 */
#define IFX_GTM_MSCSET_CON1_SEL7_OFF (24u)

/** \brief  Length for Ifx_GTM_MSCSET_CON2_Bits.SEL10 */
#define IFX_GTM_MSCSET_CON2_SEL10_LEN (5u)

/** \brief  Mask for Ifx_GTM_MSCSET_CON2_Bits.SEL10 */
#define IFX_GTM_MSCSET_CON2_SEL10_MSK (0x1fu)

/** \brief  Offset for Ifx_GTM_MSCSET_CON2_Bits.SEL10 */
#define IFX_GTM_MSCSET_CON2_SEL10_OFF (16u)

/** \brief  Length for Ifx_GTM_MSCSET_CON2_Bits.SEL11 */
#define IFX_GTM_MSCSET_CON2_SEL11_LEN (5u)

/** \brief  Mask for Ifx_GTM_MSCSET_CON2_Bits.SEL11 */
#define IFX_GTM_MSCSET_CON2_SEL11_MSK (0x1fu)

/** \brief  Offset for Ifx_GTM_MSCSET_CON2_Bits.SEL11 */
#define IFX_GTM_MSCSET_CON2_SEL11_OFF (24u)

/** \brief  Length for Ifx_GTM_MSCSET_CON2_Bits.SEL8 */
#define IFX_GTM_MSCSET_CON2_SEL8_LEN (5u)

/** \brief  Mask for Ifx_GTM_MSCSET_CON2_Bits.SEL8 */
#define IFX_GTM_MSCSET_CON2_SEL8_MSK (0x1fu)

/** \brief  Offset for Ifx_GTM_MSCSET_CON2_Bits.SEL8 */
#define IFX_GTM_MSCSET_CON2_SEL8_OFF (0u)

/** \brief  Length for Ifx_GTM_MSCSET_CON2_Bits.SEL9 */
#define IFX_GTM_MSCSET_CON2_SEL9_LEN (5u)

/** \brief  Mask for Ifx_GTM_MSCSET_CON2_Bits.SEL9 */
#define IFX_GTM_MSCSET_CON2_SEL9_MSK (0x1fu)

/** \brief  Offset for Ifx_GTM_MSCSET_CON2_Bits.SEL9 */
#define IFX_GTM_MSCSET_CON2_SEL9_OFF (8u)

/** \brief  Length for Ifx_GTM_MSCSET_CON3_Bits.SEL12 */
#define IFX_GTM_MSCSET_CON3_SEL12_LEN (5u)

/** \brief  Mask for Ifx_GTM_MSCSET_CON3_Bits.SEL12 */
#define IFX_GTM_MSCSET_CON3_SEL12_MSK (0x1fu)

/** \brief  Offset for Ifx_GTM_MSCSET_CON3_Bits.SEL12 */
#define IFX_GTM_MSCSET_CON3_SEL12_OFF (0u)

/** \brief  Length for Ifx_GTM_MSCSET_CON3_Bits.SEL13 */
#define IFX_GTM_MSCSET_CON3_SEL13_LEN (5u)

/** \brief  Mask for Ifx_GTM_MSCSET_CON3_Bits.SEL13 */
#define IFX_GTM_MSCSET_CON3_SEL13_MSK (0x1fu)

/** \brief  Offset for Ifx_GTM_MSCSET_CON3_Bits.SEL13 */
#define IFX_GTM_MSCSET_CON3_SEL13_OFF (8u)

/** \brief  Length for Ifx_GTM_MSCSET_CON3_Bits.SEL14 */
#define IFX_GTM_MSCSET_CON3_SEL14_LEN (5u)

/** \brief  Mask for Ifx_GTM_MSCSET_CON3_Bits.SEL14 */
#define IFX_GTM_MSCSET_CON3_SEL14_MSK (0x1fu)

/** \brief  Offset for Ifx_GTM_MSCSET_CON3_Bits.SEL14 */
#define IFX_GTM_MSCSET_CON3_SEL14_OFF (16u)

/** \brief  Length for Ifx_GTM_MSCSET_CON3_Bits.SEL15 */
#define IFX_GTM_MSCSET_CON3_SEL15_LEN (5u)

/** \brief  Mask for Ifx_GTM_MSCSET_CON3_Bits.SEL15 */
#define IFX_GTM_MSCSET_CON3_SEL15_MSK (0x1fu)

/** \brief  Offset for Ifx_GTM_MSCSET_CON3_Bits.SEL15 */
#define IFX_GTM_MSCSET_CON3_SEL15_OFF (24u)

/** \brief  Length for Ifx_GTM_OCS_Bits.SUS */
#define IFX_GTM_OCS_SUS_LEN (4u)

/** \brief  Mask for Ifx_GTM_OCS_Bits.SUS */
#define IFX_GTM_OCS_SUS_MSK (0xfu)

/** \brief  Offset for Ifx_GTM_OCS_Bits.SUS */
#define IFX_GTM_OCS_SUS_OFF (24u)

/** \brief  Length for Ifx_GTM_OCS_Bits.SUS_P */
#define IFX_GTM_OCS_SUS_P_LEN (1u)

/** \brief  Mask for Ifx_GTM_OCS_Bits.SUS_P */
#define IFX_GTM_OCS_SUS_P_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_OCS_Bits.SUS_P */
#define IFX_GTM_OCS_SUS_P_OFF (28u)

/** \brief  Length for Ifx_GTM_OCS_Bits.SUSSTA */
#define IFX_GTM_OCS_SUSSTA_LEN (1u)

/** \brief  Mask for Ifx_GTM_OCS_Bits.SUSSTA */
#define IFX_GTM_OCS_SUSSTA_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_OCS_Bits.SUSSTA */
#define IFX_GTM_OCS_SUSSTA_OFF (29u)

/** \brief  Length for Ifx_GTM_ODA_Bits.DDREN */
#define IFX_GTM_ODA_DDREN_LEN (1u)

/** \brief  Mask for Ifx_GTM_ODA_Bits.DDREN */
#define IFX_GTM_ODA_DDREN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ODA_Bits.DDREN */
#define IFX_GTM_ODA_DDREN_OFF (0u)

/** \brief  Length for Ifx_GTM_ODA_Bits.DREN */
#define IFX_GTM_ODA_DREN_LEN (1u)

/** \brief  Mask for Ifx_GTM_ODA_Bits.DREN */
#define IFX_GTM_ODA_DREN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_ODA_Bits.DREN */
#define IFX_GTM_ODA_DREN_OFF (1u)

/** \brief  Length for Ifx_GTM_OTBU0T_Bits.CM */
#define IFX_GTM_OTBU0T_CM_LEN (2u)

/** \brief  Mask for Ifx_GTM_OTBU0T_Bits.CM */
#define IFX_GTM_OTBU0T_CM_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_OTBU0T_Bits.CM */
#define IFX_GTM_OTBU0T_CM_OFF (28u)

/** \brief  Length for Ifx_GTM_OTBU0T_Bits.CV */
#define IFX_GTM_OTBU0T_CV_LEN (27u)

/** \brief  Mask for Ifx_GTM_OTBU0T_Bits.CV */
#define IFX_GTM_OTBU0T_CV_MSK (0x7ffffffu)

/** \brief  Offset for Ifx_GTM_OTBU0T_Bits.CV */
#define IFX_GTM_OTBU0T_CV_OFF (0u)

/** \brief  Length for Ifx_GTM_OTBU1T_Bits.CV */
#define IFX_GTM_OTBU1T_CV_LEN (24u)

/** \brief  Mask for Ifx_GTM_OTBU1T_Bits.CV */
#define IFX_GTM_OTBU1T_CV_MSK (0xffffffu)

/** \brief  Offset for Ifx_GTM_OTBU1T_Bits.CV */
#define IFX_GTM_OTBU1T_CV_OFF (0u)

/** \brief  Length for Ifx_GTM_OTBU1T_Bits.EN */
#define IFX_GTM_OTBU1T_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_OTBU1T_Bits.EN */
#define IFX_GTM_OTBU1T_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_OTBU1T_Bits.EN */
#define IFX_GTM_OTBU1T_EN_OFF (28u)

/** \brief  Length for Ifx_GTM_OTBU2T_Bits.CV */
#define IFX_GTM_OTBU2T_CV_LEN (24u)

/** \brief  Mask for Ifx_GTM_OTBU2T_Bits.CV */
#define IFX_GTM_OTBU2T_CV_MSK (0xffffffu)

/** \brief  Offset for Ifx_GTM_OTBU2T_Bits.CV */
#define IFX_GTM_OTBU2T_CV_OFF (0u)

/** \brief  Length for Ifx_GTM_OTBU2T_Bits.EN */
#define IFX_GTM_OTBU2T_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_OTBU2T_Bits.EN */
#define IFX_GTM_OTBU2T_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_OTBU2T_Bits.EN */
#define IFX_GTM_OTBU2T_EN_OFF (28u)

/** \brief  Length for Ifx_GTM_OTSC0_Bits.B0HMI */
#define IFX_GTM_OTSC0_B0HMI_LEN (4u)

/** \brief  Mask for Ifx_GTM_OTSC0_Bits.B0HMI */
#define IFX_GTM_OTSC0_B0HMI_MSK (0xfu)

/** \brief  Offset for Ifx_GTM_OTSC0_Bits.B0HMI */
#define IFX_GTM_OTSC0_B0HMI_OFF (12u)

/** \brief  Length for Ifx_GTM_OTSC0_Bits.B0HMT */
#define IFX_GTM_OTSC0_B0HMT_LEN (3u)

/** \brief  Mask for Ifx_GTM_OTSC0_Bits.B0HMT */
#define IFX_GTM_OTSC0_B0HMT_MSK (0x7u)

/** \brief  Offset for Ifx_GTM_OTSC0_Bits.B0HMT */
#define IFX_GTM_OTSC0_B0HMT_OFF (8u)

/** \brief  Length for Ifx_GTM_OTSC0_Bits.B0LMI */
#define IFX_GTM_OTSC0_B0LMI_LEN (4u)

/** \brief  Mask for Ifx_GTM_OTSC0_Bits.B0LMI */
#define IFX_GTM_OTSC0_B0LMI_MSK (0xfu)

/** \brief  Offset for Ifx_GTM_OTSC0_Bits.B0LMI */
#define IFX_GTM_OTSC0_B0LMI_OFF (4u)

/** \brief  Length for Ifx_GTM_OTSC0_Bits.B0LMT */
#define IFX_GTM_OTSC0_B0LMT_LEN (3u)

/** \brief  Mask for Ifx_GTM_OTSC0_Bits.B0LMT */
#define IFX_GTM_OTSC0_B0LMT_MSK (0x7u)

/** \brief  Offset for Ifx_GTM_OTSC0_Bits.B0LMT */
#define IFX_GTM_OTSC0_B0LMT_OFF (0u)

/** \brief  Length for Ifx_GTM_OTSC0_Bits.B1HMI */
#define IFX_GTM_OTSC0_B1HMI_LEN (4u)

/** \brief  Mask for Ifx_GTM_OTSC0_Bits.B1HMI */
#define IFX_GTM_OTSC0_B1HMI_MSK (0xfu)

/** \brief  Offset for Ifx_GTM_OTSC0_Bits.B1HMI */
#define IFX_GTM_OTSC0_B1HMI_OFF (28u)

/** \brief  Length for Ifx_GTM_OTSC0_Bits.B1HMT */
#define IFX_GTM_OTSC0_B1HMT_LEN (3u)

/** \brief  Mask for Ifx_GTM_OTSC0_Bits.B1HMT */
#define IFX_GTM_OTSC0_B1HMT_MSK (0x7u)

/** \brief  Offset for Ifx_GTM_OTSC0_Bits.B1HMT */
#define IFX_GTM_OTSC0_B1HMT_OFF (24u)

/** \brief  Length for Ifx_GTM_OTSC0_Bits.B1LMI */
#define IFX_GTM_OTSC0_B1LMI_LEN (4u)

/** \brief  Mask for Ifx_GTM_OTSC0_Bits.B1LMI */
#define IFX_GTM_OTSC0_B1LMI_MSK (0xfu)

/** \brief  Offset for Ifx_GTM_OTSC0_Bits.B1LMI */
#define IFX_GTM_OTSC0_B1LMI_OFF (20u)

/** \brief  Length for Ifx_GTM_OTSC0_Bits.B1LMT */
#define IFX_GTM_OTSC0_B1LMT_LEN (3u)

/** \brief  Mask for Ifx_GTM_OTSC0_Bits.B1LMT */
#define IFX_GTM_OTSC0_B1LMT_MSK (0x7u)

/** \brief  Offset for Ifx_GTM_OTSC0_Bits.B1LMT */
#define IFX_GTM_OTSC0_B1LMT_OFF (16u)

/** \brief  Length for Ifx_GTM_OTSC1_Bits.MCS */
#define IFX_GTM_OTSC1_MCS_LEN (4u)

/** \brief  Mask for Ifx_GTM_OTSC1_Bits.MCS */
#define IFX_GTM_OTSC1_MCS_MSK (0xfu)

/** \brief  Offset for Ifx_GTM_OTSC1_Bits.MCS */
#define IFX_GTM_OTSC1_MCS_OFF (0u)

/** \brief  Length for Ifx_GTM_OTSC1_Bits.MI */
#define IFX_GTM_OTSC1_MI_LEN (4u)

/** \brief  Mask for Ifx_GTM_OTSC1_Bits.MI */
#define IFX_GTM_OTSC1_MI_MSK (0xfu)

/** \brief  Offset for Ifx_GTM_OTSC1_Bits.MI */
#define IFX_GTM_OTSC1_MI_OFF (4u)

/** \brief  Length for Ifx_GTM_OTSC1_Bits.MOE */
#define IFX_GTM_OTSC1_MOE_LEN (1u)

/** \brief  Mask for Ifx_GTM_OTSC1_Bits.MOE */
#define IFX_GTM_OTSC1_MOE_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_OTSC1_Bits.MOE */
#define IFX_GTM_OTSC1_MOE_OFF (9u)

/** \brief  Length for Ifx_GTM_OTSS_Bits.OTGB0 */
#define IFX_GTM_OTSS_OTGB0_LEN (4u)

/** \brief  Mask for Ifx_GTM_OTSS_Bits.OTGB0 */
#define IFX_GTM_OTSS_OTGB0_MSK (0xfu)

/** \brief  Offset for Ifx_GTM_OTSS_Bits.OTGB0 */
#define IFX_GTM_OTSS_OTGB0_OFF (0u)

/** \brief  Length for Ifx_GTM_OTSS_Bits.OTGB1 */
#define IFX_GTM_OTSS_OTGB1_LEN (4u)

/** \brief  Mask for Ifx_GTM_OTSS_Bits.OTGB1 */
#define IFX_GTM_OTSS_OTGB1_MSK (0xfu)

/** \brief  Offset for Ifx_GTM_OTSS_Bits.OTGB1 */
#define IFX_GTM_OTSS_OTGB1_OFF (8u)

/** \brief  Length for Ifx_GTM_OTSS_Bits.OTGB2 */
#define IFX_GTM_OTSS_OTGB2_LEN (4u)

/** \brief  Mask for Ifx_GTM_OTSS_Bits.OTGB2 */
#define IFX_GTM_OTSS_OTGB2_MSK (0xfu)

/** \brief  Offset for Ifx_GTM_OTSS_Bits.OTGB2 */
#define IFX_GTM_OTSS_OTGB2_OFF (16u)

/** \brief  Length for Ifx_GTM_REV_Bits.DEV_CODE0 */
#define IFX_GTM_REV_DEV_CODE0_LEN (4u)

/** \brief  Mask for Ifx_GTM_REV_Bits.DEV_CODE0 */
#define IFX_GTM_REV_DEV_CODE0_MSK (0xfu)

/** \brief  Offset for Ifx_GTM_REV_Bits.DEV_CODE0 */
#define IFX_GTM_REV_DEV_CODE0_OFF (20u)

/** \brief  Length for Ifx_GTM_REV_Bits.DEV_CODE1 */
#define IFX_GTM_REV_DEV_CODE1_LEN (4u)

/** \brief  Mask for Ifx_GTM_REV_Bits.DEV_CODE1 */
#define IFX_GTM_REV_DEV_CODE1_MSK (0xfu)

/** \brief  Offset for Ifx_GTM_REV_Bits.DEV_CODE1 */
#define IFX_GTM_REV_DEV_CODE1_OFF (24u)

/** \brief  Length for Ifx_GTM_REV_Bits.DEV_CODE2 */
#define IFX_GTM_REV_DEV_CODE2_LEN (4u)

/** \brief  Mask for Ifx_GTM_REV_Bits.DEV_CODE2 */
#define IFX_GTM_REV_DEV_CODE2_MSK (0xfu)

/** \brief  Offset for Ifx_GTM_REV_Bits.DEV_CODE2 */
#define IFX_GTM_REV_DEV_CODE2_OFF (28u)

/** \brief  Length for Ifx_GTM_REV_Bits.MAJOR */
#define IFX_GTM_REV_MAJOR_LEN (4u)

/** \brief  Mask for Ifx_GTM_REV_Bits.MAJOR */
#define IFX_GTM_REV_MAJOR_MSK (0xfu)

/** \brief  Offset for Ifx_GTM_REV_Bits.MAJOR */
#define IFX_GTM_REV_MAJOR_OFF (16u)

/** \brief  Length for Ifx_GTM_REV_Bits.MINOR */
#define IFX_GTM_REV_MINOR_LEN (4u)

/** \brief  Mask for Ifx_GTM_REV_Bits.MINOR */
#define IFX_GTM_REV_MINOR_MSK (0xfu)

/** \brief  Offset for Ifx_GTM_REV_Bits.MINOR */
#define IFX_GTM_REV_MINOR_OFF (12u)

/** \brief  Length for Ifx_GTM_REV_Bits.NO */
#define IFX_GTM_REV_NO_LEN (4u)

/** \brief  Mask for Ifx_GTM_REV_Bits.NO */
#define IFX_GTM_REV_NO_MSK (0xfu)

/** \brief  Offset for Ifx_GTM_REV_Bits.NO */
#define IFX_GTM_REV_NO_OFF (8u)

/** \brief  Length for Ifx_GTM_REV_Bits.STEP */
#define IFX_GTM_REV_STEP_LEN (8u)

/** \brief  Mask for Ifx_GTM_REV_Bits.STEP */
#define IFX_GTM_REV_STEP_MSK (0xffu)

/** \brief  Offset for Ifx_GTM_REV_Bits.STEP */
#define IFX_GTM_REV_STEP_OFF (0u)

/** \brief  Length for Ifx_GTM_RST_Bits.RST */
#define IFX_GTM_RST_RST_LEN (1u)

/** \brief  Mask for Ifx_GTM_RST_Bits.RST */
#define IFX_GTM_RST_RST_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_RST_Bits.RST */
#define IFX_GTM_RST_RST_OFF (0u)

/** \brief  Length for Ifx_GTM_SPE_CMP_Bits.CMP */
#define IFX_GTM_SPE_CMP_CMP_LEN (24u)

/** \brief  Mask for Ifx_GTM_SPE_CMP_Bits.CMP */
#define IFX_GTM_SPE_CMP_CMP_MSK (0xffffffu)

/** \brief  Offset for Ifx_GTM_SPE_CMP_Bits.CMP */
#define IFX_GTM_SPE_CMP_CMP_OFF (0u)

/** \brief  Length for Ifx_GTM_SPE_CNT_Bits.CNT */
#define IFX_GTM_SPE_CNT_CNT_LEN (24u)

/** \brief  Mask for Ifx_GTM_SPE_CNT_Bits.CNT */
#define IFX_GTM_SPE_CNT_CNT_MSK (0xffffffu)

/** \brief  Offset for Ifx_GTM_SPE_CNT_Bits.CNT */
#define IFX_GTM_SPE_CNT_CNT_OFF (0u)

/** \brief  Length for Ifx_GTM_SPE_CTRL_STAT_Bits.ADIR */
#define IFX_GTM_SPE_CTRL_STAT_ADIR_LEN (1u)

/** \brief  Mask for Ifx_GTM_SPE_CTRL_STAT_Bits.ADIR */
#define IFX_GTM_SPE_CTRL_STAT_ADIR_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_SPE_CTRL_STAT_Bits.ADIR */
#define IFX_GTM_SPE_CTRL_STAT_ADIR_OFF (15u)

/** \brief  Length for Ifx_GTM_SPE_CTRL_STAT_Bits.AIP */
#define IFX_GTM_SPE_CTRL_STAT_AIP_LEN (3u)

/** \brief  Mask for Ifx_GTM_SPE_CTRL_STAT_Bits.AIP */
#define IFX_GTM_SPE_CTRL_STAT_AIP_MSK (0x7u)

/** \brief  Offset for Ifx_GTM_SPE_CTRL_STAT_Bits.AIP */
#define IFX_GTM_SPE_CTRL_STAT_AIP_OFF (12u)

/** \brief  Length for Ifx_GTM_SPE_CTRL_STAT_Bits.FSOL */
#define IFX_GTM_SPE_CTRL_STAT_FSOL_LEN (8u)

/** \brief  Mask for Ifx_GTM_SPE_CTRL_STAT_Bits.FSOL */
#define IFX_GTM_SPE_CTRL_STAT_FSOL_MSK (0xffu)

/** \brief  Offset for Ifx_GTM_SPE_CTRL_STAT_Bits.FSOL */
#define IFX_GTM_SPE_CTRL_STAT_FSOL_OFF (24u)

/** \brief  Length for Ifx_GTM_SPE_CTRL_STAT_Bits.FSOM */
#define IFX_GTM_SPE_CTRL_STAT_FSOM_LEN (1u)

/** \brief  Mask for Ifx_GTM_SPE_CTRL_STAT_Bits.FSOM */
#define IFX_GTM_SPE_CTRL_STAT_FSOM_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_SPE_CTRL_STAT_Bits.FSOM */
#define IFX_GTM_SPE_CTRL_STAT_FSOM_OFF (7u)

/** \brief  Length for Ifx_GTM_SPE_CTRL_STAT_Bits.NIP */
#define IFX_GTM_SPE_CTRL_STAT_NIP_LEN (3u)

/** \brief  Mask for Ifx_GTM_SPE_CTRL_STAT_Bits.NIP */
#define IFX_GTM_SPE_CTRL_STAT_NIP_MSK (0x7u)

/** \brief  Offset for Ifx_GTM_SPE_CTRL_STAT_Bits.NIP */
#define IFX_GTM_SPE_CTRL_STAT_NIP_OFF (20u)

/** \brief  Length for Ifx_GTM_SPE_CTRL_STAT_Bits.PDIR */
#define IFX_GTM_SPE_CTRL_STAT_PDIR_LEN (1u)

/** \brief  Mask for Ifx_GTM_SPE_CTRL_STAT_Bits.PDIR */
#define IFX_GTM_SPE_CTRL_STAT_PDIR_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_SPE_CTRL_STAT_Bits.PDIR */
#define IFX_GTM_SPE_CTRL_STAT_PDIR_OFF (19u)

/** \brief  Length for Ifx_GTM_SPE_CTRL_STAT_Bits.PIP */
#define IFX_GTM_SPE_CTRL_STAT_PIP_LEN (3u)

/** \brief  Mask for Ifx_GTM_SPE_CTRL_STAT_Bits.PIP */
#define IFX_GTM_SPE_CTRL_STAT_PIP_MSK (0x7u)

/** \brief  Offset for Ifx_GTM_SPE_CTRL_STAT_Bits.PIP */
#define IFX_GTM_SPE_CTRL_STAT_PIP_OFF (16u)

/** \brief  Length for Ifx_GTM_SPE_CTRL_STAT_Bits.SIE0 */
#define IFX_GTM_SPE_CTRL_STAT_SIE0_LEN (1u)

/** \brief  Mask for Ifx_GTM_SPE_CTRL_STAT_Bits.SIE0 */
#define IFX_GTM_SPE_CTRL_STAT_SIE0_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_SPE_CTRL_STAT_Bits.SIE0 */
#define IFX_GTM_SPE_CTRL_STAT_SIE0_OFF (1u)

/** \brief  Length for Ifx_GTM_SPE_CTRL_STAT_Bits.SIE1 */
#define IFX_GTM_SPE_CTRL_STAT_SIE1_LEN (1u)

/** \brief  Mask for Ifx_GTM_SPE_CTRL_STAT_Bits.SIE1 */
#define IFX_GTM_SPE_CTRL_STAT_SIE1_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_SPE_CTRL_STAT_Bits.SIE1 */
#define IFX_GTM_SPE_CTRL_STAT_SIE1_OFF (2u)

/** \brief  Length for Ifx_GTM_SPE_CTRL_STAT_Bits.SIE2 */
#define IFX_GTM_SPE_CTRL_STAT_SIE2_LEN (1u)

/** \brief  Mask for Ifx_GTM_SPE_CTRL_STAT_Bits.SIE2 */
#define IFX_GTM_SPE_CTRL_STAT_SIE2_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_SPE_CTRL_STAT_Bits.SIE2 */
#define IFX_GTM_SPE_CTRL_STAT_SIE2_OFF (3u)

/** \brief  Length for Ifx_GTM_SPE_CTRL_STAT_Bits.SPE_EN */
#define IFX_GTM_SPE_CTRL_STAT_SPE_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_SPE_CTRL_STAT_Bits.SPE_EN */
#define IFX_GTM_SPE_CTRL_STAT_SPE_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_SPE_CTRL_STAT_Bits.SPE_EN */
#define IFX_GTM_SPE_CTRL_STAT_SPE_EN_OFF (0u)

/** \brief  Length for Ifx_GTM_SPE_CTRL_STAT_Bits.SPE_PAT_PTR */
#define IFX_GTM_SPE_CTRL_STAT_SPE_PAT_PTR_LEN (3u)

/** \brief  Mask for Ifx_GTM_SPE_CTRL_STAT_Bits.SPE_PAT_PTR */
#define IFX_GTM_SPE_CTRL_STAT_SPE_PAT_PTR_MSK (0x7u)

/** \brief  Offset for Ifx_GTM_SPE_CTRL_STAT_Bits.SPE_PAT_PTR */
#define IFX_GTM_SPE_CTRL_STAT_SPE_PAT_PTR_OFF (8u)

/** \brief  Length for Ifx_GTM_SPE_CTRL_STAT_Bits.TIM_SEL */
#define IFX_GTM_SPE_CTRL_STAT_TIM_SEL_LEN (1u)

/** \brief  Mask for Ifx_GTM_SPE_CTRL_STAT_Bits.TIM_SEL */
#define IFX_GTM_SPE_CTRL_STAT_TIM_SEL_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_SPE_CTRL_STAT_Bits.TIM_SEL */
#define IFX_GTM_SPE_CTRL_STAT_TIM_SEL_OFF (6u)

/** \brief  Length for Ifx_GTM_SPE_CTRL_STAT_Bits.TRIG_SEL */
#define IFX_GTM_SPE_CTRL_STAT_TRIG_SEL_LEN (2u)

/** \brief  Mask for Ifx_GTM_SPE_CTRL_STAT_Bits.TRIG_SEL */
#define IFX_GTM_SPE_CTRL_STAT_TRIG_SEL_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_SPE_CTRL_STAT_Bits.TRIG_SEL */
#define IFX_GTM_SPE_CTRL_STAT_TRIG_SEL_OFF (4u)

/** \brief  Length for Ifx_GTM_SPE_EIRQ_EN_Bits.SPE_BIS_EIRQ_EN */
#define IFX_GTM_SPE_EIRQ_EN_SPE_BIS_EIRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_SPE_EIRQ_EN_Bits.SPE_BIS_EIRQ_EN */
#define IFX_GTM_SPE_EIRQ_EN_SPE_BIS_EIRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_SPE_EIRQ_EN_Bits.SPE_BIS_EIRQ_EN */
#define IFX_GTM_SPE_EIRQ_EN_SPE_BIS_EIRQ_EN_OFF (3u)

/** \brief  Length for Ifx_GTM_SPE_EIRQ_EN_Bits.SPE_DCHG_EIRQ_EN */
#define IFX_GTM_SPE_EIRQ_EN_SPE_DCHG_EIRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_SPE_EIRQ_EN_Bits.SPE_DCHG_EIRQ_EN */
#define IFX_GTM_SPE_EIRQ_EN_SPE_DCHG_EIRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_SPE_EIRQ_EN_Bits.SPE_DCHG_EIRQ_EN */
#define IFX_GTM_SPE_EIRQ_EN_SPE_DCHG_EIRQ_EN_OFF (1u)

/** \brief  Length for Ifx_GTM_SPE_EIRQ_EN_Bits.SPE_NIPD_EIRQ_EN */
#define IFX_GTM_SPE_EIRQ_EN_SPE_NIPD_EIRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_SPE_EIRQ_EN_Bits.SPE_NIPD_EIRQ_EN */
#define IFX_GTM_SPE_EIRQ_EN_SPE_NIPD_EIRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_SPE_EIRQ_EN_Bits.SPE_NIPD_EIRQ_EN */
#define IFX_GTM_SPE_EIRQ_EN_SPE_NIPD_EIRQ_EN_OFF (0u)

/** \brief  Length for Ifx_GTM_SPE_EIRQ_EN_Bits.SPE_PERR_EIRQ_EN */
#define IFX_GTM_SPE_EIRQ_EN_SPE_PERR_EIRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_SPE_EIRQ_EN_Bits.SPE_PERR_EIRQ_EN */
#define IFX_GTM_SPE_EIRQ_EN_SPE_PERR_EIRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_SPE_EIRQ_EN_Bits.SPE_PERR_EIRQ_EN */
#define IFX_GTM_SPE_EIRQ_EN_SPE_PERR_EIRQ_EN_OFF (2u)

/** \brief  Length for Ifx_GTM_SPE_EIRQ_EN_Bits.SPE_RCMP_EIRQ_EN */
#define IFX_GTM_SPE_EIRQ_EN_SPE_RCMP_EIRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_SPE_EIRQ_EN_Bits.SPE_RCMP_EIRQ_EN */
#define IFX_GTM_SPE_EIRQ_EN_SPE_RCMP_EIRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_SPE_EIRQ_EN_Bits.SPE_RCMP_EIRQ_EN */
#define IFX_GTM_SPE_EIRQ_EN_SPE_RCMP_EIRQ_EN_OFF (4u)

/** \brief  Length for Ifx_GTM_SPE_IRQ_EN_Bits.SPE_BIS_IRQ_EN */
#define IFX_GTM_SPE_IRQ_EN_SPE_BIS_IRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_SPE_IRQ_EN_Bits.SPE_BIS_IRQ_EN */
#define IFX_GTM_SPE_IRQ_EN_SPE_BIS_IRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_SPE_IRQ_EN_Bits.SPE_BIS_IRQ_EN */
#define IFX_GTM_SPE_IRQ_EN_SPE_BIS_IRQ_EN_OFF (3u)

/** \brief  Length for Ifx_GTM_SPE_IRQ_EN_Bits.SPE_DCHG_IRQ_EN */
#define IFX_GTM_SPE_IRQ_EN_SPE_DCHG_IRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_SPE_IRQ_EN_Bits.SPE_DCHG_IRQ_EN */
#define IFX_GTM_SPE_IRQ_EN_SPE_DCHG_IRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_SPE_IRQ_EN_Bits.SPE_DCHG_IRQ_EN */
#define IFX_GTM_SPE_IRQ_EN_SPE_DCHG_IRQ_EN_OFF (1u)

/** \brief  Length for Ifx_GTM_SPE_IRQ_EN_Bits.SPE_NIPD_IRQ_EN */
#define IFX_GTM_SPE_IRQ_EN_SPE_NIPD_IRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_SPE_IRQ_EN_Bits.SPE_NIPD_IRQ_EN */
#define IFX_GTM_SPE_IRQ_EN_SPE_NIPD_IRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_SPE_IRQ_EN_Bits.SPE_NIPD_IRQ_EN */
#define IFX_GTM_SPE_IRQ_EN_SPE_NIPD_IRQ_EN_OFF (0u)

/** \brief  Length for Ifx_GTM_SPE_IRQ_EN_Bits.SPE_PERR_IRQ_EN */
#define IFX_GTM_SPE_IRQ_EN_SPE_PERR_IRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_SPE_IRQ_EN_Bits.SPE_PERR_IRQ_EN */
#define IFX_GTM_SPE_IRQ_EN_SPE_PERR_IRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_SPE_IRQ_EN_Bits.SPE_PERR_IRQ_EN */
#define IFX_GTM_SPE_IRQ_EN_SPE_PERR_IRQ_EN_OFF (2u)

/** \brief  Length for Ifx_GTM_SPE_IRQ_EN_Bits.SPE_RCMP_IRQ_EN */
#define IFX_GTM_SPE_IRQ_EN_SPE_RCMP_IRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_SPE_IRQ_EN_Bits.SPE_RCMP_IRQ_EN */
#define IFX_GTM_SPE_IRQ_EN_SPE_RCMP_IRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_SPE_IRQ_EN_Bits.SPE_RCMP_IRQ_EN */
#define IFX_GTM_SPE_IRQ_EN_SPE_RCMP_IRQ_EN_OFF (4u)

/** \brief  Length for Ifx_GTM_SPE_IRQ_FORCINT_Bits.TRG_SPE_BIS */
#define IFX_GTM_SPE_IRQ_FORCINT_TRG_SPE_BIS_LEN (1u)

/** \brief  Mask for Ifx_GTM_SPE_IRQ_FORCINT_Bits.TRG_SPE_BIS */
#define IFX_GTM_SPE_IRQ_FORCINT_TRG_SPE_BIS_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_SPE_IRQ_FORCINT_Bits.TRG_SPE_BIS */
#define IFX_GTM_SPE_IRQ_FORCINT_TRG_SPE_BIS_OFF (3u)

/** \brief  Length for Ifx_GTM_SPE_IRQ_FORCINT_Bits.TRG_SPE_DCHG */
#define IFX_GTM_SPE_IRQ_FORCINT_TRG_SPE_DCHG_LEN (1u)

/** \brief  Mask for Ifx_GTM_SPE_IRQ_FORCINT_Bits.TRG_SPE_DCHG */
#define IFX_GTM_SPE_IRQ_FORCINT_TRG_SPE_DCHG_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_SPE_IRQ_FORCINT_Bits.TRG_SPE_DCHG */
#define IFX_GTM_SPE_IRQ_FORCINT_TRG_SPE_DCHG_OFF (1u)

/** \brief  Length for Ifx_GTM_SPE_IRQ_FORCINT_Bits.TRG_SPE_NIPD */
#define IFX_GTM_SPE_IRQ_FORCINT_TRG_SPE_NIPD_LEN (1u)

/** \brief  Mask for Ifx_GTM_SPE_IRQ_FORCINT_Bits.TRG_SPE_NIPD */
#define IFX_GTM_SPE_IRQ_FORCINT_TRG_SPE_NIPD_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_SPE_IRQ_FORCINT_Bits.TRG_SPE_NIPD */
#define IFX_GTM_SPE_IRQ_FORCINT_TRG_SPE_NIPD_OFF (0u)

/** \brief  Length for Ifx_GTM_SPE_IRQ_FORCINT_Bits.TRG_SPE_PERR */
#define IFX_GTM_SPE_IRQ_FORCINT_TRG_SPE_PERR_LEN (1u)

/** \brief  Mask for Ifx_GTM_SPE_IRQ_FORCINT_Bits.TRG_SPE_PERR */
#define IFX_GTM_SPE_IRQ_FORCINT_TRG_SPE_PERR_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_SPE_IRQ_FORCINT_Bits.TRG_SPE_PERR */
#define IFX_GTM_SPE_IRQ_FORCINT_TRG_SPE_PERR_OFF (2u)

/** \brief  Length for Ifx_GTM_SPE_IRQ_FORCINT_Bits.TRG_SPE_RCMP */
#define IFX_GTM_SPE_IRQ_FORCINT_TRG_SPE_RCMP_LEN (1u)

/** \brief  Mask for Ifx_GTM_SPE_IRQ_FORCINT_Bits.TRG_SPE_RCMP */
#define IFX_GTM_SPE_IRQ_FORCINT_TRG_SPE_RCMP_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_SPE_IRQ_FORCINT_Bits.TRG_SPE_RCMP */
#define IFX_GTM_SPE_IRQ_FORCINT_TRG_SPE_RCMP_OFF (4u)

/** \brief  Length for Ifx_GTM_SPE_IRQ_MODE_Bits.IRQ_MODE */
#define IFX_GTM_SPE_IRQ_MODE_IRQ_MODE_LEN (2u)

/** \brief  Mask for Ifx_GTM_SPE_IRQ_MODE_Bits.IRQ_MODE */
#define IFX_GTM_SPE_IRQ_MODE_IRQ_MODE_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_SPE_IRQ_MODE_Bits.IRQ_MODE */
#define IFX_GTM_SPE_IRQ_MODE_IRQ_MODE_OFF (0u)

/** \brief  Length for Ifx_GTM_SPE_IRQ_NOTIFY_Bits.SPE_BIS */
#define IFX_GTM_SPE_IRQ_NOTIFY_SPE_BIS_LEN (1u)

/** \brief  Mask for Ifx_GTM_SPE_IRQ_NOTIFY_Bits.SPE_BIS */
#define IFX_GTM_SPE_IRQ_NOTIFY_SPE_BIS_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_SPE_IRQ_NOTIFY_Bits.SPE_BIS */
#define IFX_GTM_SPE_IRQ_NOTIFY_SPE_BIS_OFF (3u)

/** \brief  Length for Ifx_GTM_SPE_IRQ_NOTIFY_Bits.SPE_DCHG */
#define IFX_GTM_SPE_IRQ_NOTIFY_SPE_DCHG_LEN (1u)

/** \brief  Mask for Ifx_GTM_SPE_IRQ_NOTIFY_Bits.SPE_DCHG */
#define IFX_GTM_SPE_IRQ_NOTIFY_SPE_DCHG_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_SPE_IRQ_NOTIFY_Bits.SPE_DCHG */
#define IFX_GTM_SPE_IRQ_NOTIFY_SPE_DCHG_OFF (1u)

/** \brief  Length for Ifx_GTM_SPE_IRQ_NOTIFY_Bits.SPE_NIPD */
#define IFX_GTM_SPE_IRQ_NOTIFY_SPE_NIPD_LEN (1u)

/** \brief  Mask for Ifx_GTM_SPE_IRQ_NOTIFY_Bits.SPE_NIPD */
#define IFX_GTM_SPE_IRQ_NOTIFY_SPE_NIPD_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_SPE_IRQ_NOTIFY_Bits.SPE_NIPD */
#define IFX_GTM_SPE_IRQ_NOTIFY_SPE_NIPD_OFF (0u)

/** \brief  Length for Ifx_GTM_SPE_IRQ_NOTIFY_Bits.SPE_PERR */
#define IFX_GTM_SPE_IRQ_NOTIFY_SPE_PERR_LEN (1u)

/** \brief  Mask for Ifx_GTM_SPE_IRQ_NOTIFY_Bits.SPE_PERR */
#define IFX_GTM_SPE_IRQ_NOTIFY_SPE_PERR_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_SPE_IRQ_NOTIFY_Bits.SPE_PERR */
#define IFX_GTM_SPE_IRQ_NOTIFY_SPE_PERR_OFF (2u)

/** \brief  Length for Ifx_GTM_SPE_IRQ_NOTIFY_Bits.SPE_RCMP */
#define IFX_GTM_SPE_IRQ_NOTIFY_SPE_RCMP_LEN (1u)

/** \brief  Mask for Ifx_GTM_SPE_IRQ_NOTIFY_Bits.SPE_RCMP */
#define IFX_GTM_SPE_IRQ_NOTIFY_SPE_RCMP_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_SPE_IRQ_NOTIFY_Bits.SPE_RCMP */
#define IFX_GTM_SPE_IRQ_NOTIFY_SPE_RCMP_OFF (4u)

/** \brief  Length for Ifx_GTM_SPE_OUT_CTRL_Bits.SPE_OUT_CTRL */
#define IFX_GTM_SPE_OUT_CTRL_SPE_OUT_CTRL_LEN (16u)

/** \brief  Mask for Ifx_GTM_SPE_OUT_CTRL_Bits.SPE_OUT_CTRL */
#define IFX_GTM_SPE_OUT_CTRL_SPE_OUT_CTRL_MSK (0xffffu)

/** \brief  Offset for Ifx_GTM_SPE_OUT_CTRL_Bits.SPE_OUT_CTRL */
#define IFX_GTM_SPE_OUT_CTRL_SPE_OUT_CTRL_OFF (0u)

/** \brief  Length for Ifx_GTM_SPE_OUT_PAT_Bits.SPE_OUT_PAT */
#define IFX_GTM_SPE_OUT_PAT_SPE_OUT_PAT_LEN (16u)

/** \brief  Mask for Ifx_GTM_SPE_OUT_PAT_Bits.SPE_OUT_PAT */
#define IFX_GTM_SPE_OUT_PAT_SPE_OUT_PAT_MSK (0xffffu)

/** \brief  Offset for Ifx_GTM_SPE_OUT_PAT_Bits.SPE_OUT_PAT */
#define IFX_GTM_SPE_OUT_PAT_SPE_OUT_PAT_OFF (0u)

/** \brief  Length for Ifx_GTM_SPE_PAT_Bits.IP0_PAT */
#define IFX_GTM_SPE_PAT_IP0_PAT_LEN (3u)

/** \brief  Mask for Ifx_GTM_SPE_PAT_Bits.IP0_PAT */
#define IFX_GTM_SPE_PAT_IP0_PAT_MSK (0x7u)

/** \brief  Offset for Ifx_GTM_SPE_PAT_Bits.IP0_PAT */
#define IFX_GTM_SPE_PAT_IP0_PAT_OFF (1u)

/** \brief  Length for Ifx_GTM_SPE_PAT_Bits.IP0_VAL */
#define IFX_GTM_SPE_PAT_IP0_VAL_LEN (1u)

/** \brief  Mask for Ifx_GTM_SPE_PAT_Bits.IP0_VAL */
#define IFX_GTM_SPE_PAT_IP0_VAL_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_SPE_PAT_Bits.IP0_VAL */
#define IFX_GTM_SPE_PAT_IP0_VAL_OFF (0u)

/** \brief  Length for Ifx_GTM_SPE_PAT_Bits.IP1_PAT */
#define IFX_GTM_SPE_PAT_IP1_PAT_LEN (3u)

/** \brief  Mask for Ifx_GTM_SPE_PAT_Bits.IP1_PAT */
#define IFX_GTM_SPE_PAT_IP1_PAT_MSK (0x7u)

/** \brief  Offset for Ifx_GTM_SPE_PAT_Bits.IP1_PAT */
#define IFX_GTM_SPE_PAT_IP1_PAT_OFF (5u)

/** \brief  Length for Ifx_GTM_SPE_PAT_Bits.IP1_VAL */
#define IFX_GTM_SPE_PAT_IP1_VAL_LEN (1u)

/** \brief  Mask for Ifx_GTM_SPE_PAT_Bits.IP1_VAL */
#define IFX_GTM_SPE_PAT_IP1_VAL_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_SPE_PAT_Bits.IP1_VAL */
#define IFX_GTM_SPE_PAT_IP1_VAL_OFF (4u)

/** \brief  Length for Ifx_GTM_SPE_PAT_Bits.IP2_PAT */
#define IFX_GTM_SPE_PAT_IP2_PAT_LEN (3u)

/** \brief  Mask for Ifx_GTM_SPE_PAT_Bits.IP2_PAT */
#define IFX_GTM_SPE_PAT_IP2_PAT_MSK (0x7u)

/** \brief  Offset for Ifx_GTM_SPE_PAT_Bits.IP2_PAT */
#define IFX_GTM_SPE_PAT_IP2_PAT_OFF (9u)

/** \brief  Length for Ifx_GTM_SPE_PAT_Bits.IP2_VAL */
#define IFX_GTM_SPE_PAT_IP2_VAL_LEN (1u)

/** \brief  Mask for Ifx_GTM_SPE_PAT_Bits.IP2_VAL */
#define IFX_GTM_SPE_PAT_IP2_VAL_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_SPE_PAT_Bits.IP2_VAL */
#define IFX_GTM_SPE_PAT_IP2_VAL_OFF (8u)

/** \brief  Length for Ifx_GTM_SPE_PAT_Bits.IP3_PAT */
#define IFX_GTM_SPE_PAT_IP3_PAT_LEN (3u)

/** \brief  Mask for Ifx_GTM_SPE_PAT_Bits.IP3_PAT */
#define IFX_GTM_SPE_PAT_IP3_PAT_MSK (0x7u)

/** \brief  Offset for Ifx_GTM_SPE_PAT_Bits.IP3_PAT */
#define IFX_GTM_SPE_PAT_IP3_PAT_OFF (13u)

/** \brief  Length for Ifx_GTM_SPE_PAT_Bits.IP3_VAL */
#define IFX_GTM_SPE_PAT_IP3_VAL_LEN (1u)

/** \brief  Mask for Ifx_GTM_SPE_PAT_Bits.IP3_VAL */
#define IFX_GTM_SPE_PAT_IP3_VAL_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_SPE_PAT_Bits.IP3_VAL */
#define IFX_GTM_SPE_PAT_IP3_VAL_OFF (12u)

/** \brief  Length for Ifx_GTM_SPE_PAT_Bits.IP4_PAT */
#define IFX_GTM_SPE_PAT_IP4_PAT_LEN (3u)

/** \brief  Mask for Ifx_GTM_SPE_PAT_Bits.IP4_PAT */
#define IFX_GTM_SPE_PAT_IP4_PAT_MSK (0x7u)

/** \brief  Offset for Ifx_GTM_SPE_PAT_Bits.IP4_PAT */
#define IFX_GTM_SPE_PAT_IP4_PAT_OFF (17u)

/** \brief  Length for Ifx_GTM_SPE_PAT_Bits.IP4_VAL */
#define IFX_GTM_SPE_PAT_IP4_VAL_LEN (1u)

/** \brief  Mask for Ifx_GTM_SPE_PAT_Bits.IP4_VAL */
#define IFX_GTM_SPE_PAT_IP4_VAL_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_SPE_PAT_Bits.IP4_VAL */
#define IFX_GTM_SPE_PAT_IP4_VAL_OFF (16u)

/** \brief  Length for Ifx_GTM_SPE_PAT_Bits.IP5_PAT */
#define IFX_GTM_SPE_PAT_IP5_PAT_LEN (3u)

/** \brief  Mask for Ifx_GTM_SPE_PAT_Bits.IP5_PAT */
#define IFX_GTM_SPE_PAT_IP5_PAT_MSK (0x7u)

/** \brief  Offset for Ifx_GTM_SPE_PAT_Bits.IP5_PAT */
#define IFX_GTM_SPE_PAT_IP5_PAT_OFF (21u)

/** \brief  Length for Ifx_GTM_SPE_PAT_Bits.IP5_VAL */
#define IFX_GTM_SPE_PAT_IP5_VAL_LEN (1u)

/** \brief  Mask for Ifx_GTM_SPE_PAT_Bits.IP5_VAL */
#define IFX_GTM_SPE_PAT_IP5_VAL_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_SPE_PAT_Bits.IP5_VAL */
#define IFX_GTM_SPE_PAT_IP5_VAL_OFF (20u)

/** \brief  Length for Ifx_GTM_SPE_PAT_Bits.IP6_PAT */
#define IFX_GTM_SPE_PAT_IP6_PAT_LEN (3u)

/** \brief  Mask for Ifx_GTM_SPE_PAT_Bits.IP6_PAT */
#define IFX_GTM_SPE_PAT_IP6_PAT_MSK (0x7u)

/** \brief  Offset for Ifx_GTM_SPE_PAT_Bits.IP6_PAT */
#define IFX_GTM_SPE_PAT_IP6_PAT_OFF (25u)

/** \brief  Length for Ifx_GTM_SPE_PAT_Bits.IP6_VAL */
#define IFX_GTM_SPE_PAT_IP6_VAL_LEN (1u)

/** \brief  Mask for Ifx_GTM_SPE_PAT_Bits.IP6_VAL */
#define IFX_GTM_SPE_PAT_IP6_VAL_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_SPE_PAT_Bits.IP6_VAL */
#define IFX_GTM_SPE_PAT_IP6_VAL_OFF (24u)

/** \brief  Length for Ifx_GTM_SPE_PAT_Bits.IP7_PAT */
#define IFX_GTM_SPE_PAT_IP7_PAT_LEN (3u)

/** \brief  Mask for Ifx_GTM_SPE_PAT_Bits.IP7_PAT */
#define IFX_GTM_SPE_PAT_IP7_PAT_MSK (0x7u)

/** \brief  Offset for Ifx_GTM_SPE_PAT_Bits.IP7_PAT */
#define IFX_GTM_SPE_PAT_IP7_PAT_OFF (29u)

/** \brief  Length for Ifx_GTM_SPE_PAT_Bits.IP7_VAL */
#define IFX_GTM_SPE_PAT_IP7_VAL_LEN (1u)

/** \brief  Mask for Ifx_GTM_SPE_PAT_Bits.IP7_VAL */
#define IFX_GTM_SPE_PAT_IP7_VAL_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_SPE_PAT_Bits.IP7_VAL */
#define IFX_GTM_SPE_PAT_IP7_VAL_OFF (28u)

/** \brief  Length for Ifx_GTM_TBU_CH0_BASE_Bits.BASE */
#define IFX_GTM_TBU_CH0_BASE_BASE_LEN (27u)

/** \brief  Mask for Ifx_GTM_TBU_CH0_BASE_Bits.BASE */
#define IFX_GTM_TBU_CH0_BASE_BASE_MSK (0x7ffffffu)

/** \brief  Offset for Ifx_GTM_TBU_CH0_BASE_Bits.BASE */
#define IFX_GTM_TBU_CH0_BASE_BASE_OFF (0u)

/** \brief  Length for Ifx_GTM_TBU_CH0_CTRL_Bits.CH_CLK_SRC */
#define IFX_GTM_TBU_CH0_CTRL_CH_CLK_SRC_LEN (3u)

/** \brief  Mask for Ifx_GTM_TBU_CH0_CTRL_Bits.CH_CLK_SRC */
#define IFX_GTM_TBU_CH0_CTRL_CH_CLK_SRC_MSK (0x7u)

/** \brief  Offset for Ifx_GTM_TBU_CH0_CTRL_Bits.CH_CLK_SRC */
#define IFX_GTM_TBU_CH0_CTRL_CH_CLK_SRC_OFF (1u)

/** \brief  Length for Ifx_GTM_TBU_CH0_CTRL_Bits.LOW_RES */
#define IFX_GTM_TBU_CH0_CTRL_LOW_RES_LEN (1u)

/** \brief  Mask for Ifx_GTM_TBU_CH0_CTRL_Bits.LOW_RES */
#define IFX_GTM_TBU_CH0_CTRL_LOW_RES_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TBU_CH0_CTRL_Bits.LOW_RES */
#define IFX_GTM_TBU_CH0_CTRL_LOW_RES_OFF (0u)

/** \brief  Length for Ifx_GTM_TBU_CH1_BASE_Bits.BASE */
#define IFX_GTM_TBU_CH1_BASE_BASE_LEN (24u)

/** \brief  Mask for Ifx_GTM_TBU_CH1_BASE_Bits.BASE */
#define IFX_GTM_TBU_CH1_BASE_BASE_MSK (0xffffffu)

/** \brief  Offset for Ifx_GTM_TBU_CH1_BASE_Bits.BASE */
#define IFX_GTM_TBU_CH1_BASE_BASE_OFF (0u)

/** \brief  Length for Ifx_GTM_TBU_CH1_CTRL_Bits.CH_CLK_SRC */
#define IFX_GTM_TBU_CH1_CTRL_CH_CLK_SRC_LEN (3u)

/** \brief  Mask for Ifx_GTM_TBU_CH1_CTRL_Bits.CH_CLK_SRC */
#define IFX_GTM_TBU_CH1_CTRL_CH_CLK_SRC_MSK (0x7u)

/** \brief  Offset for Ifx_GTM_TBU_CH1_CTRL_Bits.CH_CLK_SRC */
#define IFX_GTM_TBU_CH1_CTRL_CH_CLK_SRC_OFF (1u)

/** \brief  Length for Ifx_GTM_TBU_CH1_CTRL_Bits.CH_MODE */
#define IFX_GTM_TBU_CH1_CTRL_CH_MODE_LEN (1u)

/** \brief  Mask for Ifx_GTM_TBU_CH1_CTRL_Bits.CH_MODE */
#define IFX_GTM_TBU_CH1_CTRL_CH_MODE_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TBU_CH1_CTRL_Bits.CH_MODE */
#define IFX_GTM_TBU_CH1_CTRL_CH_MODE_OFF (0u)

/** \brief  Length for Ifx_GTM_TBU_CH2_BASE_Bits.BASE */
#define IFX_GTM_TBU_CH2_BASE_BASE_LEN (24u)

/** \brief  Mask for Ifx_GTM_TBU_CH2_BASE_Bits.BASE */
#define IFX_GTM_TBU_CH2_BASE_BASE_MSK (0xffffffu)

/** \brief  Offset for Ifx_GTM_TBU_CH2_BASE_Bits.BASE */
#define IFX_GTM_TBU_CH2_BASE_BASE_OFF (0u)

/** \brief  Length for Ifx_GTM_TBU_CH2_CTRL_Bits.CH_CLK_SRC */
#define IFX_GTM_TBU_CH2_CTRL_CH_CLK_SRC_LEN (3u)

/** \brief  Mask for Ifx_GTM_TBU_CH2_CTRL_Bits.CH_CLK_SRC */
#define IFX_GTM_TBU_CH2_CTRL_CH_CLK_SRC_MSK (0x7u)

/** \brief  Offset for Ifx_GTM_TBU_CH2_CTRL_Bits.CH_CLK_SRC */
#define IFX_GTM_TBU_CH2_CTRL_CH_CLK_SRC_OFF (1u)

/** \brief  Length for Ifx_GTM_TBU_CH2_CTRL_Bits.CH_MODE */
#define IFX_GTM_TBU_CH2_CTRL_CH_MODE_LEN (1u)

/** \brief  Mask for Ifx_GTM_TBU_CH2_CTRL_Bits.CH_MODE */
#define IFX_GTM_TBU_CH2_CTRL_CH_MODE_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TBU_CH2_CTRL_Bits.CH_MODE */
#define IFX_GTM_TBU_CH2_CTRL_CH_MODE_OFF (0u)

/** \brief  Length for Ifx_GTM_TBU_CHEN_Bits.ENDIS_CH0 */
#define IFX_GTM_TBU_CHEN_ENDIS_CH0_LEN (2u)

/** \brief  Mask for Ifx_GTM_TBU_CHEN_Bits.ENDIS_CH0 */
#define IFX_GTM_TBU_CHEN_ENDIS_CH0_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TBU_CHEN_Bits.ENDIS_CH0 */
#define IFX_GTM_TBU_CHEN_ENDIS_CH0_OFF (0u)

/** \brief  Length for Ifx_GTM_TBU_CHEN_Bits.ENDIS_CH1 */
#define IFX_GTM_TBU_CHEN_ENDIS_CH1_LEN (2u)

/** \brief  Mask for Ifx_GTM_TBU_CHEN_Bits.ENDIS_CH1 */
#define IFX_GTM_TBU_CHEN_ENDIS_CH1_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TBU_CHEN_Bits.ENDIS_CH1 */
#define IFX_GTM_TBU_CHEN_ENDIS_CH1_OFF (2u)

/** \brief  Length for Ifx_GTM_TBU_CHEN_Bits.ENDIS_CH2 */
#define IFX_GTM_TBU_CHEN_ENDIS_CH2_LEN (2u)

/** \brief  Mask for Ifx_GTM_TBU_CHEN_Bits.ENDIS_CH2 */
#define IFX_GTM_TBU_CHEN_ENDIS_CH2_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TBU_CHEN_Bits.ENDIS_CH2 */
#define IFX_GTM_TBU_CHEN_ENDIS_CH2_OFF (4u)

/** \brief  Length for Ifx_GTM_TIM_AUX_IN_SRC_Bits.SRC_CH0 */
#define IFX_GTM_TIM_AUX_IN_SRC_SRC_CH0_LEN (1u)

/** \brief  Mask for Ifx_GTM_TIM_AUX_IN_SRC_Bits.SRC_CH0 */
#define IFX_GTM_TIM_AUX_IN_SRC_SRC_CH0_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TIM_AUX_IN_SRC_Bits.SRC_CH0 */
#define IFX_GTM_TIM_AUX_IN_SRC_SRC_CH0_OFF (0u)

/** \brief  Length for Ifx_GTM_TIM_AUX_IN_SRC_Bits.SRC_CH1 */
#define IFX_GTM_TIM_AUX_IN_SRC_SRC_CH1_LEN (1u)

/** \brief  Mask for Ifx_GTM_TIM_AUX_IN_SRC_Bits.SRC_CH1 */
#define IFX_GTM_TIM_AUX_IN_SRC_SRC_CH1_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TIM_AUX_IN_SRC_Bits.SRC_CH1 */
#define IFX_GTM_TIM_AUX_IN_SRC_SRC_CH1_OFF (1u)

/** \brief  Length for Ifx_GTM_TIM_AUX_IN_SRC_Bits.SRC_CH2 */
#define IFX_GTM_TIM_AUX_IN_SRC_SRC_CH2_LEN (1u)

/** \brief  Mask for Ifx_GTM_TIM_AUX_IN_SRC_Bits.SRC_CH2 */
#define IFX_GTM_TIM_AUX_IN_SRC_SRC_CH2_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TIM_AUX_IN_SRC_Bits.SRC_CH2 */
#define IFX_GTM_TIM_AUX_IN_SRC_SRC_CH2_OFF (2u)

/** \brief  Length for Ifx_GTM_TIM_AUX_IN_SRC_Bits.SRC_CH3 */
#define IFX_GTM_TIM_AUX_IN_SRC_SRC_CH3_LEN (1u)

/** \brief  Mask for Ifx_GTM_TIM_AUX_IN_SRC_Bits.SRC_CH3 */
#define IFX_GTM_TIM_AUX_IN_SRC_SRC_CH3_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TIM_AUX_IN_SRC_Bits.SRC_CH3 */
#define IFX_GTM_TIM_AUX_IN_SRC_SRC_CH3_OFF (3u)

/** \brief  Length for Ifx_GTM_TIM_AUX_IN_SRC_Bits.SRC_CH4 */
#define IFX_GTM_TIM_AUX_IN_SRC_SRC_CH4_LEN (1u)

/** \brief  Mask for Ifx_GTM_TIM_AUX_IN_SRC_Bits.SRC_CH4 */
#define IFX_GTM_TIM_AUX_IN_SRC_SRC_CH4_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TIM_AUX_IN_SRC_Bits.SRC_CH4 */
#define IFX_GTM_TIM_AUX_IN_SRC_SRC_CH4_OFF (4u)

/** \brief  Length for Ifx_GTM_TIM_AUX_IN_SRC_Bits.SRC_CH5 */
#define IFX_GTM_TIM_AUX_IN_SRC_SRC_CH5_LEN (1u)

/** \brief  Mask for Ifx_GTM_TIM_AUX_IN_SRC_Bits.SRC_CH5 */
#define IFX_GTM_TIM_AUX_IN_SRC_SRC_CH5_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TIM_AUX_IN_SRC_Bits.SRC_CH5 */
#define IFX_GTM_TIM_AUX_IN_SRC_SRC_CH5_OFF (5u)

/** \brief  Length for Ifx_GTM_TIM_AUX_IN_SRC_Bits.SRC_CH6 */
#define IFX_GTM_TIM_AUX_IN_SRC_SRC_CH6_LEN (1u)

/** \brief  Mask for Ifx_GTM_TIM_AUX_IN_SRC_Bits.SRC_CH6 */
#define IFX_GTM_TIM_AUX_IN_SRC_SRC_CH6_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TIM_AUX_IN_SRC_Bits.SRC_CH6 */
#define IFX_GTM_TIM_AUX_IN_SRC_SRC_CH6_OFF (6u)

/** \brief  Length for Ifx_GTM_TIM_AUX_IN_SRC_Bits.SRC_CH7 */
#define IFX_GTM_TIM_AUX_IN_SRC_SRC_CH7_LEN (1u)

/** \brief  Mask for Ifx_GTM_TIM_AUX_IN_SRC_Bits.SRC_CH7 */
#define IFX_GTM_TIM_AUX_IN_SRC_SRC_CH7_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TIM_AUX_IN_SRC_Bits.SRC_CH7 */
#define IFX_GTM_TIM_AUX_IN_SRC_SRC_CH7_OFF (7u)

/** \brief  Length for Ifx_GTM_TIM_CH_CNT_Bits.CNT */
#define IFX_GTM_TIM_CH_CNT_CNT_LEN (24u)

/** \brief  Mask for Ifx_GTM_TIM_CH_CNT_Bits.CNT */
#define IFX_GTM_TIM_CH_CNT_CNT_MSK (0xffffffu)

/** \brief  Offset for Ifx_GTM_TIM_CH_CNT_Bits.CNT */
#define IFX_GTM_TIM_CH_CNT_CNT_OFF (0u)

/** \brief  Length for Ifx_GTM_TIM_CH_CNTS_Bits.CNTS */
#define IFX_GTM_TIM_CH_CNTS_CNTS_LEN (24u)

/** \brief  Mask for Ifx_GTM_TIM_CH_CNTS_Bits.CNTS */
#define IFX_GTM_TIM_CH_CNTS_CNTS_MSK (0xffffffu)

/** \brief  Offset for Ifx_GTM_TIM_CH_CNTS_Bits.CNTS */
#define IFX_GTM_TIM_CH_CNTS_CNTS_OFF (0u)

/** \brief  Length for Ifx_GTM_TIM_CH_CNTS_Bits.ECNT */
#define IFX_GTM_TIM_CH_CNTS_ECNT_LEN (8u)

/** \brief  Mask for Ifx_GTM_TIM_CH_CNTS_Bits.ECNT */
#define IFX_GTM_TIM_CH_CNTS_ECNT_MSK (0xffu)

/** \brief  Offset for Ifx_GTM_TIM_CH_CNTS_Bits.ECNT */
#define IFX_GTM_TIM_CH_CNTS_ECNT_OFF (24u)

/** \brief  Length for Ifx_GTM_TIM_CH_CTRL_Bits.ARU_EN */
#define IFX_GTM_TIM_CH_CTRL_ARU_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_TIM_CH_CTRL_Bits.ARU_EN */
#define IFX_GTM_TIM_CH_CTRL_ARU_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TIM_CH_CTRL_Bits.ARU_EN */
#define IFX_GTM_TIM_CH_CTRL_ARU_EN_OFF (5u)

/** \brief  Length for Ifx_GTM_TIM_CH_CTRL_Bits.CICTRL */
#define IFX_GTM_TIM_CH_CTRL_CICTRL_LEN (1u)

/** \brief  Mask for Ifx_GTM_TIM_CH_CTRL_Bits.CICTRL */
#define IFX_GTM_TIM_CH_CTRL_CICTRL_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TIM_CH_CTRL_Bits.CICTRL */
#define IFX_GTM_TIM_CH_CTRL_CICTRL_OFF (6u)

/** \brief  Length for Ifx_GTM_TIM_CH_CTRL_Bits.CLK_SEL */
#define IFX_GTM_TIM_CH_CTRL_CLK_SEL_LEN (3u)

/** \brief  Mask for Ifx_GTM_TIM_CH_CTRL_Bits.CLK_SEL */
#define IFX_GTM_TIM_CH_CTRL_CLK_SEL_MSK (0x7u)

/** \brief  Offset for Ifx_GTM_TIM_CH_CTRL_Bits.CLK_SEL */
#define IFX_GTM_TIM_CH_CTRL_CLK_SEL_OFF (24u)

/** \brief  Length for Ifx_GTM_TIM_CH_CTRL_Bits.CNTS_SEL */
#define IFX_GTM_TIM_CH_CTRL_CNTS_SEL_LEN (1u)

/** \brief  Mask for Ifx_GTM_TIM_CH_CTRL_Bits.CNTS_SEL */
#define IFX_GTM_TIM_CH_CTRL_CNTS_SEL_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TIM_CH_CTRL_Bits.CNTS_SEL */
#define IFX_GTM_TIM_CH_CTRL_CNTS_SEL_OFF (12u)

/** \brief  Length for Ifx_GTM_TIM_CH_CTRL_Bits.DSL */
#define IFX_GTM_TIM_CH_CTRL_DSL_LEN (1u)

/** \brief  Mask for Ifx_GTM_TIM_CH_CTRL_Bits.DSL */
#define IFX_GTM_TIM_CH_CTRL_DSL_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TIM_CH_CTRL_Bits.DSL */
#define IFX_GTM_TIM_CH_CTRL_DSL_OFF (13u)

/** \brief  Length for Ifx_GTM_TIM_CH_CTRL_Bits.ECNT_RESET */
#define IFX_GTM_TIM_CH_CTRL_ECNT_RESET_LEN (1u)

/** \brief  Mask for Ifx_GTM_TIM_CH_CTRL_Bits.ECNT_RESET */
#define IFX_GTM_TIM_CH_CTRL_ECNT_RESET_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TIM_CH_CTRL_Bits.ECNT_RESET */
#define IFX_GTM_TIM_CH_CTRL_ECNT_RESET_OFF (15u)

/** \brief  Length for Ifx_GTM_TIM_CH_CTRL_Bits.EGPR0_SEL */
#define IFX_GTM_TIM_CH_CTRL_EGPR0_SEL_LEN (1u)

/** \brief  Mask for Ifx_GTM_TIM_CH_CTRL_Bits.EGPR0_SEL */
#define IFX_GTM_TIM_CH_CTRL_EGPR0_SEL_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TIM_CH_CTRL_Bits.EGPR0_SEL */
#define IFX_GTM_TIM_CH_CTRL_EGPR0_SEL_OFF (28u)

/** \brief  Length for Ifx_GTM_TIM_CH_CTRL_Bits.EGPR1_SEL */
#define IFX_GTM_TIM_CH_CTRL_EGPR1_SEL_LEN (1u)

/** \brief  Mask for Ifx_GTM_TIM_CH_CTRL_Bits.EGPR1_SEL */
#define IFX_GTM_TIM_CH_CTRL_EGPR1_SEL_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TIM_CH_CTRL_Bits.EGPR1_SEL */
#define IFX_GTM_TIM_CH_CTRL_EGPR1_SEL_OFF (29u)

/** \brief  Length for Ifx_GTM_TIM_CH_CTRL_Bits.EXT_CAP_EN */
#define IFX_GTM_TIM_CH_CTRL_EXT_CAP_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_TIM_CH_CTRL_Bits.EXT_CAP_EN */
#define IFX_GTM_TIM_CH_CTRL_EXT_CAP_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TIM_CH_CTRL_Bits.EXT_CAP_EN */
#define IFX_GTM_TIM_CH_CTRL_EXT_CAP_EN_OFF (19u)

/** \brief  Length for Ifx_GTM_TIM_CH_CTRL_Bits.FLT_CNT_FRQ */
#define IFX_GTM_TIM_CH_CTRL_FLT_CNT_FRQ_LEN (2u)

/** \brief  Mask for Ifx_GTM_TIM_CH_CTRL_Bits.FLT_CNT_FRQ */
#define IFX_GTM_TIM_CH_CTRL_FLT_CNT_FRQ_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TIM_CH_CTRL_Bits.FLT_CNT_FRQ */
#define IFX_GTM_TIM_CH_CTRL_FLT_CNT_FRQ_OFF (17u)

/** \brief  Length for Ifx_GTM_TIM_CH_CTRL_Bits.FLT_CTR_FE */
#define IFX_GTM_TIM_CH_CTRL_FLT_CTR_FE_LEN (1u)

/** \brief  Mask for Ifx_GTM_TIM_CH_CTRL_Bits.FLT_CTR_FE */
#define IFX_GTM_TIM_CH_CTRL_FLT_CTR_FE_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TIM_CH_CTRL_Bits.FLT_CTR_FE */
#define IFX_GTM_TIM_CH_CTRL_FLT_CTR_FE_OFF (23u)

/** \brief  Length for Ifx_GTM_TIM_CH_CTRL_Bits.FLT_CTR_RE */
#define IFX_GTM_TIM_CH_CTRL_FLT_CTR_RE_LEN (1u)

/** \brief  Mask for Ifx_GTM_TIM_CH_CTRL_Bits.FLT_CTR_RE */
#define IFX_GTM_TIM_CH_CTRL_FLT_CTR_RE_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TIM_CH_CTRL_Bits.FLT_CTR_RE */
#define IFX_GTM_TIM_CH_CTRL_FLT_CTR_RE_OFF (21u)

/** \brief  Length for Ifx_GTM_TIM_CH_CTRL_Bits.FLT_EN */
#define IFX_GTM_TIM_CH_CTRL_FLT_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_TIM_CH_CTRL_Bits.FLT_EN */
#define IFX_GTM_TIM_CH_CTRL_FLT_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TIM_CH_CTRL_Bits.FLT_EN */
#define IFX_GTM_TIM_CH_CTRL_FLT_EN_OFF (16u)

/** \brief  Length for Ifx_GTM_TIM_CH_CTRL_Bits.FLT_MODE_FE */
#define IFX_GTM_TIM_CH_CTRL_FLT_MODE_FE_LEN (1u)

/** \brief  Mask for Ifx_GTM_TIM_CH_CTRL_Bits.FLT_MODE_FE */
#define IFX_GTM_TIM_CH_CTRL_FLT_MODE_FE_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TIM_CH_CTRL_Bits.FLT_MODE_FE */
#define IFX_GTM_TIM_CH_CTRL_FLT_MODE_FE_OFF (22u)

/** \brief  Length for Ifx_GTM_TIM_CH_CTRL_Bits.FLT_MODE_RE */
#define IFX_GTM_TIM_CH_CTRL_FLT_MODE_RE_LEN (1u)

/** \brief  Mask for Ifx_GTM_TIM_CH_CTRL_Bits.FLT_MODE_RE */
#define IFX_GTM_TIM_CH_CTRL_FLT_MODE_RE_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TIM_CH_CTRL_Bits.FLT_MODE_RE */
#define IFX_GTM_TIM_CH_CTRL_FLT_MODE_RE_OFF (20u)

/** \brief  Length for Ifx_GTM_TIM_CH_CTRL_Bits.FR_ECNT_OFL */
#define IFX_GTM_TIM_CH_CTRL_FR_ECNT_OFL_LEN (1u)

/** \brief  Mask for Ifx_GTM_TIM_CH_CTRL_Bits.FR_ECNT_OFL */
#define IFX_GTM_TIM_CH_CTRL_FR_ECNT_OFL_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TIM_CH_CTRL_Bits.FR_ECNT_OFL */
#define IFX_GTM_TIM_CH_CTRL_FR_ECNT_OFL_OFF (27u)

/** \brief  Length for Ifx_GTM_TIM_CH_CTRL_Bits.GPR0_SEL */
#define IFX_GTM_TIM_CH_CTRL_GPR0_SEL_LEN (2u)

/** \brief  Mask for Ifx_GTM_TIM_CH_CTRL_Bits.GPR0_SEL */
#define IFX_GTM_TIM_CH_CTRL_GPR0_SEL_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TIM_CH_CTRL_Bits.GPR0_SEL */
#define IFX_GTM_TIM_CH_CTRL_GPR0_SEL_OFF (8u)

/** \brief  Length for Ifx_GTM_TIM_CH_CTRL_Bits.GPR1_SEL */
#define IFX_GTM_TIM_CH_CTRL_GPR1_SEL_LEN (2u)

/** \brief  Mask for Ifx_GTM_TIM_CH_CTRL_Bits.GPR1_SEL */
#define IFX_GTM_TIM_CH_CTRL_GPR1_SEL_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TIM_CH_CTRL_Bits.GPR1_SEL */
#define IFX_GTM_TIM_CH_CTRL_GPR1_SEL_OFF (10u)

/** \brief  Length for Ifx_GTM_TIM_CH_CTRL_Bits.ISL */
#define IFX_GTM_TIM_CH_CTRL_ISL_LEN (1u)

/** \brief  Mask for Ifx_GTM_TIM_CH_CTRL_Bits.ISL */
#define IFX_GTM_TIM_CH_CTRL_ISL_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TIM_CH_CTRL_Bits.ISL */
#define IFX_GTM_TIM_CH_CTRL_ISL_OFF (14u)

/** \brief  Length for Ifx_GTM_TIM_CH_CTRL_Bits.OSM */
#define IFX_GTM_TIM_CH_CTRL_OSM_LEN (1u)

/** \brief  Mask for Ifx_GTM_TIM_CH_CTRL_Bits.OSM */
#define IFX_GTM_TIM_CH_CTRL_OSM_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TIM_CH_CTRL_Bits.OSM */
#define IFX_GTM_TIM_CH_CTRL_OSM_OFF (4u)

/** \brief  Length for Ifx_GTM_TIM_CH_CTRL_Bits.TBU0_SEL */
#define IFX_GTM_TIM_CH_CTRL_TBU0_SEL_LEN (1u)

/** \brief  Mask for Ifx_GTM_TIM_CH_CTRL_Bits.TBU0_SEL */
#define IFX_GTM_TIM_CH_CTRL_TBU0_SEL_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TIM_CH_CTRL_Bits.TBU0_SEL */
#define IFX_GTM_TIM_CH_CTRL_TBU0_SEL_OFF (7u)

/** \brief  Length for Ifx_GTM_TIM_CH_CTRL_Bits.TIM_EN */
#define IFX_GTM_TIM_CH_CTRL_TIM_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_TIM_CH_CTRL_Bits.TIM_EN */
#define IFX_GTM_TIM_CH_CTRL_TIM_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TIM_CH_CTRL_Bits.TIM_EN */
#define IFX_GTM_TIM_CH_CTRL_TIM_EN_OFF (0u)

/** \brief  Length for Ifx_GTM_TIM_CH_CTRL_Bits.TIM_MODE */
#define IFX_GTM_TIM_CH_CTRL_TIM_MODE_LEN (3u)

/** \brief  Mask for Ifx_GTM_TIM_CH_CTRL_Bits.TIM_MODE */
#define IFX_GTM_TIM_CH_CTRL_TIM_MODE_MSK (0x7u)

/** \brief  Offset for Ifx_GTM_TIM_CH_CTRL_Bits.TIM_MODE */
#define IFX_GTM_TIM_CH_CTRL_TIM_MODE_OFF (1u)

/** \brief  Length for Ifx_GTM_TIM_CH_CTRL_Bits.TOCTRL */
#define IFX_GTM_TIM_CH_CTRL_TOCTRL_LEN (2u)

/** \brief  Mask for Ifx_GTM_TIM_CH_CTRL_Bits.TOCTRL */
#define IFX_GTM_TIM_CH_CTRL_TOCTRL_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TIM_CH_CTRL_Bits.TOCTRL */
#define IFX_GTM_TIM_CH_CTRL_TOCTRL_OFF (30u)

/** \brief  Length for Ifx_GTM_TIM_CH_ECNT_Bits.ECNT */
#define IFX_GTM_TIM_CH_ECNT_ECNT_LEN (16u)

/** \brief  Mask for Ifx_GTM_TIM_CH_ECNT_Bits.ECNT */
#define IFX_GTM_TIM_CH_ECNT_ECNT_MSK (0xffffu)

/** \brief  Offset for Ifx_GTM_TIM_CH_ECNT_Bits.ECNT */
#define IFX_GTM_TIM_CH_ECNT_ECNT_OFF (0u)

/** \brief  Length for Ifx_GTM_TIM_CH_ECTRL_Bits.EXT_CAP_SRC */
#define IFX_GTM_TIM_CH_ECTRL_EXT_CAP_SRC_LEN (3u)

/** \brief  Mask for Ifx_GTM_TIM_CH_ECTRL_Bits.EXT_CAP_SRC */
#define IFX_GTM_TIM_CH_ECTRL_EXT_CAP_SRC_MSK (0x7u)

/** \brief  Offset for Ifx_GTM_TIM_CH_ECTRL_Bits.EXT_CAP_SRC */
#define IFX_GTM_TIM_CH_ECTRL_EXT_CAP_SRC_OFF (0u)

/** \brief  Length for Ifx_GTM_TIM_CH_EIRQ_EN_Bits.CNTOFL_EIRQ_EN */
#define IFX_GTM_TIM_CH_EIRQ_EN_CNTOFL_EIRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_TIM_CH_EIRQ_EN_Bits.CNTOFL_EIRQ_EN */
#define IFX_GTM_TIM_CH_EIRQ_EN_CNTOFL_EIRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TIM_CH_EIRQ_EN_Bits.CNTOFL_EIRQ_EN */
#define IFX_GTM_TIM_CH_EIRQ_EN_CNTOFL_EIRQ_EN_OFF (2u)

/** \brief  Length for Ifx_GTM_TIM_CH_EIRQ_EN_Bits.ECNTOFL_EIRQ_EN */
#define IFX_GTM_TIM_CH_EIRQ_EN_ECNTOFL_EIRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_TIM_CH_EIRQ_EN_Bits.ECNTOFL_EIRQ_EN */
#define IFX_GTM_TIM_CH_EIRQ_EN_ECNTOFL_EIRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TIM_CH_EIRQ_EN_Bits.ECNTOFL_EIRQ_EN */
#define IFX_GTM_TIM_CH_EIRQ_EN_ECNTOFL_EIRQ_EN_OFF (1u)

/** \brief  Length for Ifx_GTM_TIM_CH_EIRQ_EN_Bits.GLITCHDET_EIRQ_EN */
#define IFX_GTM_TIM_CH_EIRQ_EN_GLITCHDET_EIRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_TIM_CH_EIRQ_EN_Bits.GLITCHDET_EIRQ_EN */
#define IFX_GTM_TIM_CH_EIRQ_EN_GLITCHDET_EIRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TIM_CH_EIRQ_EN_Bits.GLITCHDET_EIRQ_EN */
#define IFX_GTM_TIM_CH_EIRQ_EN_GLITCHDET_EIRQ_EN_OFF (5u)

/** \brief  Length for Ifx_GTM_TIM_CH_EIRQ_EN_Bits.GPROFL_EIRQ_EN */
#define IFX_GTM_TIM_CH_EIRQ_EN_GPROFL_EIRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_TIM_CH_EIRQ_EN_Bits.GPROFL_EIRQ_EN */
#define IFX_GTM_TIM_CH_EIRQ_EN_GPROFL_EIRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TIM_CH_EIRQ_EN_Bits.GPROFL_EIRQ_EN */
#define IFX_GTM_TIM_CH_EIRQ_EN_GPROFL_EIRQ_EN_OFF (3u)

/** \brief  Length for Ifx_GTM_TIM_CH_EIRQ_EN_Bits.NEWVAL_EIRQ_EN */
#define IFX_GTM_TIM_CH_EIRQ_EN_NEWVAL_EIRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_TIM_CH_EIRQ_EN_Bits.NEWVAL_EIRQ_EN */
#define IFX_GTM_TIM_CH_EIRQ_EN_NEWVAL_EIRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TIM_CH_EIRQ_EN_Bits.NEWVAL_EIRQ_EN */
#define IFX_GTM_TIM_CH_EIRQ_EN_NEWVAL_EIRQ_EN_OFF (0u)

/** \brief  Length for Ifx_GTM_TIM_CH_EIRQ_EN_Bits.TODET_EIRQ_EN */
#define IFX_GTM_TIM_CH_EIRQ_EN_TODET_EIRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_TIM_CH_EIRQ_EN_Bits.TODET_EIRQ_EN */
#define IFX_GTM_TIM_CH_EIRQ_EN_TODET_EIRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TIM_CH_EIRQ_EN_Bits.TODET_EIRQ_EN */
#define IFX_GTM_TIM_CH_EIRQ_EN_TODET_EIRQ_EN_OFF (4u)

/** \brief  Length for Ifx_GTM_TIM_CH_FLT_FE_Bits.FLT_FE */
#define IFX_GTM_TIM_CH_FLT_FE_FLT_FE_LEN (24u)

/** \brief  Mask for Ifx_GTM_TIM_CH_FLT_FE_Bits.FLT_FE */
#define IFX_GTM_TIM_CH_FLT_FE_FLT_FE_MSK (0xffffffu)

/** \brief  Offset for Ifx_GTM_TIM_CH_FLT_FE_Bits.FLT_FE */
#define IFX_GTM_TIM_CH_FLT_FE_FLT_FE_OFF (0u)

/** \brief  Length for Ifx_GTM_TIM_CH_FLT_RE_Bits.FLT_RE */
#define IFX_GTM_TIM_CH_FLT_RE_FLT_RE_LEN (24u)

/** \brief  Mask for Ifx_GTM_TIM_CH_FLT_RE_Bits.FLT_RE */
#define IFX_GTM_TIM_CH_FLT_RE_FLT_RE_MSK (0xffffffu)

/** \brief  Offset for Ifx_GTM_TIM_CH_FLT_RE_Bits.FLT_RE */
#define IFX_GTM_TIM_CH_FLT_RE_FLT_RE_OFF (0u)

/** \brief  Length for Ifx_GTM_TIM_CH_GPR0_Bits.ECNT */
#define IFX_GTM_TIM_CH_GPR0_ECNT_LEN (8u)

/** \brief  Mask for Ifx_GTM_TIM_CH_GPR0_Bits.ECNT */
#define IFX_GTM_TIM_CH_GPR0_ECNT_MSK (0xffu)

/** \brief  Offset for Ifx_GTM_TIM_CH_GPR0_Bits.ECNT */
#define IFX_GTM_TIM_CH_GPR0_ECNT_OFF (24u)

/** \brief  Length for Ifx_GTM_TIM_CH_GPR0_Bits.GPR0 */
#define IFX_GTM_TIM_CH_GPR0_GPR0_LEN (24u)

/** \brief  Mask for Ifx_GTM_TIM_CH_GPR0_Bits.GPR0 */
#define IFX_GTM_TIM_CH_GPR0_GPR0_MSK (0xffffffu)

/** \brief  Offset for Ifx_GTM_TIM_CH_GPR0_Bits.GPR0 */
#define IFX_GTM_TIM_CH_GPR0_GPR0_OFF (0u)

/** \brief  Length for Ifx_GTM_TIM_CH_GPR1_Bits.ECNT */
#define IFX_GTM_TIM_CH_GPR1_ECNT_LEN (8u)

/** \brief  Mask for Ifx_GTM_TIM_CH_GPR1_Bits.ECNT */
#define IFX_GTM_TIM_CH_GPR1_ECNT_MSK (0xffu)

/** \brief  Offset for Ifx_GTM_TIM_CH_GPR1_Bits.ECNT */
#define IFX_GTM_TIM_CH_GPR1_ECNT_OFF (24u)

/** \brief  Length for Ifx_GTM_TIM_CH_GPR1_Bits.GPR1 */
#define IFX_GTM_TIM_CH_GPR1_GPR1_LEN (24u)

/** \brief  Mask for Ifx_GTM_TIM_CH_GPR1_Bits.GPR1 */
#define IFX_GTM_TIM_CH_GPR1_GPR1_MSK (0xffffffu)

/** \brief  Offset for Ifx_GTM_TIM_CH_GPR1_Bits.GPR1 */
#define IFX_GTM_TIM_CH_GPR1_GPR1_OFF (0u)

/** \brief  Length for Ifx_GTM_TIM_CH_IRQ_EN_Bits.CNTOFL_IRQ_EN */
#define IFX_GTM_TIM_CH_IRQ_EN_CNTOFL_IRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_TIM_CH_IRQ_EN_Bits.CNTOFL_IRQ_EN */
#define IFX_GTM_TIM_CH_IRQ_EN_CNTOFL_IRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TIM_CH_IRQ_EN_Bits.CNTOFL_IRQ_EN */
#define IFX_GTM_TIM_CH_IRQ_EN_CNTOFL_IRQ_EN_OFF (2u)

/** \brief  Length for Ifx_GTM_TIM_CH_IRQ_EN_Bits.ECNTOFL_IRQ_EN */
#define IFX_GTM_TIM_CH_IRQ_EN_ECNTOFL_IRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_TIM_CH_IRQ_EN_Bits.ECNTOFL_IRQ_EN */
#define IFX_GTM_TIM_CH_IRQ_EN_ECNTOFL_IRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TIM_CH_IRQ_EN_Bits.ECNTOFL_IRQ_EN */
#define IFX_GTM_TIM_CH_IRQ_EN_ECNTOFL_IRQ_EN_OFF (1u)

/** \brief  Length for Ifx_GTM_TIM_CH_IRQ_EN_Bits.GLITCHDET_IRQ_EN */
#define IFX_GTM_TIM_CH_IRQ_EN_GLITCHDET_IRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_TIM_CH_IRQ_EN_Bits.GLITCHDET_IRQ_EN */
#define IFX_GTM_TIM_CH_IRQ_EN_GLITCHDET_IRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TIM_CH_IRQ_EN_Bits.GLITCHDET_IRQ_EN */
#define IFX_GTM_TIM_CH_IRQ_EN_GLITCHDET_IRQ_EN_OFF (5u)

/** \brief  Length for Ifx_GTM_TIM_CH_IRQ_EN_Bits.GPROFL_IRQ_EN */
#define IFX_GTM_TIM_CH_IRQ_EN_GPROFL_IRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_TIM_CH_IRQ_EN_Bits.GPROFL_IRQ_EN */
#define IFX_GTM_TIM_CH_IRQ_EN_GPROFL_IRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TIM_CH_IRQ_EN_Bits.GPROFL_IRQ_EN */
#define IFX_GTM_TIM_CH_IRQ_EN_GPROFL_IRQ_EN_OFF (3u)

/** \brief  Length for Ifx_GTM_TIM_CH_IRQ_EN_Bits.NEWVAL_IRQ_EN */
#define IFX_GTM_TIM_CH_IRQ_EN_NEWVAL_IRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_TIM_CH_IRQ_EN_Bits.NEWVAL_IRQ_EN */
#define IFX_GTM_TIM_CH_IRQ_EN_NEWVAL_IRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TIM_CH_IRQ_EN_Bits.NEWVAL_IRQ_EN */
#define IFX_GTM_TIM_CH_IRQ_EN_NEWVAL_IRQ_EN_OFF (0u)

/** \brief  Length for Ifx_GTM_TIM_CH_IRQ_EN_Bits.TODET_IRQ_EN */
#define IFX_GTM_TIM_CH_IRQ_EN_TODET_IRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_TIM_CH_IRQ_EN_Bits.TODET_IRQ_EN */
#define IFX_GTM_TIM_CH_IRQ_EN_TODET_IRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TIM_CH_IRQ_EN_Bits.TODET_IRQ_EN */
#define IFX_GTM_TIM_CH_IRQ_EN_TODET_IRQ_EN_OFF (4u)

/** \brief  Length for Ifx_GTM_TIM_CH_IRQ_FORCINT_Bits.TRG_CNTOFL */
#define IFX_GTM_TIM_CH_IRQ_FORCINT_TRG_CNTOFL_LEN (1u)

/** \brief  Mask for Ifx_GTM_TIM_CH_IRQ_FORCINT_Bits.TRG_CNTOFL */
#define IFX_GTM_TIM_CH_IRQ_FORCINT_TRG_CNTOFL_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TIM_CH_IRQ_FORCINT_Bits.TRG_CNTOFL */
#define IFX_GTM_TIM_CH_IRQ_FORCINT_TRG_CNTOFL_OFF (2u)

/** \brief  Length for Ifx_GTM_TIM_CH_IRQ_FORCINT_Bits.TRG_ECNTOFL */
#define IFX_GTM_TIM_CH_IRQ_FORCINT_TRG_ECNTOFL_LEN (1u)

/** \brief  Mask for Ifx_GTM_TIM_CH_IRQ_FORCINT_Bits.TRG_ECNTOFL */
#define IFX_GTM_TIM_CH_IRQ_FORCINT_TRG_ECNTOFL_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TIM_CH_IRQ_FORCINT_Bits.TRG_ECNTOFL */
#define IFX_GTM_TIM_CH_IRQ_FORCINT_TRG_ECNTOFL_OFF (1u)

/** \brief  Length for Ifx_GTM_TIM_CH_IRQ_FORCINT_Bits.TRG_GLITCHDET */
#define IFX_GTM_TIM_CH_IRQ_FORCINT_TRG_GLITCHDET_LEN (1u)

/** \brief  Mask for Ifx_GTM_TIM_CH_IRQ_FORCINT_Bits.TRG_GLITCHDET */
#define IFX_GTM_TIM_CH_IRQ_FORCINT_TRG_GLITCHDET_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TIM_CH_IRQ_FORCINT_Bits.TRG_GLITCHDET */
#define IFX_GTM_TIM_CH_IRQ_FORCINT_TRG_GLITCHDET_OFF (5u)

/** \brief  Length for Ifx_GTM_TIM_CH_IRQ_FORCINT_Bits.TRG_GPROFL */
#define IFX_GTM_TIM_CH_IRQ_FORCINT_TRG_GPROFL_LEN (1u)

/** \brief  Mask for Ifx_GTM_TIM_CH_IRQ_FORCINT_Bits.TRG_GPROFL */
#define IFX_GTM_TIM_CH_IRQ_FORCINT_TRG_GPROFL_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TIM_CH_IRQ_FORCINT_Bits.TRG_GPROFL */
#define IFX_GTM_TIM_CH_IRQ_FORCINT_TRG_GPROFL_OFF (3u)

/** \brief  Length for Ifx_GTM_TIM_CH_IRQ_FORCINT_Bits.TRG_NEWVAL */
#define IFX_GTM_TIM_CH_IRQ_FORCINT_TRG_NEWVAL_LEN (1u)

/** \brief  Mask for Ifx_GTM_TIM_CH_IRQ_FORCINT_Bits.TRG_NEWVAL */
#define IFX_GTM_TIM_CH_IRQ_FORCINT_TRG_NEWVAL_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TIM_CH_IRQ_FORCINT_Bits.TRG_NEWVAL */
#define IFX_GTM_TIM_CH_IRQ_FORCINT_TRG_NEWVAL_OFF (0u)

/** \brief  Length for Ifx_GTM_TIM_CH_IRQ_FORCINT_Bits.TRG_TODET */
#define IFX_GTM_TIM_CH_IRQ_FORCINT_TRG_TODET_LEN (1u)

/** \brief  Mask for Ifx_GTM_TIM_CH_IRQ_FORCINT_Bits.TRG_TODET */
#define IFX_GTM_TIM_CH_IRQ_FORCINT_TRG_TODET_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TIM_CH_IRQ_FORCINT_Bits.TRG_TODET */
#define IFX_GTM_TIM_CH_IRQ_FORCINT_TRG_TODET_OFF (4u)

/** \brief  Length for Ifx_GTM_TIM_CH_IRQ_MODE_Bits.IRQ_MODE */
#define IFX_GTM_TIM_CH_IRQ_MODE_IRQ_MODE_LEN (2u)

/** \brief  Mask for Ifx_GTM_TIM_CH_IRQ_MODE_Bits.IRQ_MODE */
#define IFX_GTM_TIM_CH_IRQ_MODE_IRQ_MODE_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TIM_CH_IRQ_MODE_Bits.IRQ_MODE */
#define IFX_GTM_TIM_CH_IRQ_MODE_IRQ_MODE_OFF (0u)

/** \brief  Length for Ifx_GTM_TIM_CH_IRQ_NOTIFY_Bits.CNTOFL */
#define IFX_GTM_TIM_CH_IRQ_NOTIFY_CNTOFL_LEN (1u)

/** \brief  Mask for Ifx_GTM_TIM_CH_IRQ_NOTIFY_Bits.CNTOFL */
#define IFX_GTM_TIM_CH_IRQ_NOTIFY_CNTOFL_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TIM_CH_IRQ_NOTIFY_Bits.CNTOFL */
#define IFX_GTM_TIM_CH_IRQ_NOTIFY_CNTOFL_OFF (2u)

/** \brief  Length for Ifx_GTM_TIM_CH_IRQ_NOTIFY_Bits.ECNTOFL */
#define IFX_GTM_TIM_CH_IRQ_NOTIFY_ECNTOFL_LEN (1u)

/** \brief  Mask for Ifx_GTM_TIM_CH_IRQ_NOTIFY_Bits.ECNTOFL */
#define IFX_GTM_TIM_CH_IRQ_NOTIFY_ECNTOFL_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TIM_CH_IRQ_NOTIFY_Bits.ECNTOFL */
#define IFX_GTM_TIM_CH_IRQ_NOTIFY_ECNTOFL_OFF (1u)

/** \brief  Length for Ifx_GTM_TIM_CH_IRQ_NOTIFY_Bits.GLITCHDET */
#define IFX_GTM_TIM_CH_IRQ_NOTIFY_GLITCHDET_LEN (1u)

/** \brief  Mask for Ifx_GTM_TIM_CH_IRQ_NOTIFY_Bits.GLITCHDET */
#define IFX_GTM_TIM_CH_IRQ_NOTIFY_GLITCHDET_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TIM_CH_IRQ_NOTIFY_Bits.GLITCHDET */
#define IFX_GTM_TIM_CH_IRQ_NOTIFY_GLITCHDET_OFF (5u)

/** \brief  Length for Ifx_GTM_TIM_CH_IRQ_NOTIFY_Bits.GPROFL */
#define IFX_GTM_TIM_CH_IRQ_NOTIFY_GPROFL_LEN (1u)

/** \brief  Mask for Ifx_GTM_TIM_CH_IRQ_NOTIFY_Bits.GPROFL */
#define IFX_GTM_TIM_CH_IRQ_NOTIFY_GPROFL_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TIM_CH_IRQ_NOTIFY_Bits.GPROFL */
#define IFX_GTM_TIM_CH_IRQ_NOTIFY_GPROFL_OFF (3u)

/** \brief  Length for Ifx_GTM_TIM_CH_IRQ_NOTIFY_Bits.NEWVAL */
#define IFX_GTM_TIM_CH_IRQ_NOTIFY_NEWVAL_LEN (1u)

/** \brief  Mask for Ifx_GTM_TIM_CH_IRQ_NOTIFY_Bits.NEWVAL */
#define IFX_GTM_TIM_CH_IRQ_NOTIFY_NEWVAL_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TIM_CH_IRQ_NOTIFY_Bits.NEWVAL */
#define IFX_GTM_TIM_CH_IRQ_NOTIFY_NEWVAL_OFF (0u)

/** \brief  Length for Ifx_GTM_TIM_CH_IRQ_NOTIFY_Bits.TODET */
#define IFX_GTM_TIM_CH_IRQ_NOTIFY_TODET_LEN (1u)

/** \brief  Mask for Ifx_GTM_TIM_CH_IRQ_NOTIFY_Bits.TODET */
#define IFX_GTM_TIM_CH_IRQ_NOTIFY_TODET_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TIM_CH_IRQ_NOTIFY_Bits.TODET */
#define IFX_GTM_TIM_CH_IRQ_NOTIFY_TODET_OFF (4u)

/** \brief  Length for Ifx_GTM_TIM_CH_TDUC_Bits.TO_CNT */
#define IFX_GTM_TIM_CH_TDUC_TO_CNT_LEN (8u)

/** \brief  Mask for Ifx_GTM_TIM_CH_TDUC_Bits.TO_CNT */
#define IFX_GTM_TIM_CH_TDUC_TO_CNT_MSK (0xffu)

/** \brief  Offset for Ifx_GTM_TIM_CH_TDUC_Bits.TO_CNT */
#define IFX_GTM_TIM_CH_TDUC_TO_CNT_OFF (0u)

/** \brief  Length for Ifx_GTM_TIM_CH_TDUV_Bits.TCS */
#define IFX_GTM_TIM_CH_TDUV_TCS_LEN (3u)

/** \brief  Mask for Ifx_GTM_TIM_CH_TDUV_Bits.TCS */
#define IFX_GTM_TIM_CH_TDUV_TCS_MSK (0x7u)

/** \brief  Offset for Ifx_GTM_TIM_CH_TDUV_Bits.TCS */
#define IFX_GTM_TIM_CH_TDUV_TCS_OFF (28u)

/** \brief  Length for Ifx_GTM_TIM_CH_TDUV_Bits.TOV */
#define IFX_GTM_TIM_CH_TDUV_TOV_LEN (8u)

/** \brief  Mask for Ifx_GTM_TIM_CH_TDUV_Bits.TOV */
#define IFX_GTM_TIM_CH_TDUV_TOV_MSK (0xffu)

/** \brief  Offset for Ifx_GTM_TIM_CH_TDUV_Bits.TOV */
#define IFX_GTM_TIM_CH_TDUV_TOV_OFF (0u)

/** \brief  Length for Ifx_GTM_TIM_IN_SRC_Bits.MODE_0 */
#define IFX_GTM_TIM_IN_SRC_MODE_0_LEN (2u)

/** \brief  Mask for Ifx_GTM_TIM_IN_SRC_Bits.MODE_0 */
#define IFX_GTM_TIM_IN_SRC_MODE_0_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TIM_IN_SRC_Bits.MODE_0 */
#define IFX_GTM_TIM_IN_SRC_MODE_0_OFF (2u)

/** \brief  Length for Ifx_GTM_TIM_IN_SRC_Bits.MODE_1 */
#define IFX_GTM_TIM_IN_SRC_MODE_1_LEN (2u)

/** \brief  Mask for Ifx_GTM_TIM_IN_SRC_Bits.MODE_1 */
#define IFX_GTM_TIM_IN_SRC_MODE_1_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TIM_IN_SRC_Bits.MODE_1 */
#define IFX_GTM_TIM_IN_SRC_MODE_1_OFF (6u)

/** \brief  Length for Ifx_GTM_TIM_IN_SRC_Bits.MODE_2 */
#define IFX_GTM_TIM_IN_SRC_MODE_2_LEN (2u)

/** \brief  Mask for Ifx_GTM_TIM_IN_SRC_Bits.MODE_2 */
#define IFX_GTM_TIM_IN_SRC_MODE_2_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TIM_IN_SRC_Bits.MODE_2 */
#define IFX_GTM_TIM_IN_SRC_MODE_2_OFF (10u)

/** \brief  Length for Ifx_GTM_TIM_IN_SRC_Bits.MODE_3 */
#define IFX_GTM_TIM_IN_SRC_MODE_3_LEN (2u)

/** \brief  Mask for Ifx_GTM_TIM_IN_SRC_Bits.MODE_3 */
#define IFX_GTM_TIM_IN_SRC_MODE_3_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TIM_IN_SRC_Bits.MODE_3 */
#define IFX_GTM_TIM_IN_SRC_MODE_3_OFF (14u)

/** \brief  Length for Ifx_GTM_TIM_IN_SRC_Bits.MODE_4 */
#define IFX_GTM_TIM_IN_SRC_MODE_4_LEN (2u)

/** \brief  Mask for Ifx_GTM_TIM_IN_SRC_Bits.MODE_4 */
#define IFX_GTM_TIM_IN_SRC_MODE_4_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TIM_IN_SRC_Bits.MODE_4 */
#define IFX_GTM_TIM_IN_SRC_MODE_4_OFF (18u)

/** \brief  Length for Ifx_GTM_TIM_IN_SRC_Bits.MODE_5 */
#define IFX_GTM_TIM_IN_SRC_MODE_5_LEN (2u)

/** \brief  Mask for Ifx_GTM_TIM_IN_SRC_Bits.MODE_5 */
#define IFX_GTM_TIM_IN_SRC_MODE_5_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TIM_IN_SRC_Bits.MODE_5 */
#define IFX_GTM_TIM_IN_SRC_MODE_5_OFF (22u)

/** \brief  Length for Ifx_GTM_TIM_IN_SRC_Bits.MODE_6 */
#define IFX_GTM_TIM_IN_SRC_MODE_6_LEN (2u)

/** \brief  Mask for Ifx_GTM_TIM_IN_SRC_Bits.MODE_6 */
#define IFX_GTM_TIM_IN_SRC_MODE_6_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TIM_IN_SRC_Bits.MODE_6 */
#define IFX_GTM_TIM_IN_SRC_MODE_6_OFF (26u)

/** \brief  Length for Ifx_GTM_TIM_IN_SRC_Bits.MODE_7 */
#define IFX_GTM_TIM_IN_SRC_MODE_7_LEN (2u)

/** \brief  Mask for Ifx_GTM_TIM_IN_SRC_Bits.MODE_7 */
#define IFX_GTM_TIM_IN_SRC_MODE_7_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TIM_IN_SRC_Bits.MODE_7 */
#define IFX_GTM_TIM_IN_SRC_MODE_7_OFF (30u)

/** \brief  Length for Ifx_GTM_TIM_IN_SRC_Bits.VAL_0 */
#define IFX_GTM_TIM_IN_SRC_VAL_0_LEN (2u)

/** \brief  Mask for Ifx_GTM_TIM_IN_SRC_Bits.VAL_0 */
#define IFX_GTM_TIM_IN_SRC_VAL_0_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TIM_IN_SRC_Bits.VAL_0 */
#define IFX_GTM_TIM_IN_SRC_VAL_0_OFF (0u)

/** \brief  Length for Ifx_GTM_TIM_IN_SRC_Bits.VAL_1 */
#define IFX_GTM_TIM_IN_SRC_VAL_1_LEN (2u)

/** \brief  Mask for Ifx_GTM_TIM_IN_SRC_Bits.VAL_1 */
#define IFX_GTM_TIM_IN_SRC_VAL_1_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TIM_IN_SRC_Bits.VAL_1 */
#define IFX_GTM_TIM_IN_SRC_VAL_1_OFF (4u)

/** \brief  Length for Ifx_GTM_TIM_IN_SRC_Bits.VAL_2 */
#define IFX_GTM_TIM_IN_SRC_VAL_2_LEN (2u)

/** \brief  Mask for Ifx_GTM_TIM_IN_SRC_Bits.VAL_2 */
#define IFX_GTM_TIM_IN_SRC_VAL_2_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TIM_IN_SRC_Bits.VAL_2 */
#define IFX_GTM_TIM_IN_SRC_VAL_2_OFF (8u)

/** \brief  Length for Ifx_GTM_TIM_IN_SRC_Bits.VAL_3 */
#define IFX_GTM_TIM_IN_SRC_VAL_3_LEN (2u)

/** \brief  Mask for Ifx_GTM_TIM_IN_SRC_Bits.VAL_3 */
#define IFX_GTM_TIM_IN_SRC_VAL_3_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TIM_IN_SRC_Bits.VAL_3 */
#define IFX_GTM_TIM_IN_SRC_VAL_3_OFF (12u)

/** \brief  Length for Ifx_GTM_TIM_IN_SRC_Bits.VAL_4 */
#define IFX_GTM_TIM_IN_SRC_VAL_4_LEN (2u)

/** \brief  Mask for Ifx_GTM_TIM_IN_SRC_Bits.VAL_4 */
#define IFX_GTM_TIM_IN_SRC_VAL_4_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TIM_IN_SRC_Bits.VAL_4 */
#define IFX_GTM_TIM_IN_SRC_VAL_4_OFF (16u)

/** \brief  Length for Ifx_GTM_TIM_IN_SRC_Bits.VAL_5 */
#define IFX_GTM_TIM_IN_SRC_VAL_5_LEN (2u)

/** \brief  Mask for Ifx_GTM_TIM_IN_SRC_Bits.VAL_5 */
#define IFX_GTM_TIM_IN_SRC_VAL_5_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TIM_IN_SRC_Bits.VAL_5 */
#define IFX_GTM_TIM_IN_SRC_VAL_5_OFF (20u)

/** \brief  Length for Ifx_GTM_TIM_IN_SRC_Bits.VAL_6 */
#define IFX_GTM_TIM_IN_SRC_VAL_6_LEN (2u)

/** \brief  Mask for Ifx_GTM_TIM_IN_SRC_Bits.VAL_6 */
#define IFX_GTM_TIM_IN_SRC_VAL_6_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TIM_IN_SRC_Bits.VAL_6 */
#define IFX_GTM_TIM_IN_SRC_VAL_6_OFF (24u)

/** \brief  Length for Ifx_GTM_TIM_IN_SRC_Bits.VAL_7 */
#define IFX_GTM_TIM_IN_SRC_VAL_7_LEN (2u)

/** \brief  Mask for Ifx_GTM_TIM_IN_SRC_Bits.VAL_7 */
#define IFX_GTM_TIM_IN_SRC_VAL_7_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TIM_IN_SRC_Bits.VAL_7 */
#define IFX_GTM_TIM_IN_SRC_VAL_7_OFF (28u)

/** \brief  Length for Ifx_GTM_TIM_RST_Bits.RST_CH0 */
#define IFX_GTM_TIM_RST_RST_CH0_LEN (1u)

/** \brief  Mask for Ifx_GTM_TIM_RST_Bits.RST_CH0 */
#define IFX_GTM_TIM_RST_RST_CH0_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TIM_RST_Bits.RST_CH0 */
#define IFX_GTM_TIM_RST_RST_CH0_OFF (0u)

/** \brief  Length for Ifx_GTM_TIM_RST_Bits.RST_CH1 */
#define IFX_GTM_TIM_RST_RST_CH1_LEN (1u)

/** \brief  Mask for Ifx_GTM_TIM_RST_Bits.RST_CH1 */
#define IFX_GTM_TIM_RST_RST_CH1_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TIM_RST_Bits.RST_CH1 */
#define IFX_GTM_TIM_RST_RST_CH1_OFF (1u)

/** \brief  Length for Ifx_GTM_TIM_RST_Bits.RST_CH2 */
#define IFX_GTM_TIM_RST_RST_CH2_LEN (1u)

/** \brief  Mask for Ifx_GTM_TIM_RST_Bits.RST_CH2 */
#define IFX_GTM_TIM_RST_RST_CH2_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TIM_RST_Bits.RST_CH2 */
#define IFX_GTM_TIM_RST_RST_CH2_OFF (2u)

/** \brief  Length for Ifx_GTM_TIM_RST_Bits.RST_CH3 */
#define IFX_GTM_TIM_RST_RST_CH3_LEN (1u)

/** \brief  Mask for Ifx_GTM_TIM_RST_Bits.RST_CH3 */
#define IFX_GTM_TIM_RST_RST_CH3_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TIM_RST_Bits.RST_CH3 */
#define IFX_GTM_TIM_RST_RST_CH3_OFF (3u)

/** \brief  Length for Ifx_GTM_TIM_RST_Bits.RST_CH4 */
#define IFX_GTM_TIM_RST_RST_CH4_LEN (1u)

/** \brief  Mask for Ifx_GTM_TIM_RST_Bits.RST_CH4 */
#define IFX_GTM_TIM_RST_RST_CH4_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TIM_RST_Bits.RST_CH4 */
#define IFX_GTM_TIM_RST_RST_CH4_OFF (4u)

/** \brief  Length for Ifx_GTM_TIM_RST_Bits.RST_CH5 */
#define IFX_GTM_TIM_RST_RST_CH5_LEN (1u)

/** \brief  Mask for Ifx_GTM_TIM_RST_Bits.RST_CH5 */
#define IFX_GTM_TIM_RST_RST_CH5_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TIM_RST_Bits.RST_CH5 */
#define IFX_GTM_TIM_RST_RST_CH5_OFF (5u)

/** \brief  Length for Ifx_GTM_TIM_RST_Bits.RST_CH6 */
#define IFX_GTM_TIM_RST_RST_CH6_LEN (1u)

/** \brief  Mask for Ifx_GTM_TIM_RST_Bits.RST_CH6 */
#define IFX_GTM_TIM_RST_RST_CH6_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TIM_RST_Bits.RST_CH6 */
#define IFX_GTM_TIM_RST_RST_CH6_OFF (6u)

/** \brief  Length for Ifx_GTM_TIM_RST_Bits.RST_CH7 */
#define IFX_GTM_TIM_RST_RST_CH7_LEN (1u)

/** \brief  Mask for Ifx_GTM_TIM_RST_Bits.RST_CH7 */
#define IFX_GTM_TIM_RST_RST_CH7_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TIM_RST_Bits.RST_CH7 */
#define IFX_GTM_TIM_RST_RST_CH7_OFF (7u)

/** \brief  Length for Ifx_GTM_TOM_CH_CM0_Bits.CM0 */
#define IFX_GTM_TOM_CH_CM0_CM0_LEN (16u)

/** \brief  Mask for Ifx_GTM_TOM_CH_CM0_Bits.CM0 */
#define IFX_GTM_TOM_CH_CM0_CM0_MSK (0xffffu)

/** \brief  Offset for Ifx_GTM_TOM_CH_CM0_Bits.CM0 */
#define IFX_GTM_TOM_CH_CM0_CM0_OFF (0u)

/** \brief  Length for Ifx_GTM_TOM_CH_CM1_Bits.CM1 */
#define IFX_GTM_TOM_CH_CM1_CM1_LEN (16u)

/** \brief  Mask for Ifx_GTM_TOM_CH_CM1_Bits.CM1 */
#define IFX_GTM_TOM_CH_CM1_CM1_MSK (0xffffu)

/** \brief  Offset for Ifx_GTM_TOM_CH_CM1_Bits.CM1 */
#define IFX_GTM_TOM_CH_CM1_CM1_OFF (0u)

/** \brief  Length for Ifx_GTM_TOM_CH_CN0_Bits.CN0 */
#define IFX_GTM_TOM_CH_CN0_CN0_LEN (16u)

/** \brief  Mask for Ifx_GTM_TOM_CH_CN0_Bits.CN0 */
#define IFX_GTM_TOM_CH_CN0_CN0_MSK (0xffffu)

/** \brief  Offset for Ifx_GTM_TOM_CH_CN0_Bits.CN0 */
#define IFX_GTM_TOM_CH_CN0_CN0_OFF (0u)

/** \brief  Length for Ifx_GTM_TOM_CH_CTRL_Bits.BITREV */
#define IFX_GTM_TOM_CH_CTRL_BITREV_LEN (1u)

/** \brief  Mask for Ifx_GTM_TOM_CH_CTRL_Bits.BITREV */
#define IFX_GTM_TOM_CH_CTRL_BITREV_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TOM_CH_CTRL_Bits.BITREV */
#define IFX_GTM_TOM_CH_CTRL_BITREV_OFF (27u)

/** \brief  Length for Ifx_GTM_TOM_CH_CTRL_Bits.CLK_SRC_SR */
#define IFX_GTM_TOM_CH_CTRL_CLK_SRC_SR_LEN (3u)

/** \brief  Mask for Ifx_GTM_TOM_CH_CTRL_Bits.CLK_SRC_SR */
#define IFX_GTM_TOM_CH_CTRL_CLK_SRC_SR_MSK (0x7u)

/** \brief  Offset for Ifx_GTM_TOM_CH_CTRL_Bits.CLK_SRC_SR */
#define IFX_GTM_TOM_CH_CTRL_CLK_SRC_SR_OFF (12u)

/** \brief  Length for Ifx_GTM_TOM_CH_CTRL_Bits.GCM */
#define IFX_GTM_TOM_CH_CTRL_GCM_LEN (1u)

/** \brief  Mask for Ifx_GTM_TOM_CH_CTRL_Bits.GCM */
#define IFX_GTM_TOM_CH_CTRL_GCM_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TOM_CH_CTRL_Bits.GCM */
#define IFX_GTM_TOM_CH_CTRL_GCM_OFF (29u)

/** \brief  Length for Ifx_GTM_TOM_CH_CTRL_Bits.OSM */
#define IFX_GTM_TOM_CH_CTRL_OSM_LEN (1u)

/** \brief  Mask for Ifx_GTM_TOM_CH_CTRL_Bits.OSM */
#define IFX_GTM_TOM_CH_CTRL_OSM_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TOM_CH_CTRL_Bits.OSM */
#define IFX_GTM_TOM_CH_CTRL_OSM_OFF (26u)

/** \brief  Length for Ifx_GTM_TOM_CH_CTRL_Bits.RST_CCU0 */
#define IFX_GTM_TOM_CH_CTRL_RST_CCU0_LEN (1u)

/** \brief  Mask for Ifx_GTM_TOM_CH_CTRL_Bits.RST_CCU0 */
#define IFX_GTM_TOM_CH_CTRL_RST_CCU0_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TOM_CH_CTRL_Bits.RST_CCU0 */
#define IFX_GTM_TOM_CH_CTRL_RST_CCU0_OFF (20u)

/** \brief  Length for Ifx_GTM_TOM_CH_CTRL_Bits.SL */
#define IFX_GTM_TOM_CH_CTRL_SL_LEN (1u)

/** \brief  Mask for Ifx_GTM_TOM_CH_CTRL_Bits.SL */
#define IFX_GTM_TOM_CH_CTRL_SL_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TOM_CH_CTRL_Bits.SL */
#define IFX_GTM_TOM_CH_CTRL_SL_OFF (11u)

/** \brief  Length for Ifx_GTM_TOM_CH_CTRL_Bits.SPEM */
#define IFX_GTM_TOM_CH_CTRL_SPEM_LEN (1u)

/** \brief  Mask for Ifx_GTM_TOM_CH_CTRL_Bits.SPEM */
#define IFX_GTM_TOM_CH_CTRL_SPEM_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TOM_CH_CTRL_Bits.SPEM */
#define IFX_GTM_TOM_CH_CTRL_SPEM_OFF (28u)

/** \brief  Length for Ifx_GTM_TOM_CH_CTRL_Bits.TRIGOUT */
#define IFX_GTM_TOM_CH_CTRL_TRIGOUT_LEN (1u)

/** \brief  Mask for Ifx_GTM_TOM_CH_CTRL_Bits.TRIGOUT */
#define IFX_GTM_TOM_CH_CTRL_TRIGOUT_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TOM_CH_CTRL_Bits.TRIGOUT */
#define IFX_GTM_TOM_CH_CTRL_TRIGOUT_OFF (24u)

/** \brief  Length for Ifx_GTM_TOM_CH_IRQ_EN_Bits.CCU0TC_IRQ_EN */
#define IFX_GTM_TOM_CH_IRQ_EN_CCU0TC_IRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_TOM_CH_IRQ_EN_Bits.CCU0TC_IRQ_EN */
#define IFX_GTM_TOM_CH_IRQ_EN_CCU0TC_IRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TOM_CH_IRQ_EN_Bits.CCU0TC_IRQ_EN */
#define IFX_GTM_TOM_CH_IRQ_EN_CCU0TC_IRQ_EN_OFF (0u)

/** \brief  Length for Ifx_GTM_TOM_CH_IRQ_EN_Bits.CCU1TC_IRQ_EN */
#define IFX_GTM_TOM_CH_IRQ_EN_CCU1TC_IRQ_EN_LEN (1u)

/** \brief  Mask for Ifx_GTM_TOM_CH_IRQ_EN_Bits.CCU1TC_IRQ_EN */
#define IFX_GTM_TOM_CH_IRQ_EN_CCU1TC_IRQ_EN_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TOM_CH_IRQ_EN_Bits.CCU1TC_IRQ_EN */
#define IFX_GTM_TOM_CH_IRQ_EN_CCU1TC_IRQ_EN_OFF (1u)

/** \brief  Length for Ifx_GTM_TOM_CH_IRQ_FORCINT_Bits.TRG_CCU0TC0 */
#define IFX_GTM_TOM_CH_IRQ_FORCINT_TRG_CCU0TC0_LEN (1u)

/** \brief  Mask for Ifx_GTM_TOM_CH_IRQ_FORCINT_Bits.TRG_CCU0TC0 */
#define IFX_GTM_TOM_CH_IRQ_FORCINT_TRG_CCU0TC0_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TOM_CH_IRQ_FORCINT_Bits.TRG_CCU0TC0 */
#define IFX_GTM_TOM_CH_IRQ_FORCINT_TRG_CCU0TC0_OFF (0u)

/** \brief  Length for Ifx_GTM_TOM_CH_IRQ_FORCINT_Bits.TRG_CCU1TC0 */
#define IFX_GTM_TOM_CH_IRQ_FORCINT_TRG_CCU1TC0_LEN (1u)

/** \brief  Mask for Ifx_GTM_TOM_CH_IRQ_FORCINT_Bits.TRG_CCU1TC0 */
#define IFX_GTM_TOM_CH_IRQ_FORCINT_TRG_CCU1TC0_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TOM_CH_IRQ_FORCINT_Bits.TRG_CCU1TC0 */
#define IFX_GTM_TOM_CH_IRQ_FORCINT_TRG_CCU1TC0_OFF (1u)

/** \brief  Length for Ifx_GTM_TOM_CH_IRQ_MODE_Bits.IRQ_MODE */
#define IFX_GTM_TOM_CH_IRQ_MODE_IRQ_MODE_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_CH_IRQ_MODE_Bits.IRQ_MODE */
#define IFX_GTM_TOM_CH_IRQ_MODE_IRQ_MODE_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_CH_IRQ_MODE_Bits.IRQ_MODE */
#define IFX_GTM_TOM_CH_IRQ_MODE_IRQ_MODE_OFF (0u)

/** \brief  Length for Ifx_GTM_TOM_CH_IRQ_NOTIFY_Bits.CCU0TC */
#define IFX_GTM_TOM_CH_IRQ_NOTIFY_CCU0TC_LEN (1u)

/** \brief  Mask for Ifx_GTM_TOM_CH_IRQ_NOTIFY_Bits.CCU0TC */
#define IFX_GTM_TOM_CH_IRQ_NOTIFY_CCU0TC_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TOM_CH_IRQ_NOTIFY_Bits.CCU0TC */
#define IFX_GTM_TOM_CH_IRQ_NOTIFY_CCU0TC_OFF (0u)

/** \brief  Length for Ifx_GTM_TOM_CH_IRQ_NOTIFY_Bits.CCU1TC */
#define IFX_GTM_TOM_CH_IRQ_NOTIFY_CCU1TC_LEN (1u)

/** \brief  Mask for Ifx_GTM_TOM_CH_IRQ_NOTIFY_Bits.CCU1TC */
#define IFX_GTM_TOM_CH_IRQ_NOTIFY_CCU1TC_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TOM_CH_IRQ_NOTIFY_Bits.CCU1TC */
#define IFX_GTM_TOM_CH_IRQ_NOTIFY_CCU1TC_OFF (1u)

/** \brief  Length for Ifx_GTM_TOM_CH_SR0_Bits.SR0 */
#define IFX_GTM_TOM_CH_SR0_SR0_LEN (16u)

/** \brief  Mask for Ifx_GTM_TOM_CH_SR0_Bits.SR0 */
#define IFX_GTM_TOM_CH_SR0_SR0_MSK (0xffffu)

/** \brief  Offset for Ifx_GTM_TOM_CH_SR0_Bits.SR0 */
#define IFX_GTM_TOM_CH_SR0_SR0_OFF (0u)

/** \brief  Length for Ifx_GTM_TOM_CH_SR1_Bits.SR1 */
#define IFX_GTM_TOM_CH_SR1_SR1_LEN (16u)

/** \brief  Mask for Ifx_GTM_TOM_CH_SR1_Bits.SR1 */
#define IFX_GTM_TOM_CH_SR1_SR1_MSK (0xffffu)

/** \brief  Offset for Ifx_GTM_TOM_CH_SR1_Bits.SR1 */
#define IFX_GTM_TOM_CH_SR1_SR1_OFF (0u)

/** \brief  Length for Ifx_GTM_TOM_CH_STAT_Bits.OL */
#define IFX_GTM_TOM_CH_STAT_OL_LEN (1u)

/** \brief  Mask for Ifx_GTM_TOM_CH_STAT_Bits.OL */
#define IFX_GTM_TOM_CH_STAT_OL_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TOM_CH_STAT_Bits.OL */
#define IFX_GTM_TOM_CH_STAT_OL_OFF (0u)

/** \brief  Length for Ifx_GTM_TOM_TGC0_ACT_TB_Bits.ACT_TB */
#define IFX_GTM_TOM_TGC0_ACT_TB_ACT_TB_LEN (24u)

/** \brief  Mask for Ifx_GTM_TOM_TGC0_ACT_TB_Bits.ACT_TB */
#define IFX_GTM_TOM_TGC0_ACT_TB_ACT_TB_MSK (0xffffffu)

/** \brief  Offset for Ifx_GTM_TOM_TGC0_ACT_TB_Bits.ACT_TB */
#define IFX_GTM_TOM_TGC0_ACT_TB_ACT_TB_OFF (0u)

/** \brief  Length for Ifx_GTM_TOM_TGC0_ACT_TB_Bits.TB_TRIG */
#define IFX_GTM_TOM_TGC0_ACT_TB_TB_TRIG_LEN (1u)

/** \brief  Mask for Ifx_GTM_TOM_TGC0_ACT_TB_Bits.TB_TRIG */
#define IFX_GTM_TOM_TGC0_ACT_TB_TB_TRIG_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TOM_TGC0_ACT_TB_Bits.TB_TRIG */
#define IFX_GTM_TOM_TGC0_ACT_TB_TB_TRIG_OFF (24u)

/** \brief  Length for Ifx_GTM_TOM_TGC0_ACT_TB_Bits.TBU_SEL */
#define IFX_GTM_TOM_TGC0_ACT_TB_TBU_SEL_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC0_ACT_TB_Bits.TBU_SEL */
#define IFX_GTM_TOM_TGC0_ACT_TB_TBU_SEL_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC0_ACT_TB_Bits.TBU_SEL */
#define IFX_GTM_TOM_TGC0_ACT_TB_TBU_SEL_OFF (25u)

/** \brief  Length for Ifx_GTM_TOM_TGC0_ENDIS_CTRL_Bits.ENDIS_CTRL0 */
#define IFX_GTM_TOM_TGC0_ENDIS_CTRL_ENDIS_CTRL0_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC0_ENDIS_CTRL_Bits.ENDIS_CTRL0 */
#define IFX_GTM_TOM_TGC0_ENDIS_CTRL_ENDIS_CTRL0_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC0_ENDIS_CTRL_Bits.ENDIS_CTRL0 */
#define IFX_GTM_TOM_TGC0_ENDIS_CTRL_ENDIS_CTRL0_OFF (0u)

/** \brief  Length for Ifx_GTM_TOM_TGC0_ENDIS_CTRL_Bits.ENDIS_CTRL1 */
#define IFX_GTM_TOM_TGC0_ENDIS_CTRL_ENDIS_CTRL1_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC0_ENDIS_CTRL_Bits.ENDIS_CTRL1 */
#define IFX_GTM_TOM_TGC0_ENDIS_CTRL_ENDIS_CTRL1_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC0_ENDIS_CTRL_Bits.ENDIS_CTRL1 */
#define IFX_GTM_TOM_TGC0_ENDIS_CTRL_ENDIS_CTRL1_OFF (2u)

/** \brief  Length for Ifx_GTM_TOM_TGC0_ENDIS_CTRL_Bits.ENDIS_CTRL2 */
#define IFX_GTM_TOM_TGC0_ENDIS_CTRL_ENDIS_CTRL2_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC0_ENDIS_CTRL_Bits.ENDIS_CTRL2 */
#define IFX_GTM_TOM_TGC0_ENDIS_CTRL_ENDIS_CTRL2_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC0_ENDIS_CTRL_Bits.ENDIS_CTRL2 */
#define IFX_GTM_TOM_TGC0_ENDIS_CTRL_ENDIS_CTRL2_OFF (4u)

/** \brief  Length for Ifx_GTM_TOM_TGC0_ENDIS_CTRL_Bits.ENDIS_CTRL3 */
#define IFX_GTM_TOM_TGC0_ENDIS_CTRL_ENDIS_CTRL3_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC0_ENDIS_CTRL_Bits.ENDIS_CTRL3 */
#define IFX_GTM_TOM_TGC0_ENDIS_CTRL_ENDIS_CTRL3_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC0_ENDIS_CTRL_Bits.ENDIS_CTRL3 */
#define IFX_GTM_TOM_TGC0_ENDIS_CTRL_ENDIS_CTRL3_OFF (6u)

/** \brief  Length for Ifx_GTM_TOM_TGC0_ENDIS_CTRL_Bits.ENDIS_CTRL4 */
#define IFX_GTM_TOM_TGC0_ENDIS_CTRL_ENDIS_CTRL4_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC0_ENDIS_CTRL_Bits.ENDIS_CTRL4 */
#define IFX_GTM_TOM_TGC0_ENDIS_CTRL_ENDIS_CTRL4_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC0_ENDIS_CTRL_Bits.ENDIS_CTRL4 */
#define IFX_GTM_TOM_TGC0_ENDIS_CTRL_ENDIS_CTRL4_OFF (8u)

/** \brief  Length for Ifx_GTM_TOM_TGC0_ENDIS_CTRL_Bits.ENDIS_CTRL5 */
#define IFX_GTM_TOM_TGC0_ENDIS_CTRL_ENDIS_CTRL5_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC0_ENDIS_CTRL_Bits.ENDIS_CTRL5 */
#define IFX_GTM_TOM_TGC0_ENDIS_CTRL_ENDIS_CTRL5_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC0_ENDIS_CTRL_Bits.ENDIS_CTRL5 */
#define IFX_GTM_TOM_TGC0_ENDIS_CTRL_ENDIS_CTRL5_OFF (10u)

/** \brief  Length for Ifx_GTM_TOM_TGC0_ENDIS_CTRL_Bits.ENDIS_CTRL6 */
#define IFX_GTM_TOM_TGC0_ENDIS_CTRL_ENDIS_CTRL6_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC0_ENDIS_CTRL_Bits.ENDIS_CTRL6 */
#define IFX_GTM_TOM_TGC0_ENDIS_CTRL_ENDIS_CTRL6_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC0_ENDIS_CTRL_Bits.ENDIS_CTRL6 */
#define IFX_GTM_TOM_TGC0_ENDIS_CTRL_ENDIS_CTRL6_OFF (12u)

/** \brief  Length for Ifx_GTM_TOM_TGC0_ENDIS_CTRL_Bits.ENDIS_CTRL7 */
#define IFX_GTM_TOM_TGC0_ENDIS_CTRL_ENDIS_CTRL7_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC0_ENDIS_CTRL_Bits.ENDIS_CTRL7 */
#define IFX_GTM_TOM_TGC0_ENDIS_CTRL_ENDIS_CTRL7_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC0_ENDIS_CTRL_Bits.ENDIS_CTRL7 */
#define IFX_GTM_TOM_TGC0_ENDIS_CTRL_ENDIS_CTRL7_OFF (14u)

/** \brief  Length for Ifx_GTM_TOM_TGC0_ENDIS_STAT_Bits.ENDIS_STAT0 */
#define IFX_GTM_TOM_TGC0_ENDIS_STAT_ENDIS_STAT0_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC0_ENDIS_STAT_Bits.ENDIS_STAT0 */
#define IFX_GTM_TOM_TGC0_ENDIS_STAT_ENDIS_STAT0_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC0_ENDIS_STAT_Bits.ENDIS_STAT0 */
#define IFX_GTM_TOM_TGC0_ENDIS_STAT_ENDIS_STAT0_OFF (0u)

/** \brief  Length for Ifx_GTM_TOM_TGC0_ENDIS_STAT_Bits.ENDIS_STAT1 */
#define IFX_GTM_TOM_TGC0_ENDIS_STAT_ENDIS_STAT1_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC0_ENDIS_STAT_Bits.ENDIS_STAT1 */
#define IFX_GTM_TOM_TGC0_ENDIS_STAT_ENDIS_STAT1_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC0_ENDIS_STAT_Bits.ENDIS_STAT1 */
#define IFX_GTM_TOM_TGC0_ENDIS_STAT_ENDIS_STAT1_OFF (2u)

/** \brief  Length for Ifx_GTM_TOM_TGC0_ENDIS_STAT_Bits.ENDIS_STAT2 */
#define IFX_GTM_TOM_TGC0_ENDIS_STAT_ENDIS_STAT2_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC0_ENDIS_STAT_Bits.ENDIS_STAT2 */
#define IFX_GTM_TOM_TGC0_ENDIS_STAT_ENDIS_STAT2_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC0_ENDIS_STAT_Bits.ENDIS_STAT2 */
#define IFX_GTM_TOM_TGC0_ENDIS_STAT_ENDIS_STAT2_OFF (4u)

/** \brief  Length for Ifx_GTM_TOM_TGC0_ENDIS_STAT_Bits.ENDIS_STAT3 */
#define IFX_GTM_TOM_TGC0_ENDIS_STAT_ENDIS_STAT3_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC0_ENDIS_STAT_Bits.ENDIS_STAT3 */
#define IFX_GTM_TOM_TGC0_ENDIS_STAT_ENDIS_STAT3_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC0_ENDIS_STAT_Bits.ENDIS_STAT3 */
#define IFX_GTM_TOM_TGC0_ENDIS_STAT_ENDIS_STAT3_OFF (6u)

/** \brief  Length for Ifx_GTM_TOM_TGC0_ENDIS_STAT_Bits.ENDIS_STAT4 */
#define IFX_GTM_TOM_TGC0_ENDIS_STAT_ENDIS_STAT4_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC0_ENDIS_STAT_Bits.ENDIS_STAT4 */
#define IFX_GTM_TOM_TGC0_ENDIS_STAT_ENDIS_STAT4_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC0_ENDIS_STAT_Bits.ENDIS_STAT4 */
#define IFX_GTM_TOM_TGC0_ENDIS_STAT_ENDIS_STAT4_OFF (8u)

/** \brief  Length for Ifx_GTM_TOM_TGC0_ENDIS_STAT_Bits.ENDIS_STAT5 */
#define IFX_GTM_TOM_TGC0_ENDIS_STAT_ENDIS_STAT5_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC0_ENDIS_STAT_Bits.ENDIS_STAT5 */
#define IFX_GTM_TOM_TGC0_ENDIS_STAT_ENDIS_STAT5_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC0_ENDIS_STAT_Bits.ENDIS_STAT5 */
#define IFX_GTM_TOM_TGC0_ENDIS_STAT_ENDIS_STAT5_OFF (10u)

/** \brief  Length for Ifx_GTM_TOM_TGC0_ENDIS_STAT_Bits.ENDIS_STAT6 */
#define IFX_GTM_TOM_TGC0_ENDIS_STAT_ENDIS_STAT6_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC0_ENDIS_STAT_Bits.ENDIS_STAT6 */
#define IFX_GTM_TOM_TGC0_ENDIS_STAT_ENDIS_STAT6_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC0_ENDIS_STAT_Bits.ENDIS_STAT6 */
#define IFX_GTM_TOM_TGC0_ENDIS_STAT_ENDIS_STAT6_OFF (12u)

/** \brief  Length for Ifx_GTM_TOM_TGC0_ENDIS_STAT_Bits.ENDIS_STAT7 */
#define IFX_GTM_TOM_TGC0_ENDIS_STAT_ENDIS_STAT7_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC0_ENDIS_STAT_Bits.ENDIS_STAT7 */
#define IFX_GTM_TOM_TGC0_ENDIS_STAT_ENDIS_STAT7_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC0_ENDIS_STAT_Bits.ENDIS_STAT7 */
#define IFX_GTM_TOM_TGC0_ENDIS_STAT_ENDIS_STAT7_OFF (14u)

/** \brief  Length for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.FUPD_CTRL0 */
#define IFX_GTM_TOM_TGC0_FUPD_CTRL_FUPD_CTRL0_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.FUPD_CTRL0 */
#define IFX_GTM_TOM_TGC0_FUPD_CTRL_FUPD_CTRL0_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.FUPD_CTRL0 */
#define IFX_GTM_TOM_TGC0_FUPD_CTRL_FUPD_CTRL0_OFF (0u)

/** \brief  Length for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.FUPD_CTRL1 */
#define IFX_GTM_TOM_TGC0_FUPD_CTRL_FUPD_CTRL1_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.FUPD_CTRL1 */
#define IFX_GTM_TOM_TGC0_FUPD_CTRL_FUPD_CTRL1_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.FUPD_CTRL1 */
#define IFX_GTM_TOM_TGC0_FUPD_CTRL_FUPD_CTRL1_OFF (2u)

/** \brief  Length for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.FUPD_CTRL2 */
#define IFX_GTM_TOM_TGC0_FUPD_CTRL_FUPD_CTRL2_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.FUPD_CTRL2 */
#define IFX_GTM_TOM_TGC0_FUPD_CTRL_FUPD_CTRL2_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.FUPD_CTRL2 */
#define IFX_GTM_TOM_TGC0_FUPD_CTRL_FUPD_CTRL2_OFF (4u)

/** \brief  Length for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.FUPD_CTRL3 */
#define IFX_GTM_TOM_TGC0_FUPD_CTRL_FUPD_CTRL3_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.FUPD_CTRL3 */
#define IFX_GTM_TOM_TGC0_FUPD_CTRL_FUPD_CTRL3_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.FUPD_CTRL3 */
#define IFX_GTM_TOM_TGC0_FUPD_CTRL_FUPD_CTRL3_OFF (6u)

/** \brief  Length for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.FUPD_CTRL4 */
#define IFX_GTM_TOM_TGC0_FUPD_CTRL_FUPD_CTRL4_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.FUPD_CTRL4 */
#define IFX_GTM_TOM_TGC0_FUPD_CTRL_FUPD_CTRL4_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.FUPD_CTRL4 */
#define IFX_GTM_TOM_TGC0_FUPD_CTRL_FUPD_CTRL4_OFF (8u)

/** \brief  Length for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.FUPD_CTRL5 */
#define IFX_GTM_TOM_TGC0_FUPD_CTRL_FUPD_CTRL5_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.FUPD_CTRL5 */
#define IFX_GTM_TOM_TGC0_FUPD_CTRL_FUPD_CTRL5_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.FUPD_CTRL5 */
#define IFX_GTM_TOM_TGC0_FUPD_CTRL_FUPD_CTRL5_OFF (10u)

/** \brief  Length for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.FUPD_CTRL6 */
#define IFX_GTM_TOM_TGC0_FUPD_CTRL_FUPD_CTRL6_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.FUPD_CTRL6 */
#define IFX_GTM_TOM_TGC0_FUPD_CTRL_FUPD_CTRL6_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.FUPD_CTRL6 */
#define IFX_GTM_TOM_TGC0_FUPD_CTRL_FUPD_CTRL6_OFF (12u)

/** \brief  Length for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.FUPD_CTRL7 */
#define IFX_GTM_TOM_TGC0_FUPD_CTRL_FUPD_CTRL7_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.FUPD_CTRL7 */
#define IFX_GTM_TOM_TGC0_FUPD_CTRL_FUPD_CTRL7_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.FUPD_CTRL7 */
#define IFX_GTM_TOM_TGC0_FUPD_CTRL_FUPD_CTRL7_OFF (14u)

/** \brief  Length for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.RSTCN0_CH0 */
#define IFX_GTM_TOM_TGC0_FUPD_CTRL_RSTCN0_CH0_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.RSTCN0_CH0 */
#define IFX_GTM_TOM_TGC0_FUPD_CTRL_RSTCN0_CH0_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.RSTCN0_CH0 */
#define IFX_GTM_TOM_TGC0_FUPD_CTRL_RSTCN0_CH0_OFF (16u)

/** \brief  Length for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.RSTCN0_CH1 */
#define IFX_GTM_TOM_TGC0_FUPD_CTRL_RSTCN0_CH1_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.RSTCN0_CH1 */
#define IFX_GTM_TOM_TGC0_FUPD_CTRL_RSTCN0_CH1_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.RSTCN0_CH1 */
#define IFX_GTM_TOM_TGC0_FUPD_CTRL_RSTCN0_CH1_OFF (18u)

/** \brief  Length for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.RSTCN0_CH2 */
#define IFX_GTM_TOM_TGC0_FUPD_CTRL_RSTCN0_CH2_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.RSTCN0_CH2 */
#define IFX_GTM_TOM_TGC0_FUPD_CTRL_RSTCN0_CH2_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.RSTCN0_CH2 */
#define IFX_GTM_TOM_TGC0_FUPD_CTRL_RSTCN0_CH2_OFF (20u)

/** \brief  Length for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.RSTCN0_CH3 */
#define IFX_GTM_TOM_TGC0_FUPD_CTRL_RSTCN0_CH3_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.RSTCN0_CH3 */
#define IFX_GTM_TOM_TGC0_FUPD_CTRL_RSTCN0_CH3_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.RSTCN0_CH3 */
#define IFX_GTM_TOM_TGC0_FUPD_CTRL_RSTCN0_CH3_OFF (22u)

/** \brief  Length for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.RSTCN0_CH4 */
#define IFX_GTM_TOM_TGC0_FUPD_CTRL_RSTCN0_CH4_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.RSTCN0_CH4 */
#define IFX_GTM_TOM_TGC0_FUPD_CTRL_RSTCN0_CH4_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.RSTCN0_CH4 */
#define IFX_GTM_TOM_TGC0_FUPD_CTRL_RSTCN0_CH4_OFF (24u)

/** \brief  Length for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.RSTCN0_CH5 */
#define IFX_GTM_TOM_TGC0_FUPD_CTRL_RSTCN0_CH5_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.RSTCN0_CH5 */
#define IFX_GTM_TOM_TGC0_FUPD_CTRL_RSTCN0_CH5_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.RSTCN0_CH5 */
#define IFX_GTM_TOM_TGC0_FUPD_CTRL_RSTCN0_CH5_OFF (26u)

/** \brief  Length for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.RSTCN0_CH6 */
#define IFX_GTM_TOM_TGC0_FUPD_CTRL_RSTCN0_CH6_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.RSTCN0_CH6 */
#define IFX_GTM_TOM_TGC0_FUPD_CTRL_RSTCN0_CH6_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.RSTCN0_CH6 */
#define IFX_GTM_TOM_TGC0_FUPD_CTRL_RSTCN0_CH6_OFF (28u)

/** \brief  Length for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.RSTCN0_CH7 */
#define IFX_GTM_TOM_TGC0_FUPD_CTRL_RSTCN0_CH7_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.RSTCN0_CH7 */
#define IFX_GTM_TOM_TGC0_FUPD_CTRL_RSTCN0_CH7_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC0_FUPD_CTRL_Bits.RSTCN0_CH7 */
#define IFX_GTM_TOM_TGC0_FUPD_CTRL_RSTCN0_CH7_OFF (30u)

/** \brief  Length for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.HOST_TRIG */
#define IFX_GTM_TOM_TGC0_GLB_CTRL_HOST_TRIG_LEN (1u)

/** \brief  Mask for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.HOST_TRIG */
#define IFX_GTM_TOM_TGC0_GLB_CTRL_HOST_TRIG_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.HOST_TRIG */
#define IFX_GTM_TOM_TGC0_GLB_CTRL_HOST_TRIG_OFF (0u)

/** \brief  Length for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.RST_CH0 */
#define IFX_GTM_TOM_TGC0_GLB_CTRL_RST_CH0_LEN (1u)

/** \brief  Mask for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.RST_CH0 */
#define IFX_GTM_TOM_TGC0_GLB_CTRL_RST_CH0_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.RST_CH0 */
#define IFX_GTM_TOM_TGC0_GLB_CTRL_RST_CH0_OFF (8u)

/** \brief  Length for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.RST_CH1 */
#define IFX_GTM_TOM_TGC0_GLB_CTRL_RST_CH1_LEN (1u)

/** \brief  Mask for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.RST_CH1 */
#define IFX_GTM_TOM_TGC0_GLB_CTRL_RST_CH1_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.RST_CH1 */
#define IFX_GTM_TOM_TGC0_GLB_CTRL_RST_CH1_OFF (9u)

/** \brief  Length for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.RST_CH2 */
#define IFX_GTM_TOM_TGC0_GLB_CTRL_RST_CH2_LEN (1u)

/** \brief  Mask for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.RST_CH2 */
#define IFX_GTM_TOM_TGC0_GLB_CTRL_RST_CH2_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.RST_CH2 */
#define IFX_GTM_TOM_TGC0_GLB_CTRL_RST_CH2_OFF (10u)

/** \brief  Length for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.RST_CH3 */
#define IFX_GTM_TOM_TGC0_GLB_CTRL_RST_CH3_LEN (1u)

/** \brief  Mask for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.RST_CH3 */
#define IFX_GTM_TOM_TGC0_GLB_CTRL_RST_CH3_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.RST_CH3 */
#define IFX_GTM_TOM_TGC0_GLB_CTRL_RST_CH3_OFF (11u)

/** \brief  Length for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.RST_CH4 */
#define IFX_GTM_TOM_TGC0_GLB_CTRL_RST_CH4_LEN (1u)

/** \brief  Mask for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.RST_CH4 */
#define IFX_GTM_TOM_TGC0_GLB_CTRL_RST_CH4_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.RST_CH4 */
#define IFX_GTM_TOM_TGC0_GLB_CTRL_RST_CH4_OFF (12u)

/** \brief  Length for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.RST_CH5 */
#define IFX_GTM_TOM_TGC0_GLB_CTRL_RST_CH5_LEN (1u)

/** \brief  Mask for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.RST_CH5 */
#define IFX_GTM_TOM_TGC0_GLB_CTRL_RST_CH5_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.RST_CH5 */
#define IFX_GTM_TOM_TGC0_GLB_CTRL_RST_CH5_OFF (13u)

/** \brief  Length for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.RST_CH6 */
#define IFX_GTM_TOM_TGC0_GLB_CTRL_RST_CH6_LEN (1u)

/** \brief  Mask for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.RST_CH6 */
#define IFX_GTM_TOM_TGC0_GLB_CTRL_RST_CH6_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.RST_CH6 */
#define IFX_GTM_TOM_TGC0_GLB_CTRL_RST_CH6_OFF (14u)

/** \brief  Length for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.RST_CH7 */
#define IFX_GTM_TOM_TGC0_GLB_CTRL_RST_CH7_LEN (1u)

/** \brief  Mask for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.RST_CH7 */
#define IFX_GTM_TOM_TGC0_GLB_CTRL_RST_CH7_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.RST_CH7 */
#define IFX_GTM_TOM_TGC0_GLB_CTRL_RST_CH7_OFF (15u)

/** \brief  Length for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.UPEN_CTRL0 */
#define IFX_GTM_TOM_TGC0_GLB_CTRL_UPEN_CTRL0_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.UPEN_CTRL0 */
#define IFX_GTM_TOM_TGC0_GLB_CTRL_UPEN_CTRL0_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.UPEN_CTRL0 */
#define IFX_GTM_TOM_TGC0_GLB_CTRL_UPEN_CTRL0_OFF (16u)

/** \brief  Length for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.UPEN_CTRL1 */
#define IFX_GTM_TOM_TGC0_GLB_CTRL_UPEN_CTRL1_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.UPEN_CTRL1 */
#define IFX_GTM_TOM_TGC0_GLB_CTRL_UPEN_CTRL1_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.UPEN_CTRL1 */
#define IFX_GTM_TOM_TGC0_GLB_CTRL_UPEN_CTRL1_OFF (18u)

/** \brief  Length for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.UPEN_CTRL2 */
#define IFX_GTM_TOM_TGC0_GLB_CTRL_UPEN_CTRL2_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.UPEN_CTRL2 */
#define IFX_GTM_TOM_TGC0_GLB_CTRL_UPEN_CTRL2_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.UPEN_CTRL2 */
#define IFX_GTM_TOM_TGC0_GLB_CTRL_UPEN_CTRL2_OFF (20u)

/** \brief  Length for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.UPEN_CTRL3 */
#define IFX_GTM_TOM_TGC0_GLB_CTRL_UPEN_CTRL3_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.UPEN_CTRL3 */
#define IFX_GTM_TOM_TGC0_GLB_CTRL_UPEN_CTRL3_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.UPEN_CTRL3 */
#define IFX_GTM_TOM_TGC0_GLB_CTRL_UPEN_CTRL3_OFF (22u)

/** \brief  Length for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.UPEN_CTRL4 */
#define IFX_GTM_TOM_TGC0_GLB_CTRL_UPEN_CTRL4_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.UPEN_CTRL4 */
#define IFX_GTM_TOM_TGC0_GLB_CTRL_UPEN_CTRL4_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.UPEN_CTRL4 */
#define IFX_GTM_TOM_TGC0_GLB_CTRL_UPEN_CTRL4_OFF (24u)

/** \brief  Length for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.UPEN_CTRL5 */
#define IFX_GTM_TOM_TGC0_GLB_CTRL_UPEN_CTRL5_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.UPEN_CTRL5 */
#define IFX_GTM_TOM_TGC0_GLB_CTRL_UPEN_CTRL5_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.UPEN_CTRL5 */
#define IFX_GTM_TOM_TGC0_GLB_CTRL_UPEN_CTRL5_OFF (26u)

/** \brief  Length for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.UPEN_CTRL6 */
#define IFX_GTM_TOM_TGC0_GLB_CTRL_UPEN_CTRL6_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.UPEN_CTRL6 */
#define IFX_GTM_TOM_TGC0_GLB_CTRL_UPEN_CTRL6_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.UPEN_CTRL6 */
#define IFX_GTM_TOM_TGC0_GLB_CTRL_UPEN_CTRL6_OFF (28u)

/** \brief  Length for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.UPEN_CTRL7 */
#define IFX_GTM_TOM_TGC0_GLB_CTRL_UPEN_CTRL7_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.UPEN_CTRL7 */
#define IFX_GTM_TOM_TGC0_GLB_CTRL_UPEN_CTRL7_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC0_GLB_CTRL_Bits.UPEN_CTRL7 */
#define IFX_GTM_TOM_TGC0_GLB_CTRL_UPEN_CTRL7_OFF (30u)

/** \brief  Length for Ifx_GTM_TOM_TGC0_INT_TRIG_Bits.INT_TRIG0 */
#define IFX_GTM_TOM_TGC0_INT_TRIG_INT_TRIG0_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC0_INT_TRIG_Bits.INT_TRIG0 */
#define IFX_GTM_TOM_TGC0_INT_TRIG_INT_TRIG0_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC0_INT_TRIG_Bits.INT_TRIG0 */
#define IFX_GTM_TOM_TGC0_INT_TRIG_INT_TRIG0_OFF (0u)

/** \brief  Length for Ifx_GTM_TOM_TGC0_INT_TRIG_Bits.INT_TRIG1 */
#define IFX_GTM_TOM_TGC0_INT_TRIG_INT_TRIG1_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC0_INT_TRIG_Bits.INT_TRIG1 */
#define IFX_GTM_TOM_TGC0_INT_TRIG_INT_TRIG1_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC0_INT_TRIG_Bits.INT_TRIG1 */
#define IFX_GTM_TOM_TGC0_INT_TRIG_INT_TRIG1_OFF (2u)

/** \brief  Length for Ifx_GTM_TOM_TGC0_INT_TRIG_Bits.INT_TRIG2 */
#define IFX_GTM_TOM_TGC0_INT_TRIG_INT_TRIG2_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC0_INT_TRIG_Bits.INT_TRIG2 */
#define IFX_GTM_TOM_TGC0_INT_TRIG_INT_TRIG2_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC0_INT_TRIG_Bits.INT_TRIG2 */
#define IFX_GTM_TOM_TGC0_INT_TRIG_INT_TRIG2_OFF (4u)

/** \brief  Length for Ifx_GTM_TOM_TGC0_INT_TRIG_Bits.INT_TRIG3 */
#define IFX_GTM_TOM_TGC0_INT_TRIG_INT_TRIG3_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC0_INT_TRIG_Bits.INT_TRIG3 */
#define IFX_GTM_TOM_TGC0_INT_TRIG_INT_TRIG3_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC0_INT_TRIG_Bits.INT_TRIG3 */
#define IFX_GTM_TOM_TGC0_INT_TRIG_INT_TRIG3_OFF (6u)

/** \brief  Length for Ifx_GTM_TOM_TGC0_INT_TRIG_Bits.INT_TRIG4 */
#define IFX_GTM_TOM_TGC0_INT_TRIG_INT_TRIG4_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC0_INT_TRIG_Bits.INT_TRIG4 */
#define IFX_GTM_TOM_TGC0_INT_TRIG_INT_TRIG4_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC0_INT_TRIG_Bits.INT_TRIG4 */
#define IFX_GTM_TOM_TGC0_INT_TRIG_INT_TRIG4_OFF (8u)

/** \brief  Length for Ifx_GTM_TOM_TGC0_INT_TRIG_Bits.INT_TRIG5 */
#define IFX_GTM_TOM_TGC0_INT_TRIG_INT_TRIG5_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC0_INT_TRIG_Bits.INT_TRIG5 */
#define IFX_GTM_TOM_TGC0_INT_TRIG_INT_TRIG5_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC0_INT_TRIG_Bits.INT_TRIG5 */
#define IFX_GTM_TOM_TGC0_INT_TRIG_INT_TRIG5_OFF (10u)

/** \brief  Length for Ifx_GTM_TOM_TGC0_INT_TRIG_Bits.INT_TRIG6 */
#define IFX_GTM_TOM_TGC0_INT_TRIG_INT_TRIG6_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC0_INT_TRIG_Bits.INT_TRIG6 */
#define IFX_GTM_TOM_TGC0_INT_TRIG_INT_TRIG6_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC0_INT_TRIG_Bits.INT_TRIG6 */
#define IFX_GTM_TOM_TGC0_INT_TRIG_INT_TRIG6_OFF (12u)

/** \brief  Length for Ifx_GTM_TOM_TGC0_INT_TRIG_Bits.INT_TRIG7 */
#define IFX_GTM_TOM_TGC0_INT_TRIG_INT_TRIG7_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC0_INT_TRIG_Bits.INT_TRIG7 */
#define IFX_GTM_TOM_TGC0_INT_TRIG_INT_TRIG7_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC0_INT_TRIG_Bits.INT_TRIG7 */
#define IFX_GTM_TOM_TGC0_INT_TRIG_INT_TRIG7_OFF (14u)

/** \brief  Length for Ifx_GTM_TOM_TGC0_OUTEN_CTRL_Bits.OUTEN_CTRL0 */
#define IFX_GTM_TOM_TGC0_OUTEN_CTRL_OUTEN_CTRL0_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC0_OUTEN_CTRL_Bits.OUTEN_CTRL0 */
#define IFX_GTM_TOM_TGC0_OUTEN_CTRL_OUTEN_CTRL0_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC0_OUTEN_CTRL_Bits.OUTEN_CTRL0 */
#define IFX_GTM_TOM_TGC0_OUTEN_CTRL_OUTEN_CTRL0_OFF (0u)

/** \brief  Length for Ifx_GTM_TOM_TGC0_OUTEN_CTRL_Bits.OUTEN_CTRL1 */
#define IFX_GTM_TOM_TGC0_OUTEN_CTRL_OUTEN_CTRL1_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC0_OUTEN_CTRL_Bits.OUTEN_CTRL1 */
#define IFX_GTM_TOM_TGC0_OUTEN_CTRL_OUTEN_CTRL1_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC0_OUTEN_CTRL_Bits.OUTEN_CTRL1 */
#define IFX_GTM_TOM_TGC0_OUTEN_CTRL_OUTEN_CTRL1_OFF (2u)

/** \brief  Length for Ifx_GTM_TOM_TGC0_OUTEN_CTRL_Bits.OUTEN_CTRL2 */
#define IFX_GTM_TOM_TGC0_OUTEN_CTRL_OUTEN_CTRL2_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC0_OUTEN_CTRL_Bits.OUTEN_CTRL2 */
#define IFX_GTM_TOM_TGC0_OUTEN_CTRL_OUTEN_CTRL2_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC0_OUTEN_CTRL_Bits.OUTEN_CTRL2 */
#define IFX_GTM_TOM_TGC0_OUTEN_CTRL_OUTEN_CTRL2_OFF (4u)

/** \brief  Length for Ifx_GTM_TOM_TGC0_OUTEN_CTRL_Bits.OUTEN_CTRL3 */
#define IFX_GTM_TOM_TGC0_OUTEN_CTRL_OUTEN_CTRL3_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC0_OUTEN_CTRL_Bits.OUTEN_CTRL3 */
#define IFX_GTM_TOM_TGC0_OUTEN_CTRL_OUTEN_CTRL3_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC0_OUTEN_CTRL_Bits.OUTEN_CTRL3 */
#define IFX_GTM_TOM_TGC0_OUTEN_CTRL_OUTEN_CTRL3_OFF (6u)

/** \brief  Length for Ifx_GTM_TOM_TGC0_OUTEN_CTRL_Bits.OUTEN_CTRL4 */
#define IFX_GTM_TOM_TGC0_OUTEN_CTRL_OUTEN_CTRL4_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC0_OUTEN_CTRL_Bits.OUTEN_CTRL4 */
#define IFX_GTM_TOM_TGC0_OUTEN_CTRL_OUTEN_CTRL4_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC0_OUTEN_CTRL_Bits.OUTEN_CTRL4 */
#define IFX_GTM_TOM_TGC0_OUTEN_CTRL_OUTEN_CTRL4_OFF (8u)

/** \brief  Length for Ifx_GTM_TOM_TGC0_OUTEN_CTRL_Bits.OUTEN_CTRL5 */
#define IFX_GTM_TOM_TGC0_OUTEN_CTRL_OUTEN_CTRL5_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC0_OUTEN_CTRL_Bits.OUTEN_CTRL5 */
#define IFX_GTM_TOM_TGC0_OUTEN_CTRL_OUTEN_CTRL5_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC0_OUTEN_CTRL_Bits.OUTEN_CTRL5 */
#define IFX_GTM_TOM_TGC0_OUTEN_CTRL_OUTEN_CTRL5_OFF (10u)

/** \brief  Length for Ifx_GTM_TOM_TGC0_OUTEN_CTRL_Bits.OUTEN_CTRL6 */
#define IFX_GTM_TOM_TGC0_OUTEN_CTRL_OUTEN_CTRL6_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC0_OUTEN_CTRL_Bits.OUTEN_CTRL6 */
#define IFX_GTM_TOM_TGC0_OUTEN_CTRL_OUTEN_CTRL6_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC0_OUTEN_CTRL_Bits.OUTEN_CTRL6 */
#define IFX_GTM_TOM_TGC0_OUTEN_CTRL_OUTEN_CTRL6_OFF (12u)

/** \brief  Length for Ifx_GTM_TOM_TGC0_OUTEN_CTRL_Bits.OUTEN_CTRL7 */
#define IFX_GTM_TOM_TGC0_OUTEN_CTRL_OUTEN_CTRL7_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC0_OUTEN_CTRL_Bits.OUTEN_CTRL7 */
#define IFX_GTM_TOM_TGC0_OUTEN_CTRL_OUTEN_CTRL7_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC0_OUTEN_CTRL_Bits.OUTEN_CTRL7 */
#define IFX_GTM_TOM_TGC0_OUTEN_CTRL_OUTEN_CTRL7_OFF (14u)

/** \brief  Length for Ifx_GTM_TOM_TGC0_OUTEN_STAT_Bits.OUTEN_STAT0 */
#define IFX_GTM_TOM_TGC0_OUTEN_STAT_OUTEN_STAT0_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC0_OUTEN_STAT_Bits.OUTEN_STAT0 */
#define IFX_GTM_TOM_TGC0_OUTEN_STAT_OUTEN_STAT0_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC0_OUTEN_STAT_Bits.OUTEN_STAT0 */
#define IFX_GTM_TOM_TGC0_OUTEN_STAT_OUTEN_STAT0_OFF (0u)

/** \brief  Length for Ifx_GTM_TOM_TGC0_OUTEN_STAT_Bits.OUTEN_STAT1 */
#define IFX_GTM_TOM_TGC0_OUTEN_STAT_OUTEN_STAT1_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC0_OUTEN_STAT_Bits.OUTEN_STAT1 */
#define IFX_GTM_TOM_TGC0_OUTEN_STAT_OUTEN_STAT1_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC0_OUTEN_STAT_Bits.OUTEN_STAT1 */
#define IFX_GTM_TOM_TGC0_OUTEN_STAT_OUTEN_STAT1_OFF (2u)

/** \brief  Length for Ifx_GTM_TOM_TGC0_OUTEN_STAT_Bits.OUTEN_STAT2 */
#define IFX_GTM_TOM_TGC0_OUTEN_STAT_OUTEN_STAT2_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC0_OUTEN_STAT_Bits.OUTEN_STAT2 */
#define IFX_GTM_TOM_TGC0_OUTEN_STAT_OUTEN_STAT2_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC0_OUTEN_STAT_Bits.OUTEN_STAT2 */
#define IFX_GTM_TOM_TGC0_OUTEN_STAT_OUTEN_STAT2_OFF (4u)

/** \brief  Length for Ifx_GTM_TOM_TGC0_OUTEN_STAT_Bits.OUTEN_STAT3 */
#define IFX_GTM_TOM_TGC0_OUTEN_STAT_OUTEN_STAT3_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC0_OUTEN_STAT_Bits.OUTEN_STAT3 */
#define IFX_GTM_TOM_TGC0_OUTEN_STAT_OUTEN_STAT3_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC0_OUTEN_STAT_Bits.OUTEN_STAT3 */
#define IFX_GTM_TOM_TGC0_OUTEN_STAT_OUTEN_STAT3_OFF (6u)

/** \brief  Length for Ifx_GTM_TOM_TGC0_OUTEN_STAT_Bits.OUTEN_STAT4 */
#define IFX_GTM_TOM_TGC0_OUTEN_STAT_OUTEN_STAT4_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC0_OUTEN_STAT_Bits.OUTEN_STAT4 */
#define IFX_GTM_TOM_TGC0_OUTEN_STAT_OUTEN_STAT4_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC0_OUTEN_STAT_Bits.OUTEN_STAT4 */
#define IFX_GTM_TOM_TGC0_OUTEN_STAT_OUTEN_STAT4_OFF (8u)

/** \brief  Length for Ifx_GTM_TOM_TGC0_OUTEN_STAT_Bits.OUTEN_STAT5 */
#define IFX_GTM_TOM_TGC0_OUTEN_STAT_OUTEN_STAT5_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC0_OUTEN_STAT_Bits.OUTEN_STAT5 */
#define IFX_GTM_TOM_TGC0_OUTEN_STAT_OUTEN_STAT5_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC0_OUTEN_STAT_Bits.OUTEN_STAT5 */
#define IFX_GTM_TOM_TGC0_OUTEN_STAT_OUTEN_STAT5_OFF (10u)

/** \brief  Length for Ifx_GTM_TOM_TGC0_OUTEN_STAT_Bits.OUTEN_STAT6 */
#define IFX_GTM_TOM_TGC0_OUTEN_STAT_OUTEN_STAT6_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC0_OUTEN_STAT_Bits.OUTEN_STAT6 */
#define IFX_GTM_TOM_TGC0_OUTEN_STAT_OUTEN_STAT6_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC0_OUTEN_STAT_Bits.OUTEN_STAT6 */
#define IFX_GTM_TOM_TGC0_OUTEN_STAT_OUTEN_STAT6_OFF (12u)

/** \brief  Length for Ifx_GTM_TOM_TGC0_OUTEN_STAT_Bits.OUTEN_STAT7 */
#define IFX_GTM_TOM_TGC0_OUTEN_STAT_OUTEN_STAT7_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC0_OUTEN_STAT_Bits.OUTEN_STAT7 */
#define IFX_GTM_TOM_TGC0_OUTEN_STAT_OUTEN_STAT7_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC0_OUTEN_STAT_Bits.OUTEN_STAT7 */
#define IFX_GTM_TOM_TGC0_OUTEN_STAT_OUTEN_STAT7_OFF (14u)

/** \brief  Length for Ifx_GTM_TOM_TGC1_ACT_TB_Bits.ACT_TB */
#define IFX_GTM_TOM_TGC1_ACT_TB_ACT_TB_LEN (24u)

/** \brief  Mask for Ifx_GTM_TOM_TGC1_ACT_TB_Bits.ACT_TB */
#define IFX_GTM_TOM_TGC1_ACT_TB_ACT_TB_MSK (0xffffffu)

/** \brief  Offset for Ifx_GTM_TOM_TGC1_ACT_TB_Bits.ACT_TB */
#define IFX_GTM_TOM_TGC1_ACT_TB_ACT_TB_OFF (0u)

/** \brief  Length for Ifx_GTM_TOM_TGC1_ACT_TB_Bits.TB_TRIG */
#define IFX_GTM_TOM_TGC1_ACT_TB_TB_TRIG_LEN (1u)

/** \brief  Mask for Ifx_GTM_TOM_TGC1_ACT_TB_Bits.TB_TRIG */
#define IFX_GTM_TOM_TGC1_ACT_TB_TB_TRIG_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TOM_TGC1_ACT_TB_Bits.TB_TRIG */
#define IFX_GTM_TOM_TGC1_ACT_TB_TB_TRIG_OFF (24u)

/** \brief  Length for Ifx_GTM_TOM_TGC1_ACT_TB_Bits.TBU_SEL */
#define IFX_GTM_TOM_TGC1_ACT_TB_TBU_SEL_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC1_ACT_TB_Bits.TBU_SEL */
#define IFX_GTM_TOM_TGC1_ACT_TB_TBU_SEL_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC1_ACT_TB_Bits.TBU_SEL */
#define IFX_GTM_TOM_TGC1_ACT_TB_TBU_SEL_OFF (25u)

/** \brief  Length for Ifx_GTM_TOM_TGC1_ENDIS_CTRL_Bits.ENDIS_CTRL0 */
#define IFX_GTM_TOM_TGC1_ENDIS_CTRL_ENDIS_CTRL0_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC1_ENDIS_CTRL_Bits.ENDIS_CTRL0 */
#define IFX_GTM_TOM_TGC1_ENDIS_CTRL_ENDIS_CTRL0_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC1_ENDIS_CTRL_Bits.ENDIS_CTRL0 */
#define IFX_GTM_TOM_TGC1_ENDIS_CTRL_ENDIS_CTRL0_OFF (0u)

/** \brief  Length for Ifx_GTM_TOM_TGC1_ENDIS_CTRL_Bits.ENDIS_CTRL1 */
#define IFX_GTM_TOM_TGC1_ENDIS_CTRL_ENDIS_CTRL1_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC1_ENDIS_CTRL_Bits.ENDIS_CTRL1 */
#define IFX_GTM_TOM_TGC1_ENDIS_CTRL_ENDIS_CTRL1_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC1_ENDIS_CTRL_Bits.ENDIS_CTRL1 */
#define IFX_GTM_TOM_TGC1_ENDIS_CTRL_ENDIS_CTRL1_OFF (2u)

/** \brief  Length for Ifx_GTM_TOM_TGC1_ENDIS_CTRL_Bits.ENDIS_CTRL2 */
#define IFX_GTM_TOM_TGC1_ENDIS_CTRL_ENDIS_CTRL2_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC1_ENDIS_CTRL_Bits.ENDIS_CTRL2 */
#define IFX_GTM_TOM_TGC1_ENDIS_CTRL_ENDIS_CTRL2_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC1_ENDIS_CTRL_Bits.ENDIS_CTRL2 */
#define IFX_GTM_TOM_TGC1_ENDIS_CTRL_ENDIS_CTRL2_OFF (4u)

/** \brief  Length for Ifx_GTM_TOM_TGC1_ENDIS_CTRL_Bits.ENDIS_CTRL3 */
#define IFX_GTM_TOM_TGC1_ENDIS_CTRL_ENDIS_CTRL3_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC1_ENDIS_CTRL_Bits.ENDIS_CTRL3 */
#define IFX_GTM_TOM_TGC1_ENDIS_CTRL_ENDIS_CTRL3_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC1_ENDIS_CTRL_Bits.ENDIS_CTRL3 */
#define IFX_GTM_TOM_TGC1_ENDIS_CTRL_ENDIS_CTRL3_OFF (6u)

/** \brief  Length for Ifx_GTM_TOM_TGC1_ENDIS_CTRL_Bits.ENDIS_CTRL4 */
#define IFX_GTM_TOM_TGC1_ENDIS_CTRL_ENDIS_CTRL4_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC1_ENDIS_CTRL_Bits.ENDIS_CTRL4 */
#define IFX_GTM_TOM_TGC1_ENDIS_CTRL_ENDIS_CTRL4_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC1_ENDIS_CTRL_Bits.ENDIS_CTRL4 */
#define IFX_GTM_TOM_TGC1_ENDIS_CTRL_ENDIS_CTRL4_OFF (8u)

/** \brief  Length for Ifx_GTM_TOM_TGC1_ENDIS_CTRL_Bits.ENDIS_CTRL5 */
#define IFX_GTM_TOM_TGC1_ENDIS_CTRL_ENDIS_CTRL5_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC1_ENDIS_CTRL_Bits.ENDIS_CTRL5 */
#define IFX_GTM_TOM_TGC1_ENDIS_CTRL_ENDIS_CTRL5_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC1_ENDIS_CTRL_Bits.ENDIS_CTRL5 */
#define IFX_GTM_TOM_TGC1_ENDIS_CTRL_ENDIS_CTRL5_OFF (10u)

/** \brief  Length for Ifx_GTM_TOM_TGC1_ENDIS_CTRL_Bits.ENDIS_CTRL6 */
#define IFX_GTM_TOM_TGC1_ENDIS_CTRL_ENDIS_CTRL6_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC1_ENDIS_CTRL_Bits.ENDIS_CTRL6 */
#define IFX_GTM_TOM_TGC1_ENDIS_CTRL_ENDIS_CTRL6_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC1_ENDIS_CTRL_Bits.ENDIS_CTRL6 */
#define IFX_GTM_TOM_TGC1_ENDIS_CTRL_ENDIS_CTRL6_OFF (12u)

/** \brief  Length for Ifx_GTM_TOM_TGC1_ENDIS_CTRL_Bits.ENDIS_CTRL7 */
#define IFX_GTM_TOM_TGC1_ENDIS_CTRL_ENDIS_CTRL7_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC1_ENDIS_CTRL_Bits.ENDIS_CTRL7 */
#define IFX_GTM_TOM_TGC1_ENDIS_CTRL_ENDIS_CTRL7_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC1_ENDIS_CTRL_Bits.ENDIS_CTRL7 */
#define IFX_GTM_TOM_TGC1_ENDIS_CTRL_ENDIS_CTRL7_OFF (14u)

/** \brief  Length for Ifx_GTM_TOM_TGC1_ENDIS_STAT_Bits.ENDIS_STAT0 */
#define IFX_GTM_TOM_TGC1_ENDIS_STAT_ENDIS_STAT0_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC1_ENDIS_STAT_Bits.ENDIS_STAT0 */
#define IFX_GTM_TOM_TGC1_ENDIS_STAT_ENDIS_STAT0_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC1_ENDIS_STAT_Bits.ENDIS_STAT0 */
#define IFX_GTM_TOM_TGC1_ENDIS_STAT_ENDIS_STAT0_OFF (0u)

/** \brief  Length for Ifx_GTM_TOM_TGC1_ENDIS_STAT_Bits.ENDIS_STAT1 */
#define IFX_GTM_TOM_TGC1_ENDIS_STAT_ENDIS_STAT1_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC1_ENDIS_STAT_Bits.ENDIS_STAT1 */
#define IFX_GTM_TOM_TGC1_ENDIS_STAT_ENDIS_STAT1_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC1_ENDIS_STAT_Bits.ENDIS_STAT1 */
#define IFX_GTM_TOM_TGC1_ENDIS_STAT_ENDIS_STAT1_OFF (2u)

/** \brief  Length for Ifx_GTM_TOM_TGC1_ENDIS_STAT_Bits.ENDIS_STAT2 */
#define IFX_GTM_TOM_TGC1_ENDIS_STAT_ENDIS_STAT2_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC1_ENDIS_STAT_Bits.ENDIS_STAT2 */
#define IFX_GTM_TOM_TGC1_ENDIS_STAT_ENDIS_STAT2_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC1_ENDIS_STAT_Bits.ENDIS_STAT2 */
#define IFX_GTM_TOM_TGC1_ENDIS_STAT_ENDIS_STAT2_OFF (4u)

/** \brief  Length for Ifx_GTM_TOM_TGC1_ENDIS_STAT_Bits.ENDIS_STAT3 */
#define IFX_GTM_TOM_TGC1_ENDIS_STAT_ENDIS_STAT3_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC1_ENDIS_STAT_Bits.ENDIS_STAT3 */
#define IFX_GTM_TOM_TGC1_ENDIS_STAT_ENDIS_STAT3_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC1_ENDIS_STAT_Bits.ENDIS_STAT3 */
#define IFX_GTM_TOM_TGC1_ENDIS_STAT_ENDIS_STAT3_OFF (6u)

/** \brief  Length for Ifx_GTM_TOM_TGC1_ENDIS_STAT_Bits.ENDIS_STAT4 */
#define IFX_GTM_TOM_TGC1_ENDIS_STAT_ENDIS_STAT4_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC1_ENDIS_STAT_Bits.ENDIS_STAT4 */
#define IFX_GTM_TOM_TGC1_ENDIS_STAT_ENDIS_STAT4_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC1_ENDIS_STAT_Bits.ENDIS_STAT4 */
#define IFX_GTM_TOM_TGC1_ENDIS_STAT_ENDIS_STAT4_OFF (8u)

/** \brief  Length for Ifx_GTM_TOM_TGC1_ENDIS_STAT_Bits.ENDIS_STAT5 */
#define IFX_GTM_TOM_TGC1_ENDIS_STAT_ENDIS_STAT5_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC1_ENDIS_STAT_Bits.ENDIS_STAT5 */
#define IFX_GTM_TOM_TGC1_ENDIS_STAT_ENDIS_STAT5_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC1_ENDIS_STAT_Bits.ENDIS_STAT5 */
#define IFX_GTM_TOM_TGC1_ENDIS_STAT_ENDIS_STAT5_OFF (10u)

/** \brief  Length for Ifx_GTM_TOM_TGC1_ENDIS_STAT_Bits.ENDIS_STAT6 */
#define IFX_GTM_TOM_TGC1_ENDIS_STAT_ENDIS_STAT6_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC1_ENDIS_STAT_Bits.ENDIS_STAT6 */
#define IFX_GTM_TOM_TGC1_ENDIS_STAT_ENDIS_STAT6_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC1_ENDIS_STAT_Bits.ENDIS_STAT6 */
#define IFX_GTM_TOM_TGC1_ENDIS_STAT_ENDIS_STAT6_OFF (12u)

/** \brief  Length for Ifx_GTM_TOM_TGC1_ENDIS_STAT_Bits.ENDIS_STAT7 */
#define IFX_GTM_TOM_TGC1_ENDIS_STAT_ENDIS_STAT7_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC1_ENDIS_STAT_Bits.ENDIS_STAT7 */
#define IFX_GTM_TOM_TGC1_ENDIS_STAT_ENDIS_STAT7_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC1_ENDIS_STAT_Bits.ENDIS_STAT7 */
#define IFX_GTM_TOM_TGC1_ENDIS_STAT_ENDIS_STAT7_OFF (14u)

/** \brief  Length for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.FUPD_CTRL0 */
#define IFX_GTM_TOM_TGC1_FUPD_CTRL_FUPD_CTRL0_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.FUPD_CTRL0 */
#define IFX_GTM_TOM_TGC1_FUPD_CTRL_FUPD_CTRL0_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.FUPD_CTRL0 */
#define IFX_GTM_TOM_TGC1_FUPD_CTRL_FUPD_CTRL0_OFF (0u)

/** \brief  Length for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.FUPD_CTRL1 */
#define IFX_GTM_TOM_TGC1_FUPD_CTRL_FUPD_CTRL1_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.FUPD_CTRL1 */
#define IFX_GTM_TOM_TGC1_FUPD_CTRL_FUPD_CTRL1_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.FUPD_CTRL1 */
#define IFX_GTM_TOM_TGC1_FUPD_CTRL_FUPD_CTRL1_OFF (2u)

/** \brief  Length for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.FUPD_CTRL2 */
#define IFX_GTM_TOM_TGC1_FUPD_CTRL_FUPD_CTRL2_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.FUPD_CTRL2 */
#define IFX_GTM_TOM_TGC1_FUPD_CTRL_FUPD_CTRL2_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.FUPD_CTRL2 */
#define IFX_GTM_TOM_TGC1_FUPD_CTRL_FUPD_CTRL2_OFF (4u)

/** \brief  Length for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.FUPD_CTRL3 */
#define IFX_GTM_TOM_TGC1_FUPD_CTRL_FUPD_CTRL3_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.FUPD_CTRL3 */
#define IFX_GTM_TOM_TGC1_FUPD_CTRL_FUPD_CTRL3_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.FUPD_CTRL3 */
#define IFX_GTM_TOM_TGC1_FUPD_CTRL_FUPD_CTRL3_OFF (6u)

/** \brief  Length for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.FUPD_CTRL4 */
#define IFX_GTM_TOM_TGC1_FUPD_CTRL_FUPD_CTRL4_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.FUPD_CTRL4 */
#define IFX_GTM_TOM_TGC1_FUPD_CTRL_FUPD_CTRL4_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.FUPD_CTRL4 */
#define IFX_GTM_TOM_TGC1_FUPD_CTRL_FUPD_CTRL4_OFF (8u)

/** \brief  Length for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.FUPD_CTRL5 */
#define IFX_GTM_TOM_TGC1_FUPD_CTRL_FUPD_CTRL5_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.FUPD_CTRL5 */
#define IFX_GTM_TOM_TGC1_FUPD_CTRL_FUPD_CTRL5_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.FUPD_CTRL5 */
#define IFX_GTM_TOM_TGC1_FUPD_CTRL_FUPD_CTRL5_OFF (10u)

/** \brief  Length for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.FUPD_CTRL6 */
#define IFX_GTM_TOM_TGC1_FUPD_CTRL_FUPD_CTRL6_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.FUPD_CTRL6 */
#define IFX_GTM_TOM_TGC1_FUPD_CTRL_FUPD_CTRL6_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.FUPD_CTRL6 */
#define IFX_GTM_TOM_TGC1_FUPD_CTRL_FUPD_CTRL6_OFF (12u)

/** \brief  Length for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.FUPD_CTRL7 */
#define IFX_GTM_TOM_TGC1_FUPD_CTRL_FUPD_CTRL7_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.FUPD_CTRL7 */
#define IFX_GTM_TOM_TGC1_FUPD_CTRL_FUPD_CTRL7_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.FUPD_CTRL7 */
#define IFX_GTM_TOM_TGC1_FUPD_CTRL_FUPD_CTRL7_OFF (14u)

/** \brief  Length for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.RSTCN0_CH0 */
#define IFX_GTM_TOM_TGC1_FUPD_CTRL_RSTCN0_CH0_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.RSTCN0_CH0 */
#define IFX_GTM_TOM_TGC1_FUPD_CTRL_RSTCN0_CH0_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.RSTCN0_CH0 */
#define IFX_GTM_TOM_TGC1_FUPD_CTRL_RSTCN0_CH0_OFF (16u)

/** \brief  Length for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.RSTCN0_CH1 */
#define IFX_GTM_TOM_TGC1_FUPD_CTRL_RSTCN0_CH1_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.RSTCN0_CH1 */
#define IFX_GTM_TOM_TGC1_FUPD_CTRL_RSTCN0_CH1_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.RSTCN0_CH1 */
#define IFX_GTM_TOM_TGC1_FUPD_CTRL_RSTCN0_CH1_OFF (18u)

/** \brief  Length for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.RSTCN0_CH2 */
#define IFX_GTM_TOM_TGC1_FUPD_CTRL_RSTCN0_CH2_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.RSTCN0_CH2 */
#define IFX_GTM_TOM_TGC1_FUPD_CTRL_RSTCN0_CH2_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.RSTCN0_CH2 */
#define IFX_GTM_TOM_TGC1_FUPD_CTRL_RSTCN0_CH2_OFF (20u)

/** \brief  Length for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.RSTCN0_CH3 */
#define IFX_GTM_TOM_TGC1_FUPD_CTRL_RSTCN0_CH3_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.RSTCN0_CH3 */
#define IFX_GTM_TOM_TGC1_FUPD_CTRL_RSTCN0_CH3_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.RSTCN0_CH3 */
#define IFX_GTM_TOM_TGC1_FUPD_CTRL_RSTCN0_CH3_OFF (22u)

/** \brief  Length for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.RSTCN0_CH4 */
#define IFX_GTM_TOM_TGC1_FUPD_CTRL_RSTCN0_CH4_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.RSTCN0_CH4 */
#define IFX_GTM_TOM_TGC1_FUPD_CTRL_RSTCN0_CH4_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.RSTCN0_CH4 */
#define IFX_GTM_TOM_TGC1_FUPD_CTRL_RSTCN0_CH4_OFF (24u)

/** \brief  Length for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.RSTCN0_CH5 */
#define IFX_GTM_TOM_TGC1_FUPD_CTRL_RSTCN0_CH5_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.RSTCN0_CH5 */
#define IFX_GTM_TOM_TGC1_FUPD_CTRL_RSTCN0_CH5_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.RSTCN0_CH5 */
#define IFX_GTM_TOM_TGC1_FUPD_CTRL_RSTCN0_CH5_OFF (26u)

/** \brief  Length for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.RSTCN0_CH6 */
#define IFX_GTM_TOM_TGC1_FUPD_CTRL_RSTCN0_CH6_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.RSTCN0_CH6 */
#define IFX_GTM_TOM_TGC1_FUPD_CTRL_RSTCN0_CH6_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.RSTCN0_CH6 */
#define IFX_GTM_TOM_TGC1_FUPD_CTRL_RSTCN0_CH6_OFF (28u)

/** \brief  Length for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.RSTCN0_CH7 */
#define IFX_GTM_TOM_TGC1_FUPD_CTRL_RSTCN0_CH7_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.RSTCN0_CH7 */
#define IFX_GTM_TOM_TGC1_FUPD_CTRL_RSTCN0_CH7_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC1_FUPD_CTRL_Bits.RSTCN0_CH7 */
#define IFX_GTM_TOM_TGC1_FUPD_CTRL_RSTCN0_CH7_OFF (30u)

/** \brief  Length for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.HOST_TRIG */
#define IFX_GTM_TOM_TGC1_GLB_CTRL_HOST_TRIG_LEN (1u)

/** \brief  Mask for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.HOST_TRIG */
#define IFX_GTM_TOM_TGC1_GLB_CTRL_HOST_TRIG_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.HOST_TRIG */
#define IFX_GTM_TOM_TGC1_GLB_CTRL_HOST_TRIG_OFF (0u)

/** \brief  Length for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.RST_CH0 */
#define IFX_GTM_TOM_TGC1_GLB_CTRL_RST_CH0_LEN (1u)

/** \brief  Mask for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.RST_CH0 */
#define IFX_GTM_TOM_TGC1_GLB_CTRL_RST_CH0_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.RST_CH0 */
#define IFX_GTM_TOM_TGC1_GLB_CTRL_RST_CH0_OFF (8u)

/** \brief  Length for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.RST_CH1 */
#define IFX_GTM_TOM_TGC1_GLB_CTRL_RST_CH1_LEN (1u)

/** \brief  Mask for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.RST_CH1 */
#define IFX_GTM_TOM_TGC1_GLB_CTRL_RST_CH1_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.RST_CH1 */
#define IFX_GTM_TOM_TGC1_GLB_CTRL_RST_CH1_OFF (9u)

/** \brief  Length for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.RST_CH2 */
#define IFX_GTM_TOM_TGC1_GLB_CTRL_RST_CH2_LEN (1u)

/** \brief  Mask for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.RST_CH2 */
#define IFX_GTM_TOM_TGC1_GLB_CTRL_RST_CH2_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.RST_CH2 */
#define IFX_GTM_TOM_TGC1_GLB_CTRL_RST_CH2_OFF (10u)

/** \brief  Length for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.RST_CH3 */
#define IFX_GTM_TOM_TGC1_GLB_CTRL_RST_CH3_LEN (1u)

/** \brief  Mask for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.RST_CH3 */
#define IFX_GTM_TOM_TGC1_GLB_CTRL_RST_CH3_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.RST_CH3 */
#define IFX_GTM_TOM_TGC1_GLB_CTRL_RST_CH3_OFF (11u)

/** \brief  Length for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.RST_CH4 */
#define IFX_GTM_TOM_TGC1_GLB_CTRL_RST_CH4_LEN (1u)

/** \brief  Mask for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.RST_CH4 */
#define IFX_GTM_TOM_TGC1_GLB_CTRL_RST_CH4_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.RST_CH4 */
#define IFX_GTM_TOM_TGC1_GLB_CTRL_RST_CH4_OFF (12u)

/** \brief  Length for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.RST_CH5 */
#define IFX_GTM_TOM_TGC1_GLB_CTRL_RST_CH5_LEN (1u)

/** \brief  Mask for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.RST_CH5 */
#define IFX_GTM_TOM_TGC1_GLB_CTRL_RST_CH5_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.RST_CH5 */
#define IFX_GTM_TOM_TGC1_GLB_CTRL_RST_CH5_OFF (13u)

/** \brief  Length for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.RST_CH6 */
#define IFX_GTM_TOM_TGC1_GLB_CTRL_RST_CH6_LEN (1u)

/** \brief  Mask for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.RST_CH6 */
#define IFX_GTM_TOM_TGC1_GLB_CTRL_RST_CH6_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.RST_CH6 */
#define IFX_GTM_TOM_TGC1_GLB_CTRL_RST_CH6_OFF (14u)

/** \brief  Length for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.RST_CH7 */
#define IFX_GTM_TOM_TGC1_GLB_CTRL_RST_CH7_LEN (1u)

/** \brief  Mask for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.RST_CH7 */
#define IFX_GTM_TOM_TGC1_GLB_CTRL_RST_CH7_MSK (0x1u)

/** \brief  Offset for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.RST_CH7 */
#define IFX_GTM_TOM_TGC1_GLB_CTRL_RST_CH7_OFF (15u)

/** \brief  Length for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.UPEN_CTRL0 */
#define IFX_GTM_TOM_TGC1_GLB_CTRL_UPEN_CTRL0_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.UPEN_CTRL0 */
#define IFX_GTM_TOM_TGC1_GLB_CTRL_UPEN_CTRL0_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.UPEN_CTRL0 */
#define IFX_GTM_TOM_TGC1_GLB_CTRL_UPEN_CTRL0_OFF (16u)

/** \brief  Length for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.UPEN_CTRL1 */
#define IFX_GTM_TOM_TGC1_GLB_CTRL_UPEN_CTRL1_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.UPEN_CTRL1 */
#define IFX_GTM_TOM_TGC1_GLB_CTRL_UPEN_CTRL1_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.UPEN_CTRL1 */
#define IFX_GTM_TOM_TGC1_GLB_CTRL_UPEN_CTRL1_OFF (18u)

/** \brief  Length for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.UPEN_CTRL2 */
#define IFX_GTM_TOM_TGC1_GLB_CTRL_UPEN_CTRL2_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.UPEN_CTRL2 */
#define IFX_GTM_TOM_TGC1_GLB_CTRL_UPEN_CTRL2_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.UPEN_CTRL2 */
#define IFX_GTM_TOM_TGC1_GLB_CTRL_UPEN_CTRL2_OFF (20u)

/** \brief  Length for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.UPEN_CTRL3 */
#define IFX_GTM_TOM_TGC1_GLB_CTRL_UPEN_CTRL3_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.UPEN_CTRL3 */
#define IFX_GTM_TOM_TGC1_GLB_CTRL_UPEN_CTRL3_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.UPEN_CTRL3 */
#define IFX_GTM_TOM_TGC1_GLB_CTRL_UPEN_CTRL3_OFF (22u)

/** \brief  Length for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.UPEN_CTRL4 */
#define IFX_GTM_TOM_TGC1_GLB_CTRL_UPEN_CTRL4_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.UPEN_CTRL4 */
#define IFX_GTM_TOM_TGC1_GLB_CTRL_UPEN_CTRL4_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.UPEN_CTRL4 */
#define IFX_GTM_TOM_TGC1_GLB_CTRL_UPEN_CTRL4_OFF (24u)

/** \brief  Length for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.UPEN_CTRL5 */
#define IFX_GTM_TOM_TGC1_GLB_CTRL_UPEN_CTRL5_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.UPEN_CTRL5 */
#define IFX_GTM_TOM_TGC1_GLB_CTRL_UPEN_CTRL5_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.UPEN_CTRL5 */
#define IFX_GTM_TOM_TGC1_GLB_CTRL_UPEN_CTRL5_OFF (26u)

/** \brief  Length for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.UPEN_CTRL6 */
#define IFX_GTM_TOM_TGC1_GLB_CTRL_UPEN_CTRL6_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.UPEN_CTRL6 */
#define IFX_GTM_TOM_TGC1_GLB_CTRL_UPEN_CTRL6_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.UPEN_CTRL6 */
#define IFX_GTM_TOM_TGC1_GLB_CTRL_UPEN_CTRL6_OFF (28u)

/** \brief  Length for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.UPEN_CTRL7 */
#define IFX_GTM_TOM_TGC1_GLB_CTRL_UPEN_CTRL7_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.UPEN_CTRL7 */
#define IFX_GTM_TOM_TGC1_GLB_CTRL_UPEN_CTRL7_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC1_GLB_CTRL_Bits.UPEN_CTRL7 */
#define IFX_GTM_TOM_TGC1_GLB_CTRL_UPEN_CTRL7_OFF (30u)

/** \brief  Length for Ifx_GTM_TOM_TGC1_INT_TRIG_Bits.INT_TRIG0 */
#define IFX_GTM_TOM_TGC1_INT_TRIG_INT_TRIG0_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC1_INT_TRIG_Bits.INT_TRIG0 */
#define IFX_GTM_TOM_TGC1_INT_TRIG_INT_TRIG0_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC1_INT_TRIG_Bits.INT_TRIG0 */
#define IFX_GTM_TOM_TGC1_INT_TRIG_INT_TRIG0_OFF (0u)

/** \brief  Length for Ifx_GTM_TOM_TGC1_INT_TRIG_Bits.INT_TRIG1 */
#define IFX_GTM_TOM_TGC1_INT_TRIG_INT_TRIG1_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC1_INT_TRIG_Bits.INT_TRIG1 */
#define IFX_GTM_TOM_TGC1_INT_TRIG_INT_TRIG1_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC1_INT_TRIG_Bits.INT_TRIG1 */
#define IFX_GTM_TOM_TGC1_INT_TRIG_INT_TRIG1_OFF (2u)

/** \brief  Length for Ifx_GTM_TOM_TGC1_INT_TRIG_Bits.INT_TRIG2 */
#define IFX_GTM_TOM_TGC1_INT_TRIG_INT_TRIG2_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC1_INT_TRIG_Bits.INT_TRIG2 */
#define IFX_GTM_TOM_TGC1_INT_TRIG_INT_TRIG2_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC1_INT_TRIG_Bits.INT_TRIG2 */
#define IFX_GTM_TOM_TGC1_INT_TRIG_INT_TRIG2_OFF (4u)

/** \brief  Length for Ifx_GTM_TOM_TGC1_INT_TRIG_Bits.INT_TRIG3 */
#define IFX_GTM_TOM_TGC1_INT_TRIG_INT_TRIG3_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC1_INT_TRIG_Bits.INT_TRIG3 */
#define IFX_GTM_TOM_TGC1_INT_TRIG_INT_TRIG3_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC1_INT_TRIG_Bits.INT_TRIG3 */
#define IFX_GTM_TOM_TGC1_INT_TRIG_INT_TRIG3_OFF (6u)

/** \brief  Length for Ifx_GTM_TOM_TGC1_INT_TRIG_Bits.INT_TRIG4 */
#define IFX_GTM_TOM_TGC1_INT_TRIG_INT_TRIG4_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC1_INT_TRIG_Bits.INT_TRIG4 */
#define IFX_GTM_TOM_TGC1_INT_TRIG_INT_TRIG4_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC1_INT_TRIG_Bits.INT_TRIG4 */
#define IFX_GTM_TOM_TGC1_INT_TRIG_INT_TRIG4_OFF (8u)

/** \brief  Length for Ifx_GTM_TOM_TGC1_INT_TRIG_Bits.INT_TRIG5 */
#define IFX_GTM_TOM_TGC1_INT_TRIG_INT_TRIG5_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC1_INT_TRIG_Bits.INT_TRIG5 */
#define IFX_GTM_TOM_TGC1_INT_TRIG_INT_TRIG5_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC1_INT_TRIG_Bits.INT_TRIG5 */
#define IFX_GTM_TOM_TGC1_INT_TRIG_INT_TRIG5_OFF (10u)

/** \brief  Length for Ifx_GTM_TOM_TGC1_INT_TRIG_Bits.INT_TRIG6 */
#define IFX_GTM_TOM_TGC1_INT_TRIG_INT_TRIG6_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC1_INT_TRIG_Bits.INT_TRIG6 */
#define IFX_GTM_TOM_TGC1_INT_TRIG_INT_TRIG6_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC1_INT_TRIG_Bits.INT_TRIG6 */
#define IFX_GTM_TOM_TGC1_INT_TRIG_INT_TRIG6_OFF (12u)

/** \brief  Length for Ifx_GTM_TOM_TGC1_INT_TRIG_Bits.INT_TRIG7 */
#define IFX_GTM_TOM_TGC1_INT_TRIG_INT_TRIG7_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC1_INT_TRIG_Bits.INT_TRIG7 */
#define IFX_GTM_TOM_TGC1_INT_TRIG_INT_TRIG7_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC1_INT_TRIG_Bits.INT_TRIG7 */
#define IFX_GTM_TOM_TGC1_INT_TRIG_INT_TRIG7_OFF (14u)

/** \brief  Length for Ifx_GTM_TOM_TGC1_OUTEN_CTRL_Bits.OUTEN_CTRL0 */
#define IFX_GTM_TOM_TGC1_OUTEN_CTRL_OUTEN_CTRL0_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC1_OUTEN_CTRL_Bits.OUTEN_CTRL0 */
#define IFX_GTM_TOM_TGC1_OUTEN_CTRL_OUTEN_CTRL0_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC1_OUTEN_CTRL_Bits.OUTEN_CTRL0 */
#define IFX_GTM_TOM_TGC1_OUTEN_CTRL_OUTEN_CTRL0_OFF (0u)

/** \brief  Length for Ifx_GTM_TOM_TGC1_OUTEN_CTRL_Bits.OUTEN_CTRL1 */
#define IFX_GTM_TOM_TGC1_OUTEN_CTRL_OUTEN_CTRL1_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC1_OUTEN_CTRL_Bits.OUTEN_CTRL1 */
#define IFX_GTM_TOM_TGC1_OUTEN_CTRL_OUTEN_CTRL1_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC1_OUTEN_CTRL_Bits.OUTEN_CTRL1 */
#define IFX_GTM_TOM_TGC1_OUTEN_CTRL_OUTEN_CTRL1_OFF (2u)

/** \brief  Length for Ifx_GTM_TOM_TGC1_OUTEN_CTRL_Bits.OUTEN_CTRL2 */
#define IFX_GTM_TOM_TGC1_OUTEN_CTRL_OUTEN_CTRL2_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC1_OUTEN_CTRL_Bits.OUTEN_CTRL2 */
#define IFX_GTM_TOM_TGC1_OUTEN_CTRL_OUTEN_CTRL2_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC1_OUTEN_CTRL_Bits.OUTEN_CTRL2 */
#define IFX_GTM_TOM_TGC1_OUTEN_CTRL_OUTEN_CTRL2_OFF (4u)

/** \brief  Length for Ifx_GTM_TOM_TGC1_OUTEN_CTRL_Bits.OUTEN_CTRL3 */
#define IFX_GTM_TOM_TGC1_OUTEN_CTRL_OUTEN_CTRL3_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC1_OUTEN_CTRL_Bits.OUTEN_CTRL3 */
#define IFX_GTM_TOM_TGC1_OUTEN_CTRL_OUTEN_CTRL3_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC1_OUTEN_CTRL_Bits.OUTEN_CTRL3 */
#define IFX_GTM_TOM_TGC1_OUTEN_CTRL_OUTEN_CTRL3_OFF (6u)

/** \brief  Length for Ifx_GTM_TOM_TGC1_OUTEN_CTRL_Bits.OUTEN_CTRL4 */
#define IFX_GTM_TOM_TGC1_OUTEN_CTRL_OUTEN_CTRL4_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC1_OUTEN_CTRL_Bits.OUTEN_CTRL4 */
#define IFX_GTM_TOM_TGC1_OUTEN_CTRL_OUTEN_CTRL4_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC1_OUTEN_CTRL_Bits.OUTEN_CTRL4 */
#define IFX_GTM_TOM_TGC1_OUTEN_CTRL_OUTEN_CTRL4_OFF (8u)

/** \brief  Length for Ifx_GTM_TOM_TGC1_OUTEN_CTRL_Bits.OUTEN_CTRL5 */
#define IFX_GTM_TOM_TGC1_OUTEN_CTRL_OUTEN_CTRL5_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC1_OUTEN_CTRL_Bits.OUTEN_CTRL5 */
#define IFX_GTM_TOM_TGC1_OUTEN_CTRL_OUTEN_CTRL5_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC1_OUTEN_CTRL_Bits.OUTEN_CTRL5 */
#define IFX_GTM_TOM_TGC1_OUTEN_CTRL_OUTEN_CTRL5_OFF (10u)

/** \brief  Length for Ifx_GTM_TOM_TGC1_OUTEN_CTRL_Bits.OUTEN_CTRL6 */
#define IFX_GTM_TOM_TGC1_OUTEN_CTRL_OUTEN_CTRL6_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC1_OUTEN_CTRL_Bits.OUTEN_CTRL6 */
#define IFX_GTM_TOM_TGC1_OUTEN_CTRL_OUTEN_CTRL6_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC1_OUTEN_CTRL_Bits.OUTEN_CTRL6 */
#define IFX_GTM_TOM_TGC1_OUTEN_CTRL_OUTEN_CTRL6_OFF (12u)

/** \brief  Length for Ifx_GTM_TOM_TGC1_OUTEN_CTRL_Bits.OUTEN_CTRL7 */
#define IFX_GTM_TOM_TGC1_OUTEN_CTRL_OUTEN_CTRL7_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC1_OUTEN_CTRL_Bits.OUTEN_CTRL7 */
#define IFX_GTM_TOM_TGC1_OUTEN_CTRL_OUTEN_CTRL7_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC1_OUTEN_CTRL_Bits.OUTEN_CTRL7 */
#define IFX_GTM_TOM_TGC1_OUTEN_CTRL_OUTEN_CTRL7_OFF (14u)

/** \brief  Length for Ifx_GTM_TOM_TGC1_OUTEN_STAT_Bits.OUTEN_STAT0 */
#define IFX_GTM_TOM_TGC1_OUTEN_STAT_OUTEN_STAT0_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC1_OUTEN_STAT_Bits.OUTEN_STAT0 */
#define IFX_GTM_TOM_TGC1_OUTEN_STAT_OUTEN_STAT0_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC1_OUTEN_STAT_Bits.OUTEN_STAT0 */
#define IFX_GTM_TOM_TGC1_OUTEN_STAT_OUTEN_STAT0_OFF (0u)

/** \brief  Length for Ifx_GTM_TOM_TGC1_OUTEN_STAT_Bits.OUTEN_STAT1 */
#define IFX_GTM_TOM_TGC1_OUTEN_STAT_OUTEN_STAT1_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC1_OUTEN_STAT_Bits.OUTEN_STAT1 */
#define IFX_GTM_TOM_TGC1_OUTEN_STAT_OUTEN_STAT1_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC1_OUTEN_STAT_Bits.OUTEN_STAT1 */
#define IFX_GTM_TOM_TGC1_OUTEN_STAT_OUTEN_STAT1_OFF (2u)

/** \brief  Length for Ifx_GTM_TOM_TGC1_OUTEN_STAT_Bits.OUTEN_STAT2 */
#define IFX_GTM_TOM_TGC1_OUTEN_STAT_OUTEN_STAT2_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC1_OUTEN_STAT_Bits.OUTEN_STAT2 */
#define IFX_GTM_TOM_TGC1_OUTEN_STAT_OUTEN_STAT2_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC1_OUTEN_STAT_Bits.OUTEN_STAT2 */
#define IFX_GTM_TOM_TGC1_OUTEN_STAT_OUTEN_STAT2_OFF (4u)

/** \brief  Length for Ifx_GTM_TOM_TGC1_OUTEN_STAT_Bits.OUTEN_STAT3 */
#define IFX_GTM_TOM_TGC1_OUTEN_STAT_OUTEN_STAT3_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC1_OUTEN_STAT_Bits.OUTEN_STAT3 */
#define IFX_GTM_TOM_TGC1_OUTEN_STAT_OUTEN_STAT3_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC1_OUTEN_STAT_Bits.OUTEN_STAT3 */
#define IFX_GTM_TOM_TGC1_OUTEN_STAT_OUTEN_STAT3_OFF (6u)

/** \brief  Length for Ifx_GTM_TOM_TGC1_OUTEN_STAT_Bits.OUTEN_STAT4 */
#define IFX_GTM_TOM_TGC1_OUTEN_STAT_OUTEN_STAT4_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC1_OUTEN_STAT_Bits.OUTEN_STAT4 */
#define IFX_GTM_TOM_TGC1_OUTEN_STAT_OUTEN_STAT4_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC1_OUTEN_STAT_Bits.OUTEN_STAT4 */
#define IFX_GTM_TOM_TGC1_OUTEN_STAT_OUTEN_STAT4_OFF (8u)

/** \brief  Length for Ifx_GTM_TOM_TGC1_OUTEN_STAT_Bits.OUTEN_STAT5 */
#define IFX_GTM_TOM_TGC1_OUTEN_STAT_OUTEN_STAT5_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC1_OUTEN_STAT_Bits.OUTEN_STAT5 */
#define IFX_GTM_TOM_TGC1_OUTEN_STAT_OUTEN_STAT5_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC1_OUTEN_STAT_Bits.OUTEN_STAT5 */
#define IFX_GTM_TOM_TGC1_OUTEN_STAT_OUTEN_STAT5_OFF (10u)

/** \brief  Length for Ifx_GTM_TOM_TGC1_OUTEN_STAT_Bits.OUTEN_STAT6 */
#define IFX_GTM_TOM_TGC1_OUTEN_STAT_OUTEN_STAT6_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC1_OUTEN_STAT_Bits.OUTEN_STAT6 */
#define IFX_GTM_TOM_TGC1_OUTEN_STAT_OUTEN_STAT6_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC1_OUTEN_STAT_Bits.OUTEN_STAT6 */
#define IFX_GTM_TOM_TGC1_OUTEN_STAT_OUTEN_STAT6_OFF (12u)

/** \brief  Length for Ifx_GTM_TOM_TGC1_OUTEN_STAT_Bits.OUTEN_STAT7 */
#define IFX_GTM_TOM_TGC1_OUTEN_STAT_OUTEN_STAT7_LEN (2u)

/** \brief  Mask for Ifx_GTM_TOM_TGC1_OUTEN_STAT_Bits.OUTEN_STAT7 */
#define IFX_GTM_TOM_TGC1_OUTEN_STAT_OUTEN_STAT7_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TOM_TGC1_OUTEN_STAT_Bits.OUTEN_STAT7 */
#define IFX_GTM_TOM_TGC1_OUTEN_STAT_OUTEN_STAT7_OFF (14u)

/** \brief  Length for Ifx_GTM_TRIGOUT_Bits.INT0 */
#define IFX_GTM_TRIGOUT_INT0_LEN (2u)

/** \brief  Mask for Ifx_GTM_TRIGOUT_Bits.INT0 */
#define IFX_GTM_TRIGOUT_INT0_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TRIGOUT_Bits.INT0 */
#define IFX_GTM_TRIGOUT_INT0_OFF (0u)

/** \brief  Length for Ifx_GTM_TRIGOUT_Bits.INT1 */
#define IFX_GTM_TRIGOUT_INT1_LEN (2u)

/** \brief  Mask for Ifx_GTM_TRIGOUT_Bits.INT1 */
#define IFX_GTM_TRIGOUT_INT1_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TRIGOUT_Bits.INT1 */
#define IFX_GTM_TRIGOUT_INT1_OFF (2u)

/** \brief  Length for Ifx_GTM_TRIGOUT_Bits.TRIG0 */
#define IFX_GTM_TRIGOUT_TRIG0_LEN (2u)

/** \brief  Mask for Ifx_GTM_TRIGOUT_Bits.TRIG0 */
#define IFX_GTM_TRIGOUT_TRIG0_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TRIGOUT_Bits.TRIG0 */
#define IFX_GTM_TRIGOUT_TRIG0_OFF (4u)

/** \brief  Length for Ifx_GTM_TRIGOUT_Bits.TRIG1 */
#define IFX_GTM_TRIGOUT_TRIG1_LEN (2u)

/** \brief  Mask for Ifx_GTM_TRIGOUT_Bits.TRIG1 */
#define IFX_GTM_TRIGOUT_TRIG1_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TRIGOUT_Bits.TRIG1 */
#define IFX_GTM_TRIGOUT_TRIG1_OFF (6u)

/** \brief  Length for Ifx_GTM_TRIGOUT_Bits.TRIG2 */
#define IFX_GTM_TRIGOUT_TRIG2_LEN (2u)

/** \brief  Mask for Ifx_GTM_TRIGOUT_Bits.TRIG2 */
#define IFX_GTM_TRIGOUT_TRIG2_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TRIGOUT_Bits.TRIG2 */
#define IFX_GTM_TRIGOUT_TRIG2_OFF (8u)

/** \brief  Length for Ifx_GTM_TRIGOUT_Bits.TRIG3 */
#define IFX_GTM_TRIGOUT_TRIG3_LEN (2u)

/** \brief  Mask for Ifx_GTM_TRIGOUT_Bits.TRIG3 */
#define IFX_GTM_TRIGOUT_TRIG3_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TRIGOUT_Bits.TRIG3 */
#define IFX_GTM_TRIGOUT_TRIG3_OFF (10u)

/** \brief  Length for Ifx_GTM_TRIGOUT_Bits.TRIG4 */
#define IFX_GTM_TRIGOUT_TRIG4_LEN (2u)

/** \brief  Mask for Ifx_GTM_TRIGOUT_Bits.TRIG4 */
#define IFX_GTM_TRIGOUT_TRIG4_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TRIGOUT_Bits.TRIG4 */
#define IFX_GTM_TRIGOUT_TRIG4_OFF (12u)

/** \brief  Length for Ifx_GTM_TRIGOUT_Bits.TRIG5 */
#define IFX_GTM_TRIGOUT_TRIG5_LEN (2u)

/** \brief  Mask for Ifx_GTM_TRIGOUT_Bits.TRIG5 */
#define IFX_GTM_TRIGOUT_TRIG5_MSK (0x3u)

/** \brief  Offset for Ifx_GTM_TRIGOUT_Bits.TRIG5 */
#define IFX_GTM_TRIGOUT_TRIG5_OFF (14u)
/** \}  */
/******************************************************************************/
/******************************************************************************/
#endif /* IFXGTM_BF_H */
