/* *****************************************************************************
 * BEGIN: Banner
 *-----------------------------------------------------------------------------
 *                                 ETAS GmbH
 *                      D-70469 Stuttgart, Borsigstr. 14
 *-----------------------------------------------------------------------------
 *    Administrative Information (automatically filled in by ISOLAR)
 *-----------------------------------------------------------------------------
 * Name: Code-Frame generation feature
 * Description:
 * Version: 7.0
 *-----------------------------------------------------------------------------
 * END: Banner
 ******************************************************************************

 * Project : RTA-BSW Starter Kit
 * Component:
 * Runnable : All Runnables in SwComponent
 *****************************************************************************
 * Tool Version: ISOLAR-A V 8.0
 * Author: BAL9YOK
 * Date :
 ****************************************************************************/

#include "Rte_Memory_SWC.h"

#define Memory_SWC_START_SEC_CODE
#include "Memory_SWC_MemMap.h"


volatile uint32 ASW_task_cnt;
volatile uint32 SWC_NvM_Test_cnt;


uint32 test;
uint8 Pim1_first, Pim1_last, Pim2_first, Pim2_last, Pim3_first, Pim3_last;
//uint8 DataBlock1[64], DataBlock2[64], DataBlock3[64];
#define CALIB_START_SEC
#include "MemMap.h"
volatile uint8 Calib_test = 0U;

#define CALIB_STOP_SEC
#include "MemMap.h"

volatile  uint32 calib;

uint8 NvM_TestCase, NvM_TestCase_old;
uint8 r_flags = 0;

uint8 dataW[64];
uint8 dataR[64];
uint8 Write_Flag;

FUNC (void, Test_CODE) RE_Memory_SWC // return value & FctID
(
		void
)
{
	uint8 i;

	SWC_NvM_Test_cnt++;
	calib = Calib_test;

	/* XCP test */
	if( Calib_test != 0 )
		ASW_task_cnt++;
	/* XCP test end */

	NvM_TestCase = Rte_IRead_RE_Memory_SWC_RPort_TST_DiagMeM_test_TST_DiagMeM_test();
	Rte_Write_PPort_TST_Diag_TestNumber_uint8_Impl(NvM_TestCase);

	if( NvM_TestCase != NvM_TestCase_old )
	{
		switch(NvM_TestCase)
		{
		case 0x07:
			Rte_CPim_Memory_SWC_PIM_SWC_01[0]=Rte_IRead_RE_Memory_SWC_RPort_TST_PIM_FirstByte_TST_PIM_FirstByte();
			Rte_CPim_Memory_SWC_PIM_SWC_01[63]=Rte_IRead_RE_Memory_SWC_RPort_TST_PIM_LastByte_TST_PIM_LastByte();
			break;
		case 0x08:
			Rte_CPim_Memory_SWC_PIM_SWC_02[0]=Rte_IRead_RE_Memory_SWC_RPort_TST_PIM_FirstByte_TST_PIM_FirstByte();
			Rte_CPim_Memory_SWC_PIM_SWC_02[63]=Rte_IRead_RE_Memory_SWC_RPort_TST_PIM_LastByte_TST_PIM_LastByte();
			break;
		case 0x09:
			Rte_CPim_Memory_SWC_PIM_SWC_03[0]=Rte_IRead_RE_Memory_SWC_RPort_TST_PIM_FirstByte_TST_PIM_FirstByte();
			Rte_CPim_Memory_SWC_PIM_SWC_03[63]=Rte_IRead_RE_Memory_SWC_RPort_TST_PIM_LastByte_TST_PIM_LastByte();
			break;
		case 0x0A:
			Rte_Call_RPort_NvM_NativeBlock_2_SetRamBlockStatus(TRUE);
			break;
		case 0x0B:
			Rte_Call_RPort_NvM_NativeBlock_3_SetRamBlockStatus(TRUE);
			break;
		case 0x0C:
			Rte_Call_RPort_NvM_NativeBlock_4_SetRamBlockStatus(TRUE);
			break;
		case 0x0D:
			for(i=0;i<64;i++)
			{
				Rte_CPim_Memory_SWC_PIM_SWC_01[i]+=i;
				Rte_CPim_Memory_SWC_PIM_SWC_02[i]+=i;
				Rte_CPim_Memory_SWC_PIM_SWC_03[i]+=i;
			}
			Rte_Call_RPort_NvM_NativeBlock_2_SetRamBlockStatus(TRUE);
			Rte_Call_RPort_NvM_NativeBlock_3_SetRamBlockStatus(TRUE);
			Rte_Call_RPort_NvM_NativeBlock_4_SetRamBlockStatus(TRUE);
			break;
		default:
			break;
		}
		NvM_TestCase_old = NvM_TestCase;
	}

	if(NvM_TestCase == 0x0E){
		Rte_Write_PPort_Pim1_First_Pim1_First(Rte_CPim_Memory_SWC_PIM_SWC_01[0]);
		Rte_Write_PPort_Pim1_Last_Pim1_Last(Rte_CPim_Memory_SWC_PIM_SWC_01[63]);

		Rte_Write_PPort_Pim2_First_Pim2_First(Rte_CPim_Memory_SWC_PIM_SWC_02[0]);
		Rte_Write_PPort_Pim2_Last_Pim2_Last(Rte_CPim_Memory_SWC_PIM_SWC_02[63]);

		Rte_Write_PPort_Pim3_First_Pim3_First(Rte_CPim_Memory_SWC_PIM_SWC_03[0]);
		Rte_Write_PPort_Pim3_Last_Pim3_Last(Rte_CPim_Memory_SWC_PIM_SWC_03[63]);

	}

	if(NvM_TestCase == 0x0F) {
		if(Write_Flag == 0){
			for (i = 0; i < 64; i++){
				dataW[i]++;
			}
			Rte_Call_RPort_NvM_NativeBlock_2_WriteBlock(dataW);
			Write_Flag++;
		}else if(Write_Flag < 20){
			Write_Flag++;
		}else if(Write_Flag == 20){
			for (i = 0; i < 64; i++){
				dataR[i] = 0;
			}
			Rte_Call_RPort_NvM_NativeBlock_2_ReadBlock(dataR);
			Write_Flag++;
		}else if(Write_Flag < 30){
			Write_Flag++;
		}else if(Write_Flag == 30){
			Rte_Write_PPort_Pim1_First_Pim1_First(dataR[0]);
			Rte_Write_PPort_Pim1_Last_Pim1_Last(dataR[63]);
			Write_Flag = 0;
		}
	}

}

#define Memory_SWC_START_SEC_CODE
#include "Memory_SWC_MemMap.h"
