# WDG Driver Details

## /**********************************Section 1: HW-SW Map******************************************/

Table 1: Configured Groups

WDT | Safety Level
WDG 0 | QM
WDG 1 | QM

## /*******************************Section 2: MPU Settings*******************************************/

Table 1: WDG SFR channel

TIMER | GTM Module | Module no | Channel no
WDG0 | TOM | 0 | 2
| WDG1 | TOM | 0 | 8

Table 2: WDG SFR and Memory Range

Timer | Section Start Address | Section End Address | Remarks
WDG0 | SCU_WDTCPU0_CON0 | SCU_WDTCPU0_SR | WDG0 password and reload value setting
GTM_TOM0_CH2_CM0 | GTM_TOM0_CH2_SR0 | Includes Counter Registers,Compare 0 Registers and Shadow 0 Registers of configured TOM Channels
GTM_TOM0_TGC0_ENDIS_STAT | GTM_TOM0_TGC1_ENDIS_STAT |
- Includes SFR's to enable or disable TOMx channels
- Number of channels in each TOMx is x =0-15
- Number of TOMx.. where x=0,1
WDG1 | SCU_WDTCPU1_CON0 | SCU_WDTCPU1_SR | WDG1 password and reload value setting
GTM_TOM0_CH8_CM0 | GTM_TOM0_CH8_SR0 | Includes Counter Registers,Compare 0 Registers and Shadow 0 Registers of configured TOM Channels
GTM_TOM0_TGC0_ENDIS_STAT | GTM_TOM0_TGC1_ENDIS_STAT |
- Includes SFR's to enable or disable TOMx channels
- Number of channels in each TOMx is x =0-15
- Number of TOMx.. where x=0,1

Table 3: WDG Code and Memory Range

Section Start Address | Section End Address | Remarks
WDG_17_SCU_START_SEC_VAR_32BIT | WDG_17_SCU_STOP_SEC_VAR_32BIT | Wdg_kConfigPtr,WdgPBFixedAddress == STD_OFF
WDG_17_SCU_START_SEC_VAR_16BIT | WDG_17_SCU_STOP_SEC_VAR_16BIT | WDG driver variable setting (only for AUTOSAR functionality)
WDG_17_SCU_START_SEC_CODE | WDG_17_SCU_STOP_SEC_CODE | WDG driver-Basic AUTOSAR & Safety functionality
WDG_17_SCU_START_SEC_VAR_UNSPECIFIED | WDG_17_SCU_STOP_SEC_VAR_UNSPECIFIED | WDG driver current mode and state(only for AUTOSAR function)

Table 4: WDG SFR Usage

API Name | SFRs Used | Remarks
Wdg_17_Scu_Init | SCU_WDTCPUxCON1, SCU_WDTCPUxCON0, SCU_WDTCPUxSR | x-holds corresponding CPU WDG
Wdg_17_Scu_SetMode | SCU_WDTCPUxCON1, SCU_WDTCPUxCON0 | x-holds corresponding CPU WDG
Wdg_17_Scu_SetTriggerCondition | SCU_WDTCPUxCON0 | x-holds corresponding CPU WDG
Wdg_17_Scu_SafeTrigger | SCU_WDTCPUxCON0 | x-holds corresponding CPU WDG
Wdg_17_Scu_SetOffMode | SCU_WDTCPUxCON1, SCU_WDTCPUxCON0 | x-holds corresponding CPU WDG

## /***************************Section 3: Periodic SFR Check For WDG***************************************/

Table 1: WDG CON1 SFR

Register Name | Value
SCU_WDTCPU0_CON1 | 0x00000000U
SCU_WDTCPU1_CON1 | 0x00000008U